2 * Copyright (C) 2006 Atmel Corporation
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 #ifndef __ASM_AVR32_ARCH_CLK_H__
23 #define __ASM_AVR32_ARCH_CLK_H__
25 #include <asm/arch/chip-features.h>
26 #include <asm/arch/portmux.h>
29 #define PLL0_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL)
30 #define MAIN_CLK_RATE PLL0_RATE
32 #define MAIN_CLK_RATE (CFG_OSC0_HZ)
35 static inline unsigned long get_cpu_clk_rate(void)
37 return MAIN_CLK_RATE >> CFG_CLKDIV_CPU;
39 static inline unsigned long get_hsb_clk_rate(void)
41 return MAIN_CLK_RATE >> CFG_CLKDIV_HSB;
43 static inline unsigned long get_pba_clk_rate(void)
45 return MAIN_CLK_RATE >> CFG_CLKDIV_PBA;
47 static inline unsigned long get_pbb_clk_rate(void)
49 return MAIN_CLK_RATE >> CFG_CLKDIV_PBB;
52 /* Accessors for specific devices. More will be added as needed. */
53 static inline unsigned long get_sdram_clk_rate(void)
55 return get_hsb_clk_rate();
57 #ifdef AT32AP700x_CHIP_HAS_USART
58 static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
60 return get_pba_clk_rate();
63 #ifdef AT32AP700x_CHIP_HAS_MACB
64 static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
66 return get_pbb_clk_rate();
68 static inline unsigned long get_macb_hclk_rate(unsigned int dev_id)
70 return get_hsb_clk_rate();
73 #ifdef AT32AP700x_CHIP_HAS_MMCI
74 static inline unsigned long get_mci_clk_rate(void)
76 return get_pbb_clk_rate();
79 #ifdef AT32AP700x_CHIP_HAS_SPI
80 static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
82 return get_pba_clk_rate();
86 extern void clk_init(void);
87 extern void gclk_init(void) __attribute__((weak));
89 /* Board code may need the SDRAM base clock as a compile-time constant */
90 #define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CFG_CLKDIV_HSB)
92 /* Generic clock control */
100 /* Some generic clocks have specific roles */
101 #define GCLK_DAC_SAMPLE_CLK 6
102 #define GCLK_LCDC_PIXCLK 7
104 extern unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent,
105 unsigned long rate, unsigned long parent_rate);
108 * gclk_set_rate - configure and enable a generic clock
109 * @id: Which GCLK[id] to enable
110 * @parent: Parent clock feeding the GCLK
111 * @rate: Target rate of the GCLK in Hz
113 * Returns the actual GCLK rate in Hz, after rounding to the nearest
116 * All three parameters are usually constant, hence the inline.
118 static inline unsigned long gclk_set_rate(unsigned int id,
119 enum gclk_parent parent, unsigned long rate)
121 unsigned long parent_rate;
127 case GCLK_PARENT_OSC0:
128 parent_rate = CFG_OSC0_HZ;
131 case GCLK_PARENT_OSC1:
132 parent_rate = CFG_OSC1_HZ;
136 case GCLK_PARENT_PLL0:
137 parent_rate = PLL0_RATE;
141 case GCLK_PARENT_PLL1:
142 parent_rate = PLL1_RATE;
150 return __gclk_set_rate(id, parent, rate, parent_rate);
154 * gclk_enable_output - enable output on a GCLK pin
155 * @id: Which GCLK[id] pin to enable
156 * @drive_strength: Drive strength of external GCLK pin, if applicable
158 static inline void gclk_enable_output(unsigned int id,
159 unsigned long drive_strength)
163 portmux_select_peripheral(PORTMUX_PORT_A, 1 << 30,
164 PORTMUX_FUNC_A, drive_strength);
167 portmux_select_peripheral(PORTMUX_PORT_A, 1 << 31,
168 PORTMUX_FUNC_A, drive_strength);
171 portmux_select_peripheral(PORTMUX_PORT_B, 1 << 19,
172 PORTMUX_FUNC_A, drive_strength);
175 portmux_select_peripheral(PORTMUX_PORT_B, 1 << 29,
176 PORTMUX_FUNC_A, drive_strength);
179 portmux_select_peripheral(PORTMUX_PORT_B, 1 << 30,
180 PORTMUX_FUNC_A, drive_strength);
185 #endif /* __ASM_AVR32_ARCH_CLK_H__ */