2 * File: include/asm-blackfin/arch-bf537/anomaly.h
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
31 /* This file shoule be up to date with:
32 * - Revision J, June 1, 2006; ADSP-BF537 Blackfin Processor Anomaly List
33 * - Revision I, June 1, 2006; ADSP-BF536 Blackfin Processor Anomaly List
34 * - Revision J, June 1, 2006; ADSP-BF534 Blackfin Processor Anomaly List
37 #ifndef _MACH_ANOMALY_H_
38 #define _MACH_ANOMALY_H_
40 /* We do not support 0.1 silicon - sorry */
41 #if (defined(CONFIG_BF_REV_0_1))
42 #error Kernel will not work on BF537/6/4 Version 0.1
45 #if (defined(CONFIG_BF_REV_0_3) || defined(CONFIG_BF_REV_0_2))
46 #define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
47 slot1 and store of a P register in slot 2 is not
49 #define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
51 #define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
53 #define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
55 #define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
57 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
58 #define ANOMALY_05000247 /* CLKIN Buffer Output Enable Reset Behavior Is
61 #define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
62 SPORT external receive and transmit clocks. */
63 #define ANOMALY_05000272 /* Certain data cache write through modes fail for
65 #define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
66 #define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
67 an edge is detected may clear interrupt */
68 #define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
70 #define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
72 #define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
73 killed in a particular stage */
76 #if defined(CONFIG_BF_REV_0_2)
77 #define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
78 IDLE around a Change of Control causes
79 unpredictable results */
80 #define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
82 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
83 #define ANOMALY_05000252 /* EMAC Tx DMA error after an early frame abort */
85 #define ANOMALY_05000253 /* Maximum external clock speed for Timers */
86 #define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
87 interrupt not functional */
88 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
89 #define ANOMALY_05000256 /* EMAC MDIO input latched on wrong MDC edge */
91 #define ANOMALY_05000257 /* An interrupt or exception during short Hardware
92 loops may cause the instruction fetch unit to
94 #define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
95 the ICPLB Data registers differ */
96 #define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
97 #define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
98 #define ANOMALY_05000262 /* Stores to data cache may be lost */
99 #define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
100 #define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
101 instruction will cause an infinite stall in the
102 second to last instruction in a hardware loop */
103 #define ANOMALY_05000268 /* Memory DMA error when peripheral DMA is running
104 and non-zero DEB_TRAFFIC_PERIOD value */
105 #define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
106 internal voltage regulator (VDDint) to decrease */
107 #define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
108 an edge is detected may clear interrupt */
109 #define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
110 DMA system instability */
111 #define ANOMALY_05000280 /* SPI Master boot mode does not work well with
112 Atmel Dataflash devices */
114 #endif /* CONFIG_BF_REV_0_2 */
116 #endif /* _MACH_ANOMALY_H_ */