git.sur5r.net Git - u-boot/blob - include/asm-blackfin/cplbtab.h

   1 /*This file is subject to the terms and conditions of the GNU General Public
   2  * License.
   3  *
   4  * Blackfin BF533/2.6 support : LG Soft India
   5  * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd
   6  * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's
   7  *              shouldn't be victimized. cplbmgr.S search logic is corrected
   8  *              to findout the appropriate victim.
   9  *           2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC
  10  *           : LG Soft India
  11  */
  12 #include <config.h>
  13
  14 #ifndef __ARCH_BFINNOMMU_CPLBTAB_H
  15 #define __ARCH_BFINNOMMU_CPLBTAB_H
  16
  17 /*************************************************************************
  18  *                      ICPLB TABLE
  19  *************************************************************************/
  20
  21 .data
  22
  23 /* This table is configurable */
  24
  25 .align 4;
  26
  27 /* Data Attibutes*/
  28
  29 #define SDRAM_IGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
  30 #define SDRAM_IKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
  31 #define L1_IMEMORY              (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
  32 #define SDRAM_INON_CHBL         (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
  33
  34 /*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
  35
  36 #define ANOMALY_05000158                0x200
  37 #ifdef CONFIG_BLKFIN_WB         /*Write Back Policy */
  38         #define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
  39         #define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
  40         #define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
  41         #define L1_DMEMORY              (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
  42         #define SDRAM_EBIU              (PAGE_SIZE_1MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
  43
  44 #else  /*Write Through*/
  45         #define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
  46         #define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
  47         #define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
  48         #define L1_DMEMORY              (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
  49         #define SDRAM_EBIU              (PAGE_SIZE_1MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
  50 #endif
  51
  52 .global icplb_table
  53 icplb_table:
  54 .byte4 0xFFA00000;
  55 .byte4 (L1_IMEMORY);
  56 .byte4 0x00000000;
  57 .byte4 (SDRAM_IKERNEL);                 /*SDRAM_Page1*/
  58 .byte4 0x00400000;
  59 .byte4 (SDRAM_IKERNEL);         /*SDRAM_Page1*/
  60 .byte4 0x07C00000;
  61 .byte4 (SDRAM_IKERNEL);         /*SDRAM_Page14*/
  62 .byte4 0x00800000;
  63 .byte4 (SDRAM_IGENERIC);                /*SDRAM_Page2*/
  64 .byte4 0x00C00000;
  65 .byte4 (SDRAM_IGENERIC);                /*SDRAM_Page2*/
  66 .byte4 0x01000000;
  67 .byte4 (SDRAM_IGENERIC);                /*SDRAM_Page4*/
  68 .byte4 0x01400000;
  69 .byte4 (SDRAM_IGENERIC);                /*SDRAM_Page5*/
  70 .byte4 0x01800000;
  71 .byte4 (SDRAM_IGENERIC);                /*SDRAM_Page6*/
  72 .byte4 0x01C00000;
  73 .byte4 (SDRAM_IGENERIC);                /*SDRAM_Page7*/
  74 #ifndef CONFIG_EZKIT                    /*STAMP Memory regions*/
  75 .byte4 0x02000000;
  76 .byte4 (SDRAM_IGENERIC);                /*SDRAM_Page8*/
  77 .byte4 0x02400000;
  78 .byte4 (SDRAM_IGENERIC);                /*SDRAM_Page9*/
  79 .byte4 0x02800000;
  80 .byte4 (SDRAM_IGENERIC);                /*SDRAM_Page10*/
  81 .byte4 0x02C00000;
  82 .byte4 (SDRAM_IGENERIC);                /*SDRAM_Page11*/
  83 .byte4 0x03000000;
  84 .byte4 (SDRAM_IGENERIC);                /*SDRAM_Page12*/
  85 .byte4 0x03400000;
  86 .byte4 (SDRAM_IGENERIC);                /*SDRAM_Page13*/
  87 #endif
  88 .byte4 0xffffffff;                      /* end of section - termination*/
  89
  90 .align 4;
  91 .global ipdt_table
  92 ipdt_table:
  93 #ifdef CONFIG_CPLB_INFO
  94 .byte4 0x00000000;
  95 .byte4 (SDRAM_IKERNEL);               /*SDRAM_Page0*/
  96 .byte4 0x00400000;
  97 .byte4 (SDRAM_IKERNEL);               /*SDRAM_Page1*/
  98 #endif
  99 .byte4 0x00800000;
 100 .byte4 (SDRAM_IGENERIC);              /*SDRAM_Page2*/
 101 .byte4 0x00C00000;
 102 .byte4 (SDRAM_IGENERIC);              /*SDRAM_Page3*/
 103 .byte4 0x01000000;
 104 .byte4 (SDRAM_IGENERIC);              /*SDRAM_Page4*/
 105 .byte4 0x01400000;
 106 .byte4 (SDRAM_IGENERIC);              /*SDRAM_Page5*/
 107 .byte4 0x01800000;
 108 .byte4 (SDRAM_IGENERIC);              /*SDRAM_Page6*/
 109 .byte4 0x01C00000;
 110 .byte4 (SDRAM_IGENERIC);              /*SDRAM_Page7*/
 111 #ifndef CONFIG_EZKIT                  /*STAMP Memory regions*/
 112 .byte4  0x02000000;
 113 .byte4  (SDRAM_IGENERIC);              /*SDRAM_Page8*/
 114 .byte4  0x02400000;
 115 .byte4  (SDRAM_IGENERIC);              /*SDRAM_Page9*/
 116 .byte4  0x02800000;
 117 .byte4  (SDRAM_IGENERIC);              /*SDRAM_Page10*/
 118 .byte4  0x02C00000;
 119 .byte4  (SDRAM_IGENERIC);              /*SDRAM_Page11*/
 120 .byte4  0x03000000;
 121 .byte4  (SDRAM_IGENERIC);              /*SDRAM_Page12*/
 122 .byte4  0x03400000;
 123 .byte4  (SDRAM_IGENERIC);              /*SDRAM_Page13*/
 124 .byte4  0x03800000;
 125 .byte4  (SDRAM_IGENERIC);              /*SDRAM_Page14*/
 126 .byte4  0x03C00000;
 127 .byte4  (SDRAM_IGENERIC);              /*SDRAM_Page15*/
 128 #endif
 129 .byte4  0x20200000;
 130 .byte4  (SDRAM_EBIU);      /* Async Memory Bank 2 (Secnd)*/
 131 .byte4  0x20100000;
 132 .byte4  (SDRAM_EBIU);      /* Async Memory Bank 1 (Prim B)*/
 133 .byte4  0x20000000;
 134 .byte4  (SDRAM_EBIU);      /* Async Memory Bank 0 (Prim A)*/
 135 .byte4  0x20300000;             /*Fix for Network*/
 136 .byte4  (SDRAM_EBIU);    /*Async Memory bank 3*/
 137
 138 #ifdef CONFIG_STAMP
 139 .byte4        0x04000000;
 140 .byte4  (SDRAM_IGENERIC);
 141 .byte4        0x04400000;
 142 .byte4  (SDRAM_IGENERIC);
 143 .byte4        0x04800000;
 144 .byte4  (SDRAM_IGENERIC);
 145 .byte4        0x04C00000;
 146 .byte4  (SDRAM_IGENERIC);
 147 .byte4        0x05000000;
 148 .byte4  (SDRAM_IGENERIC);
 149 .byte4        0x05400000;
 150 .byte4  (SDRAM_IGENERIC);
 151 .byte4        0x05800000;
 152 .byte4  (SDRAM_IGENERIC);
 153 .byte4        0x05C00000;
 154 .byte4  (SDRAM_IGENERIC);
 155 .byte4        0x06000000;
 156 .byte4  (SDRAM_IGENERIC);       /*SDRAM_Page25*/
 157 .byte4        0x06400000;
 158 .byte4  (SDRAM_IGENERIC);       /*SDRAM_Page26*/
 159 .byte4        0x06800000;
 160 .byte4  (SDRAM_IGENERIC);       /*SDRAM_Page27*/
 161 .byte4        0x06C00000;
 162 .byte4  (SDRAM_IGENERIC);       /*SDRAM_Page28*/
 163 .byte4        0x07000000;
 164 .byte4  (SDRAM_IGENERIC);       /*SDRAM_Page29*/
 165 .byte4        0x07400000;
 166 .byte4  (SDRAM_IGENERIC);       /*SDRAM_Page30*/
 167 .byte4        0x07800000;
 168 .byte4  (SDRAM_IGENERIC);       /*SDRAM_Page31*/
 169 #ifdef CONFIG_CPLB_INFO
 170 .byte4        0x07C00000;
 171 .byte4  (SDRAM_IKERNEL);        /*SDRAM_Page32*/
 172 #endif
 173 #endif
 174 .byte4 0xffffffff;                    /* end of section - termination*/
 175
 176 /*********************************************************************
 177  *                      DCPLB TABLE
 178  ********************************************************************/
 179
 180 .global dcplb_table
 181 dcplb_table:
 182 .byte4  0x00000000;
 183 .byte4  (SDRAM_DKERNEL);        /*SDRAM_Page1*/
 184 .byte4  0x00400000;
 185 .byte4  (SDRAM_DKERNEL);        /*SDRAM_Page1*/
 186 .byte4  0x07C00000;
 187 .byte4  (SDRAM_DKERNEL);        /*SDRAM_Page15*/
 188 .byte4  0x00800000;
 189 .byte4  (SDRAM_DGENERIC);       /*SDRAM_Page2*/
 190 .byte4  0x00C00000;
 191 .byte4  (SDRAM_DGENERIC);       /*SDRAM_Page3*/
 192 .byte4  0x01000000;
 193 .byte4  (SDRAM_DGENERIC);       /*SDRAM_Page4*/
 194 .byte4  0x01400000;
 195 .byte4  (SDRAM_DGENERIC);       /*SDRAM_Page5*/
 196 .byte4  0x01800000;
 197 .byte4  (SDRAM_DGENERIC);       /*SDRAM_Page6*/
 198 .byte4  0x01C00000;
 199 .byte4  (SDRAM_DGENERIC);       /*SDRAM_Page7*/
 200 #ifndef CONFIG_EZKIT
 201 .byte4  0x02000000;
 202 .byte4  (SDRAM_DGENERIC);       /*SDRAM_Page8*/
 203 .byte4  0x02400000;
 204 .byte4  (SDRAM_DGENERIC);       /*SDRAM_Page9*/
 205 .byte4  0x02800000;
 206 .byte4  (SDRAM_DGENERIC);       /*SDRAM_Page10*/
 207 .byte4  0x02C00000;
 208 .byte4  (SDRAM_DGENERIC);       /*SDRAM_Page11*/
 209 .byte4  0x03000000;
 210 .byte4  (SDRAM_DGENERIC);       /*SDRAM_Page12*/
 211 .byte4  0x03400000;
 212 .byte4  (SDRAM_DGENERIC);       /*SDRAM_Page13*/
 213 .byte4  0x03800000;
 214 .byte4  (SDRAM_DGENERIC);       /*SDRAM_Page14*/
 215 #endif
 216 .byte4  0xffffffff;             /*end of section - termination*/
 217
 218 /**********************************************************************
 219  *              PAGE DESCRIPTOR TABLE
 220  *
 221  **********************************************************************/
 222
 223 /* Till here we are discussing about the static memory management model.
 224  * However, the operating envoronments commonly define more CPLB
 225  * descriptors to cover the entire addressable memory than will fit into
 226  * the available on-chip 16 CPLB MMRs. When this happens, the below table
 227  * will be used which will hold all the potentially required CPLB descriptors
 228  *
 229  * This is how Page descriptor Table is implemented in uClinux/Blackfin.
 230  */
 231 .global dpdt_table
 232 dpdt_table:
 233 #ifdef CONFIG_CPLB_INFO
 234 .byte4        0x00000000;
 235 .byte4        (SDRAM_DKERNEL);        /*SDRAM_Page0*/
 236 .byte4        0x00400000;
 237 .byte4        (SDRAM_DKERNEL);        /*SDRAM_Page1*/
 238 #endif
 239 .byte4        0x00800000;
 240 .byte4        (SDRAM_DGENERIC);       /*SDRAM_Page2*/
 241 .byte4        0x00C00000;
 242 .byte4        (SDRAM_DGENERIC);       /*SDRAM_Page3*/
 243 .byte4        0x01000000;
 244 .byte4        (SDRAM_DGENERIC);       /*SDRAM_Page4*/
 245 .byte4        0x01400000;
 246 .byte4        (SDRAM_DGENERIC);       /*SDRAM_Page5*/
 247 .byte4        0x01800000;
 248 .byte4        (SDRAM_DGENERIC);       /*SDRAM_Page6*/
 249 .byte4        0x01C00000;
 250 .byte4        (SDRAM_DGENERIC);       /*SDRAM_Page7*/
 251
 252 #ifndef CONFIG_EZKIT
 253 .byte4        0x02000000;
 254 .byte4        (SDRAM_DGENERIC);       /*SDRAM_Page8*/
 255 .byte4        0x02400000;
 256 .byte4        (SDRAM_DGENERIC);       /*SDRAM_Page9*/
 257 .byte4        0x02800000;
 258 .byte4        (SDRAM_DGENERIC);       /*SDRAM_Page10*/
 259 .byte4        0x02C00000;
 260 .byte4        (SDRAM_DGENERIC);       /*SDRAM_Page11*/
 261 .byte4        0x03000000;
 262 .byte4        (SDRAM_DGENERIC);       /*SDRAM_Page12*/
 263 .byte4        0x03400000;
 264 .byte4        (SDRAM_DGENERIC);       /*SDRAM_Page13*/
 265 .byte4        0x03800000;
 266 .byte4        (SDRAM_DGENERIC);       /*SDRAM_Page14*/
 267 .byte4        0x03C00000;
 268 .byte4        (SDRAM_DGENERIC);       /*SDRAM_Page15*/
 269 #endif
 270 .byte4  0x20200000;
 271 .byte4  (SDRAM_EBIU);   /* Async Memory Bank 2 (Secnd)*/
 272 .byte4  0x20100000;
 273 .byte4  (SDRAM_EBIU);   /* Async Memory Bank 1 (Prim B)*/
 274 .byte4  0x20000000;
 275 .byte4  (SDRAM_EBIU);   /* Async Memory Bank 0 (Prim A)*/
 276 .byte4  0x20300000;             /*Fix for Network*/
 277 .byte4  (SDRAM_EBIU);   /*Async Memory bank 3*/
 278
 279 #ifdef CONFIG_STAMP
 280 .byte4  0x04000000;
 281 .byte4  (SDRAM_DGENERIC);
 282 .byte4  0x04400000;
 283 .byte4  (SDRAM_DGENERIC);
 284 .byte4  0x04800000;
 285 .byte4  (SDRAM_DGENERIC);
 286 .byte4  0x04C00000;
 287 .byte4  (SDRAM_DGENERIC);
 288 .byte4  0x05000000;
 289 .byte4  (SDRAM_DGENERIC);
 290 .byte4  0x05400000;
 291 .byte4  (SDRAM_DGENERIC);
 292 .byte4  0x05800000;
 293 .byte4  (SDRAM_DGENERIC);
 294 .byte4  0x05C00000;
 295 .byte4  (SDRAM_DGENERIC);
 296 .byte4  0x06000000;
 297 .byte4  (SDRAM_DGENERIC);       /*SDRAM_Page25*/
 298 .byte4  0x06400000;
 299 .byte4  (SDRAM_DGENERIC);       /*SDRAM_Page26*/
 300 .byte4  0x06800000;
 301 .byte4  (SDRAM_DGENERIC);       /*SDRAM_Page27*/
 302 .byte4  0x06C00000;
 303 .byte4  (SDRAM_DGENERIC);       /*SDRAM_Page28*/
 304 .byte4  0x07000000;
 305 .byte4  (SDRAM_DGENERIC);       /*SDRAM_Page29*/
 306 .byte4  0x07400000;
 307 .byte4  (SDRAM_DGENERIC);       /*SDRAM_Page30*/
 308 .byte4  0x07800000;
 309 .byte4  (SDRAM_DGENERIC);       /*SDRAM_Page31*/
 310 #ifdef CONFIG_CPLB_INFO
 311 .byte4  0x07C00000;
 312 .byte4  (SDRAM_DKERNEL);        /*SDRAM_Page32*/
 313 #endif
 314 #endif
 315
 316 .byte4  0xFF900000;
 317 .byte4  (L1_DMEMORY);
 318 .byte4  0xFF901000;
 319 .byte4  (L1_DMEMORY);
 320 .byte4  0xFF902000;
 321 .byte4  (L1_DMEMORY);
 322 .byte4  0xFF903000;
 323 .byte4  (L1_DMEMORY);
 324 .byte4  0xFF904000;
 325 .byte4  (L1_DMEMORY);
 326 .byte4  0xFF905000;
 327 .byte4  (L1_DMEMORY);
 328 .byte4  0xFF906000;
 329 .byte4  (L1_DMEMORY);
 330 .byte4  0xFF907000;
 331 .byte4  (L1_DMEMORY);
 332 .byte4  0xFF800000;
 333 .byte4  (L1_DMEMORY);
 334 .byte4  0xFF801000;
 335 .byte4  (L1_DMEMORY);
 336 .byte4  0xFF802000;
 337 .byte4  (L1_DMEMORY);
 338 .byte4  0xFF803000;
 339 .byte4  (L1_DMEMORY);
 340
 341 .byte4  0xffffffff;             /*end of section - termination*/
 342
 343 #ifdef CONFIG_CPLB_INFO
 344 .global ipdt_swapcount_table;   /* swapin count first, then swapout count*/
 345 ipdt_swapcount_table:
 346 .byte4        0x00000000;
 347 .byte4        0x00000000;
 348 .byte4        0x00000000;
 349 .byte4        0x00000000;
 350 .byte4        0x00000000;
 351 .byte4        0x00000000;
 352 .byte4        0x00000000;
 353 .byte4        0x00000000;
 354 .byte4        0x00000000;
 355 .byte4        0x00000000;       /* 10 */
 356 .byte4        0x00000000;
 357 .byte4        0x00000000;
 358 .byte4        0x00000000;
 359 .byte4        0x00000000;
 360 .byte4        0x00000000;
 361 .byte4        0x00000000;
 362 .byte4        0x00000000;
 363 .byte4        0x00000000;
 364 .byte4        0x00000000;
 365 .byte4        0x00000000;       /* 20 */
 366 .byte4        0x00000000;
 367 .byte4        0x00000000;
 368 .byte4        0x00000000;
 369 .byte4        0x00000000;
 370 .byte4        0x00000000;
 371 .byte4        0x00000000;
 372 .byte4        0x00000000;
 373 .byte4        0x00000000;
 374 .byte4        0x00000000;
 375 .byte4        0x00000000;       /* 30 */
 376 .byte4        0x00000000;
 377 .byte4        0x00000000;
 378 .byte4        0x00000000;
 379 .byte4        0x00000000;
 380 .byte4        0x00000000;
 381 .byte4        0x00000000;
 382 .byte4        0x00000000;
 383 .byte4        0x00000000;
 384 .byte4        0x00000000;
 385 .byte4        0x00000000;       /* 40 */
 386 .byte4        0x00000000;
 387 .byte4        0x00000000;
 388 .byte4        0x00000000;
 389 .byte4        0x00000000;
 390 .byte4        0x00000000;
 391 .byte4        0x00000000;
 392 .byte4        0x00000000;
 393 .byte4        0x00000000;
 394 .byte4        0x00000000;
 395 .byte4        0x00000000;       /* 50 */
 396 .byte4        0x00000000;
 397 .byte4        0x00000000;
 398 .byte4        0x00000000;
 399 .byte4        0x00000000;
 400 .byte4        0x00000000;
 401 .byte4        0x00000000;
 402 .byte4        0x00000000;
 403 .byte4        0x00000000;
 404 .byte4        0x00000000;
 405 .byte4        0x00000000;       /* 60 */
 406 .byte4        0x00000000;
 407 .byte4        0x00000000;
 408 .byte4        0x00000000;
 409 .byte4        0x00000000;
 410 .byte4        0x00000000;
 411 .byte4        0x00000000;
 412 .byte4        0x00000000;
 413 .byte4        0x00000000;
 414 .byte4        0x00000000;
 415 .byte4        0x00000000;       /* 70 */
 416 .byte4        0x00000000;
 417 .byte4        0x00000000;
 418 .byte4        0x00000000;
 419 .byte4        0x00000000;
 420 .byte4        0x00000000;
 421 .byte4        0x00000000;
 422 .byte4        0x00000000;
 423 .byte4        0x00000000;
 424 .byte4        0x00000000;
 425 .byte4        0x00000000;       /* 80 */
 426 .byte4        0x00000000;
 427 .byte4        0x00000000;
 428 .byte4        0x00000000;
 429 .byte4        0x00000000;
 430 .byte4        0x00000000;
 431 .byte4        0x00000000;
 432 .byte4        0x00000000;
 433 .byte4        0x00000000;
 434 .byte4        0x00000000;
 435 .byte4        0x00000000;       /* 90 */
 436 .byte4        0x00000000;
 437 .byte4        0x00000000;
 438 .byte4        0x00000000;
 439 .byte4        0x00000000;
 440 .byte4        0x00000000;
 441 .byte4        0x00000000;
 442 .byte4        0x00000000;
 443 .byte4        0x00000000;
 444 .byte4        0x00000000;
 445 .byte4        0x00000000;       /* 100 */
 446
 447 .global dpdt_swapcount_table;   /* swapin count first, then swapout count*/
 448 dpdt_swapcount_table:
 449 .byte4        0x00000000;
 450 .byte4        0x00000000;
 451 .byte4        0x00000000;
 452 .byte4        0x00000000;
 453 .byte4        0x00000000;
 454 .byte4        0x00000000;
 455 .byte4        0x00000000;
 456 .byte4        0x00000000;
 457 .byte4        0x00000000;
 458 .byte4        0x00000000;       /* 10 */
 459 .byte4        0x00000000;
 460 .byte4        0x00000000;
 461 .byte4        0x00000000;
 462 .byte4        0x00000000;
 463 .byte4        0x00000000;
 464 .byte4        0x00000000;
 465 .byte4        0x00000000;
 466 .byte4        0x00000000;
 467 .byte4        0x00000000;
 468 .byte4        0x00000000;       /* 20 */
 469 .byte4        0x00000000;
 470 .byte4        0x00000000;
 471 .byte4        0x00000000;
 472 .byte4        0x00000000;
 473 .byte4        0x00000000;
 474 .byte4        0x00000000;
 475 .byte4        0x00000000;
 476 .byte4        0x00000000;
 477 .byte4        0x00000000;
 478 .byte4        0x00000000;       /* 30 */
 479 .byte4        0x00000000;
 480 .byte4        0x00000000;
 481 .byte4        0x00000000;
 482 .byte4        0x00000000;
 483 .byte4        0x00000000;
 484 .byte4        0x00000000;
 485 .byte4        0x00000000;
 486 .byte4        0x00000000;
 487 .byte4        0x00000000;
 488 .byte4        0x00000000;       /* 40 */
 489 .byte4        0x00000000;
 490 .byte4        0x00000000;
 491 .byte4        0x00000000;
 492 .byte4        0x00000000;
 493 .byte4        0x00000000;
 494 .byte4        0x00000000;
 495 .byte4        0x00000000;
 496 .byte4        0x00000000;
 497 .byte4        0x00000000;
 498 .byte4        0x00000000;       /* 50 */
 499 .byte4        0x00000000;
 500 .byte4        0x00000000;
 501 .byte4        0x00000000;
 502 .byte4        0x00000000;
 503 .byte4        0x00000000;
 504 .byte4        0x00000000;
 505 .byte4        0x00000000;
 506 .byte4        0x00000000;
 507 .byte4        0x00000000;
 508 .byte4        0x00000000;       /* 60 */
 509 .byte4        0x00000000;
 510 .byte4        0x00000000;
 511 .byte4        0x00000000;
 512 .byte4        0x00000000;
 513 .byte4        0x00000000;
 514 .byte4        0x00000000;
 515 .byte4        0x00000000;
 516 .byte4        0x00000000;
 517 .byte4        0x00000000;
 518 .byte4        0x00000000;       /* 70 */
 519 .byte4        0x00000000;
 520 .byte4        0x00000000;
 521 .byte4        0x00000000;
 522 .byte4        0x00000000;
 523 .byte4        0x00000000;
 524 .byte4        0x00000000;
 525 .byte4        0x00000000;
 526 .byte4        0x00000000;
 527 .byte4        0x00000000;
 528 .byte4        0x00000000;       /* 80 */
 529 .byte4        0x00000000;
 530 .byte4        0x00000000;
 531 .byte4        0x00000000;
 532 .byte4        0x00000000;
 533 .byte4        0x00000000;
 534 .byte4        0x00000000;
 535 .byte4        0x00000000;
 536 .byte4        0x00000000;
 537 .byte4        0x00000000;
 538 .byte4        0x00000000;       /* 80 */
 539 .byte4        0x00000000;
 540 .byte4        0x00000000;
 541 .byte4        0x00000000;
 542 .byte4        0x00000000;
 543 .byte4        0x00000000;
 544 .byte4        0x00000000;
 545 .byte4        0x00000000;
 546 .byte4        0x00000000;
 547 .byte4        0x00000000;
 548 .byte4        0x00000000;       /* 100 */
 549 .byte4        0x00000000;
 550 .byte4        0x00000000;
 551 .byte4        0x00000000;
 552 .byte4        0x00000000;
 553 .byte4        0x00000000;
 554 .byte4        0x00000000;
 555 .byte4        0x00000000;
 556 .byte4        0x00000000;
 557 .byte4        0x00000000;
 558 .byte4        0x00000000;       /* 110 */
 559 .byte4        0x00000000;
 560 .byte4        0x00000000;
 561 .byte4        0x00000000;
 562 .byte4        0x00000000;
 563 .byte4        0x00000000;
 564 .byte4        0x00000000;
 565 .byte4        0x00000000;
 566 .byte4        0x00000000;
 567 .byte4        0x00000000;
 568 .byte4        0x00000000;       /* 120 */
 569
 570 #endif
 571
 572 #endif  /*__ARCH_BFINNOMMU_CPLBTAB_H*/