4 * Copyright (c) 2005 blackfin.uclinux.org
6 * This file is based on
7 * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c
8 * Changed by HuTao Apr18, 2003
10 * Copyright was missing when I got the code so took from MIPS arch ...MaTed---
11 * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
12 * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle
14 * Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca>
15 * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
16 * Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com>
18 * Adapted for BlackFin BF533 by Bas Vermeulen <bas@buyways.nl>
19 * Copyright (c) 2003 BuyWays B.V. (www.buyways.nl)
21 * See file CREDITS for list of people who contributed to this
24 * This program is free software; you can redistribute it and/or
25 * modify it under the terms of the GNU General Public License as
26 * published by the Free Software Foundation; either version 2 of
27 * the License, or (at your option) any later version.
29 * This program is distributed in the hope that it will be useful,
30 * but WITHOUT ANY WARRANTY; without even the implied warranty of
31 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
32 * GNU General Public License for more details.
34 * You should have received a copy of the GNU General Public License
35 * along with this program; if not, write to the Free Software
36 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
44 * Interrupt source definitions
45 * Event Source Core Event Name Number
51 * Hardware Error IVHW 5
53 * PLL Wakeup Interrupt IVG7 7
54 * DMA Error (generic) IVG7 8
55 * PPI Error Interrupt IVG7 9
56 * SPORT0 Error Interrupt IVG7 10
57 * SPORT1 Error Interrupt IVG7 11
58 * SPI Error Interrupt IVG7 12
59 * UART Error Interrupt IVG7 13
60 * RTC Interrupt IVG8 14
61 * DMA0 Interrupt (PPI) IVG8 15
62 * DMA1 (SPORT0 RX) IVG9 16
63 * DMA2 (SPORT0 TX) IVG9 17
64 * DMA3 (SPORT1 RX) IVG9 18
65 * DMA4 (SPORT1 TX) IVG9 19
67 * DMA6 (UART RX) IVG10 21
68 * DMA7 (UART TX) IVG10 22
72 * PF Interrupt A IVG12 26
73 * PF Interrupt B IVG12 27
74 * DMA8/9 Interrupt IVG13 28
75 * DMA10/11 Interrupt IVG13 29
76 * Watchdog Timer IVG13 30
77 * Software Interrupt 1 IVG14 31
78 * Software Interrupt 2 --
79 * (lowest priority) IVG15 32
82 /* The ABSTRACT IRQ definitions */
84 /* The first seven of the following are fixed,
85 * the rest you change if you need to
88 #define IRQ_EMU 0 /* Emulation */
89 #define IRQ_RST 1 /* reset */
90 #define IRQ_NMI 2 /* Non Maskable */
91 #define IRQ_EVX 3 /* Exception */
92 #define IRQ_UNUSED 4 /* - unused interrupt */
93 #define IRQ_HWERR 5 /* Hardware Error */
94 #define IRQ_CORETMR 6 /* Core timer */
95 #define IRQ_PLL_WAKEUP 7 /* PLL Wakeup Interrupt */
96 #define IRQ_DMA_ERROR 8 /* DMA Error (general) */
97 #define IRQ_PPI_ERROR 9 /* PPI Error Interrupt */
98 #define IRQ_SPORT0_ERROR 10 /* SPORT0 Error Interrupt */
99 #define IRQ_SPORT1_ERROR 11 /* SPORT1 Error Interrupt */
100 #define IRQ_SPI_ERROR 12 /* SPI Error Interrupt */
101 #define IRQ_UART_ERROR 13 /* UART Error Interrupt */
102 #define IRQ_RTC 14 /* RTC Interrupt */
103 #define IRQ_PPI 15 /* DMA0 Interrupt (PPI) */
104 #define IRQ_SPORT0 16 /* DMA1 Interrupt (SPORT0 RX) */
105 #define IRQ_SPARE1 17 /* DMA2 Interrupt (SPORT0 TX) */
106 #define IRQ_SPORT1 18 /* DMA3 Interrupt (SPORT1 RX) */
107 #define IRQ_SPARE2 19 /* DMA4 Interrupt (SPORT1 TX) */
108 #define IRQ_SPI 20 /* DMA5 Interrupt (SPI) */
109 #define IRQ_UART 21 /* DMA6 Interrupt (UART RX) */
110 #define IRQ_SPARE3 22 /* DMA7 Interrupt (UART TX) */
111 #define IRQ_TMR0 23 /* Timer 0 */
112 #define IRQ_TMR1 24 /* Timer 1 */
113 #define IRQ_TMR2 25 /* Timer 2 */
114 #define IRQ_PROG_INTA 26 /* Programmable Flags A (8) */
115 #define IRQ_PROG_INTB 27 /* Programmable Flags B (8) */
116 #define IRQ_MEM_DMA0 28 /* DMA8/9 Interrupt (Memory DMA Stream 0) */
117 #define IRQ_MEM_DMA1 29 /* DMA10/11 Interrupt (Memory DMA Stream 1) */
118 #define IRQ_WATCH 30 /* Watch Dog Timer */
119 #define IRQ_SW_INT1 31 /* Software Int 1 */
120 #define IRQ_SW_INT2 32 /* Software Int 2 (reserved for SYSCALL) */
122 #define IRQ_UART_RX_BIT 0x4000
123 #define IRQ_UART_TX_BIT 0x8000
124 #define IRQ_UART_ERROR_BIT 0x40