2 * FlexBus Internal Memory Map
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 /*********************************************************************
30 * FlexBus Chip Selects (FBCS)
31 *********************************************************************/
34 u32 csar0; /* Chip-select Address Register */
35 u32 csmr0; /* Chip-select Mask Register */
36 u32 cscr0; /* Chip-select Control Register */
37 u32 csar1; /* Chip-select Address Register */
38 u32 csmr1; /* Chip-select Mask Register */
39 u32 cscr1; /* Chip-select Control Register */
40 u32 csar2; /* Chip-select Address Register */
41 u32 csmr2; /* Chip-select Mask Register */
42 u32 cscr2; /* Chip-select Control Register */
43 u32 csar3; /* Chip-select Address Register */
44 u32 csmr3; /* Chip-select Mask Register */
45 u32 cscr3; /* Chip-select Control Register */
46 u32 csar4; /* Chip-select Address Register */
47 u32 csmr4; /* Chip-select Mask Register */
48 u32 cscr4; /* Chip-select Control Register */
49 u32 csar5; /* Chip-select Address Register */
50 u32 csmr5; /* Chip-select Mask Register */
51 u32 cscr5; /* Chip-select Control Register */
54 /* Bit definitions and macros for CSAR group */
55 #define FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
57 /* Bit definitions and macros for CSMR group */
58 #define FBCS_CSMR_V (0x00000001) /* Valid bit */
59 #define FBCS_CSMR_WP (0x00000100) /* Write protect */
60 #define FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
61 #define FBCS_CSMR_BAM_4G (0xFFFF0000)
62 #define FBCS_CSMR_BAM_2G (0x7FFF0000)
63 #define FBCS_CSMR_BAM_1G (0x3FFF0000)
64 #define FBCS_CSMR_BAM_1024M (0x3FFF0000)
65 #define FBCS_CSMR_BAM_512M (0x1FFF0000)
66 #define FBCS_CSMR_BAM_256M (0x0FFF0000)
67 #define FBCS_CSMR_BAM_128M (0x07FF0000)
68 #define FBCS_CSMR_BAM_64M (0x03FF0000)
69 #define FBCS_CSMR_BAM_32M (0x01FF0000)
70 #define FBCS_CSMR_BAM_16M (0x00FF0000)
71 #define FBCS_CSMR_BAM_8M (0x007F0000)
72 #define FBCS_CSMR_BAM_4M (0x003F0000)
73 #define FBCS_CSMR_BAM_2M (0x001F0000)
74 #define FBCS_CSMR_BAM_1M (0x000F0000)
75 #define FBCS_CSMR_BAM_1024K (0x000F0000)
76 #define FBCS_CSMR_BAM_512K (0x00070000)
77 #define FBCS_CSMR_BAM_256K (0x00030000)
78 #define FBCS_CSMR_BAM_128K (0x00010000)
79 #define FBCS_CSMR_BAM_64K (0x00000000)
81 /* Bit definitions and macros for CSCR group */
82 #define FBCS_CSCR_BSTW (0x00000008) /* Burst-write enable */
83 #define FBCS_CSCR_BSTR (0x00000010) /* Burst-read enable */
84 #define FBCS_CSCR_BEM (0x00000020) /* Byte-enable mode */
85 #define FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) /* Port size */
86 #define FBCS_CSCR_AA (0x00000100) /* Auto-acknowledge */
87 #define FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
88 #define FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */
89 #define FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */
90 #define FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
91 #define FBCS_CSCR_SWSEN (0x00800000) /* Secondary wait state enable */
92 #define FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */
94 #define FBCS_CSCR_PS_8 (0x00000040)
95 #define FBCS_CSCR_PS_16 (0x00000080)
96 #define FBCS_CSCR_PS_32 (0x00000000)
98 #endif /* __FLEXBUS_H */