2 * fec.h -- Fast Ethernet Controller definitions
4 * Some definitions copied from commproc.h for MPC8xx:
5 * MPC8xx Communication Processor Module.
6 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
8 * Add FEC Structure and definitions
9 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
10 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 /* Buffer descriptors used FEC.
36 typedef struct cpm_buf_desc {
37 ushort cbd_sc; /* Status and Control */
38 ushort cbd_datlen; /* Data length in buffer */
39 uint cbd_bufaddr; /* Buffer address in host memory */
42 #define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
43 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
44 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
45 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
46 #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
47 #define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
48 #define BD_SC_CM ((ushort)0x0200) /* Continous mode */
49 #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
50 #define BD_SC_P ((ushort)0x0100) /* xmt preamble */
51 #define BD_SC_BR ((ushort)0x0020) /* Break received */
52 #define BD_SC_FR ((ushort)0x0010) /* Framing error */
53 #define BD_SC_PR ((ushort)0x0008) /* Parity error */
54 #define BD_SC_OV ((ushort)0x0002) /* Overrun */
55 #define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
57 /* Buffer descriptor control/status used by Ethernet receive.
59 #define BD_ENET_RX_EMPTY ((ushort)0x8000)
60 #define BD_ENET_RX_RO1 ((ushort)0x4000)
61 #define BD_ENET_RX_WRAP ((ushort)0x2000)
62 #define BD_ENET_RX_INTR ((ushort)0x1000)
63 #define BD_ENET_RX_RO2 BD_ENET_RX_INTR
64 #define BD_ENET_RX_LAST ((ushort)0x0800)
65 #define BD_ENET_RX_FIRST ((ushort)0x0400)
66 #define BD_ENET_RX_MISS ((ushort)0x0100)
67 #define BD_ENET_RX_BC ((ushort)0x0080)
68 #define BD_ENET_RX_MC ((ushort)0x0040)
69 #define BD_ENET_RX_LG ((ushort)0x0020)
70 #define BD_ENET_RX_NO ((ushort)0x0010)
71 #define BD_ENET_RX_SH ((ushort)0x0008)
72 #define BD_ENET_RX_CR ((ushort)0x0004)
73 #define BD_ENET_RX_OV ((ushort)0x0002)
74 #define BD_ENET_RX_CL ((ushort)0x0001)
75 #define BD_ENET_RX_TR BD_ENET_RX_CL
76 #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
78 /* Buffer descriptor control/status used by Ethernet transmit.
80 #define BD_ENET_TX_READY ((ushort)0x8000)
81 #define BD_ENET_TX_PAD ((ushort)0x4000)
82 #define BD_ENET_TX_TO1 BD_ENET_TX_PAD
83 #define BD_ENET_TX_WRAP ((ushort)0x2000)
84 #define BD_ENET_TX_INTR ((ushort)0x1000)
85 #define BD_ENET_TX_TO2 BD_ENET_TX_INTR_
86 #define BD_ENET_TX_LAST ((ushort)0x0800)
87 #define BD_ENET_TX_TC ((ushort)0x0400)
88 #define BD_ENET_TX_DEF ((ushort)0x0200)
89 #define BD_ENET_TX_ABC BD_ENET_TX_DEF
90 #define BD_ENET_TX_HB ((ushort)0x0100)
91 #define BD_ENET_TX_LC ((ushort)0x0080)
92 #define BD_ENET_TX_RL ((ushort)0x0040)
93 #define BD_ENET_TX_RCMASK ((ushort)0x003c)
94 #define BD_ENET_TX_UN ((ushort)0x0002)
95 #define BD_ENET_TX_CSL ((ushort)0x0001)
96 #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
98 /*********************************************************************
99 * Fast Ethernet Controller (FEC)
100 *********************************************************************/
101 /* FEC private information */
111 cbd_t *rxbd; /* Rx BD */
112 cbd_t *txbd; /* Tx BD */
117 struct fec_info_s *next;
121 /* Register read/write struct */
130 u8 resv1[0x28]; /* 0x18 */
133 u8 resv2[0x44]; /* 0x48 */
136 u8 resv3[0x10]; /* 0x94 */
140 u8 resv4[0x50]; /* 0xB0 */
141 u32 opd; /* 0x100 - dummy */
143 u32 mibc; /* 0x108 */
144 u8 resv5[0x38]; /* 0x10C */
146 u8 resv6[0x270]; /* 0x148 */
147 u32 iaur; /* 0x3B8 - dummy */
148 u32 ialr; /* 0x3BC - dummy */
149 u32 palr; /* 0x3C0 */
150 u32 paur; /* 0x3C4 */
151 u32 gaur; /* 0x3C8 */
152 u32 galr; /* 0x3CC */
153 u32 erdsr; /* 0x3D0 */
154 u32 etdsr; /* 0x3D4 */
155 u32 emrbr; /* 0x3D8 */
156 u8 resv12[0x74]; /* 0x18C */
200 u32 rmon_t_crc_align;
201 u32 rmon_t_undersize;
208 u32 rmon_t_p128to255;
209 u32 rmon_t_p256to511;
210 u32 rmon_t_p512to1023;
211 u32 rmon_t_p1024to2047;
212 u32 rmon_t_p_gte2048;
226 u32 ieee_t_octets_ok;
233 u32 rmon_r_crc_align;
234 u32 rmon_r_undersize;
241 u32 rmon_r_p128to255;
242 u32 rmon_r_p256to511;
243 u32 rmon_r_p512to1023;
244 u32 rmon_r_p1024to2047;
245 u32 rmon_r_p_gte2048;
254 u32 ieee_r_octets_ok;
256 #endif /* CONFIG_MCFFEC */
258 /*********************************************************************
259 * Fast Ethernet Controller (FEC)
260 *********************************************************************/
261 /* Bit definitions and macros for FEC_EIR */
262 #define FEC_EIR_CLEAR_ALL (0xFFF80000)
263 #define FEC_EIR_HBERR (0x80000000)
264 #define FEC_EIR_BABR (0x40000000)
265 #define FEC_EIR_BABT (0x20000000)
266 #define FEC_EIR_GRA (0x10000000)
267 #define FEC_EIR_TXF (0x08000000)
268 #define FEC_EIR_TXB (0x04000000)
269 #define FEC_EIR_RXF (0x02000000)
270 #define FEC_EIR_RXB (0x01000000)
271 #define FEC_EIR_MII (0x00800000)
272 #define FEC_EIR_EBERR (0x00400000)
273 #define FEC_EIR_LC (0x00200000)
274 #define FEC_EIR_RL (0x00100000)
275 #define FEC_EIR_UN (0x00080000)
277 /* Bit definitions and macros for FEC_RDAR */
278 #define FEC_RDAR_R_DES_ACTIVE (0x01000000)
280 /* Bit definitions and macros for FEC_TDAR */
281 #define FEC_TDAR_X_DES_ACTIVE (0x01000000)
283 /* Bit definitions and macros for FEC_ECR */
284 #define FEC_ECR_ETHER_EN (0x00000002)
285 #define FEC_ECR_RESET (0x00000001)
287 /* Bit definitions and macros for FEC_MMFR */
288 #define FEC_MMFR_DATA(x) (((x)&0xFFFF))
289 #define FEC_MMFR_ST(x) (((x)&0x03)<<30)
290 #define FEC_MMFR_ST_01 (0x40000000)
291 #define FEC_MMFR_OP_RD (0x20000000)
292 #define FEC_MMFR_OP_WR (0x10000000)
293 #define FEC_MMFR_PA(x) (((x)&0x1F)<<23)
294 #define FEC_MMFR_RA(x) (((x)&0x1F)<<18)
295 #define FEC_MMFR_TA(x) (((x)&0x03)<<16)
296 #define FEC_MMFR_TA_10 (0x00020000)
298 /* Bit definitions and macros for FEC_MSCR */
299 #define FEC_MSCR_DIS_PREAMBLE (0x00000080)
300 #define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1)
302 /* Bit definitions and macros for FEC_MIBC */
303 #define FEC_MIBC_MIB_DISABLE (0x80000000)
304 #define FEC_MIBC_MIB_IDLE (0x40000000)
306 /* Bit definitions and macros for FEC_RCR */
307 #define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16)
308 #define FEC_RCR_FCE (0x00000020)
309 #define FEC_RCR_BC_REJ (0x00000010)
310 #define FEC_RCR_PROM (0x00000008)
311 #define FEC_RCR_MII_MODE (0x00000004)
312 #define FEC_RCR_DRT (0x00000002)
313 #define FEC_RCR_LOOP (0x00000001)
315 /* Bit definitions and macros for FEC_TCR */
316 #define FEC_TCR_RFC_PAUSE (0x00000010)
317 #define FEC_TCR_TFC_PAUSE (0x00000008)
318 #define FEC_TCR_FDEN (0x00000004)
319 #define FEC_TCR_HBC (0x00000002)
320 #define FEC_TCR_GTS (0x00000001)
322 /* Bit definitions and macros for FEC_PAUR */
323 #define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16)
324 #define FEC_PAUR_TYPE(x) ((x)&0xFFFF)
326 /* Bit definitions and macros for FEC_OPD */
327 #define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
328 #define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
330 /* Bit definitions and macros for FEC_TFWR */
331 #define FEC_TFWR_X_WMRK(x) ((x)&0x03)
332 #define FEC_TFWR_X_WMRK_64 (0x01)
333 #define FEC_TFWR_X_WMRK_128 (0x02)
334 #define FEC_TFWR_X_WMRK_192 (0x03)
336 /* Bit definitions and macros for FEC_FRBR */
337 #define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2)
339 /* Bit definitions and macros for FEC_FRSR */
340 #define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2)
342 /* Bit definitions and macros for FEC_ERDSR */
343 #define FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
345 /* Bit definitions and macros for FEC_ETDSR */
346 #define FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2)
348 /* Bit definitions and macros for FEC_EMRBR */
349 #define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4)
351 #define FEC_RESET_DELAY 100
352 #define FEC_RX_TOUT 100
354 int fecpin_setclear(struct eth_device *dev, int setclear);
356 #ifdef CONFIG_SYS_DISCOVER_PHY
357 void __mii_init(void);
358 uint mii_send(uint mii_cmd);
359 int mii_discover_phy(struct eth_device *dev);
360 int mcffec_miiphy_read(char *devname, unsigned char addr,
361 unsigned char reg, unsigned short *value);
362 int mcffec_miiphy_write(char *devname, unsigned char addr,
363 unsigned char reg, unsigned short value);