2 * mcf5329.h -- Definitions for Freescale Coldfire 5329
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 /****************************************************************************/
30 /*********************************************************************
31 * System Control Module (SCM)
32 *********************************************************************/
33 /* Bit definitions and macros for SCM_MPR */
34 #define SCM_MPR_MPROT0(x) (((x)&0x0F)<<28)
35 #define SCM_MPR_MPROT1(x) (((x)&0x0F)<<24)
36 #define SCM_MPR_MPROT2(x) (((x)&0x0F)<<20)
37 #define SCM_MPR_MPROT4(x) (((x)&0x0F)<<12)
38 #define SCM_MPR_MPROT5(x) (((x)&0x0F)<<8)
39 #define SCM_MPR_MPROT6(x) (((x)&0x0F)<<4)
44 /* Bit definitions and macros for SCM_BMT */
45 #define BMT_BME (0x08)
50 #define BMT_128 (0x03)
51 #define BMT_256 (0x02)
52 #define BMT_512 (0x01)
53 #define BMT_1024 (0x00)
55 /* Bit definitions and macros for SCM_PACRA */
56 #define SCM_PACRA_PACR0(x) (((x)&0x0F)<<28)
57 #define SCM_PACRA_PACR1(x) (((x)&0x0F)<<24)
58 #define SCM_PACRA_PACR2(x) (((x)&0x0F)<<20)
63 /* Bit definitions and macros for SCM_PACRB */
64 #define SCM_PACRB_PACR8(x) (((x)&0x0F)<<28)
65 #define SCM_PACRB_PACR12(x) (((x)&0x0F)<<12)
67 /* Bit definitions and macros for SCM_PACRC */
68 #define SCM_PACRC_PACR16(x) (((x)&0x0F)<<28)
69 #define SCM_PACRC_PACR17(x) (((x)&0x0F)<<24)
70 #define SCM_PACRC_PACR18(x) (((x)&0x0F)<<20)
71 #define SCM_PACRC_PACR19(x) (((x)&0x0F)<<16)
72 #define SCM_PACRC_PACR21(x) (((x)&0x0F)<<8)
73 #define SCM_PACRC_PACR22(x) (((x)&0x0F)<<4)
74 #define SCM_PACRC_PACR23(x) (((x)&0x0F)<<0)
76 /* Bit definitions and macros for SCM_PACRD */
77 #define SCM_PACRD_PACR24(x) (((x)&0x0F)<<28)
78 #define SCM_PACRD_PACR25(x) (((x)&0x0F)<<24)
79 #define SCM_PACRD_PACR26(x) (((x)&0x0F)<<20)
80 #define SCM_PACRD_PACR28(x) (((x)&0x0F)<<12)
81 #define SCM_PACRD_PACR29(x) (((x)&0x0F)<<8)
82 #define SCM_PACRD_PACR30(x) (((x)&0x0F)<<4)
83 #define SCM_PACRD_PACR31(x) (((x)&0x0F)<<0)
85 /* Bit definitions and macros for SCM_PACRE */
86 #define SCM_PACRE_PACR32(x) (((x)&0x0F)<<28)
87 #define SCM_PACRE_PACR33(x) (((x)&0x0F)<<24)
88 #define SCM_PACRE_PACR34(x) (((x)&0x0F)<<20)
89 #define SCM_PACRE_PACR35(x) (((x)&0x0F)<<16)
90 #define SCM_PACRE_PACR36(x) (((x)&0x0F)<<12)
91 #define SCM_PACRE_PACR37(x) (((x)&0x0F)<<8)
92 #define SCM_PACRE_PACR38(x) (((x)&0x0F)<<4)
94 /* Bit definitions and macros for SCM_PACRF */
95 #define SCM_PACRF_PACR40(x) (((x)&0x0F)<<28)
96 #define SCM_PACRF_PACR41(x) (((x)&0x0F)<<24)
97 #define SCM_PACRF_PACR42(x) (((x)&0x0F)<<20)
98 #define SCM_PACRF_PACR43(x) (((x)&0x0F)<<16)
99 #define SCM_PACRF_PACR44(x) (((x)&0x0F)<<12)
100 #define SCM_PACRF_PACR45(x) (((x)&0x0F)<<8)
101 #define SCM_PACRF_PACR46(x) (((x)&0x0F)<<4)
102 #define SCM_PACRF_PACR47(x) (((x)&0x0F)<<0)
104 /* Bit definitions and macros for SCM_PACRG */
105 #define SCM_PACRG_PACR48(x) (((x)&0x0F)<<28)
107 /* Bit definitions and macros for SCM_PACRH */
108 #define SCM_PACRH_PACR56(x) (((x)&0x0F)<<28)
109 #define SCM_PACRH_PACR57(x) (((x)&0x0F)<<24)
110 #define SCM_PACRH_PACR58(x) (((x)&0x0F)<<20)
112 /* PACRn Assignments */
113 #define PACR0(x) SCM_PACRA_PACR0(x)
114 #define PACR1(x) SCM_PACRA_PACR1(x)
115 #define PACR2(x) SCM_PACRA_PACR2(x)
116 #define PACR8(x) SCM_PACRB_PACR8(x)
117 #define PACR12(x) SCM_PACRB_PACR12(x)
118 #define PACR16(x) SCM_PACRC_PACR16(x)
119 #define PACR17(x) SCM_PACRC_PACR17(x)
120 #define PACR18(x) SCM_PACRC_PACR18(x)
121 #define PACR19(x) SCM_PACRC_PACR19(x)
122 #define PACR21(x) SCM_PACRC_PACR21(x)
123 #define PACR22(x) SCM_PACRC_PACR22(x)
124 #define PACR23(x) SCM_PACRC_PACR23(x)
125 #define PACR24(x) SCM_PACRD_PACR24(x)
126 #define PACR25(x) SCM_PACRD_PACR25(x)
127 #define PACR26(x) SCM_PACRD_PACR26(x)
128 #define PACR28(x) SCM_PACRD_PACR28(x)
129 #define PACR29(x) SCM_PACRD_PACR29(x)
130 #define PACR30(x) SCM_PACRD_PACR30(x)
131 #define PACR31(x) SCM_PACRD_PACR31(x)
132 #define PACR32(x) SCM_PACRE_PACR32(x)
133 #define PACR33(x) SCM_PACRE_PACR33(x)
134 #define PACR34(x) SCM_PACRE_PACR34(x)
135 #define PACR35(x) SCM_PACRE_PACR35(x)
136 #define PACR36(x) SCM_PACRE_PACR36(x)
137 #define PACR37(x) SCM_PACRE_PACR37(x)
138 #define PACR38(x) SCM_PACRE_PACR38(x)
139 #define PACR40(x) SCM_PACRF_PACR40(x)
140 #define PACR41(x) SCM_PACRF_PACR41(x)
141 #define PACR42(x) SCM_PACRF_PACR42(x)
142 #define PACR43(x) SCM_PACRF_PACR43(x)
143 #define PACR44(x) SCM_PACRF_PACR44(x)
144 #define PACR45(x) SCM_PACRF_PACR45(x)
145 #define PACR46(x) SCM_PACRF_PACR46(x)
146 #define PACR47(x) SCM_PACRF_PACR47(x)
147 #define PACR48(x) SCM_PACRG_PACR48(x)
148 #define PACR56(x) SCM_PACRH_PACR56(x)
149 #define PACR57(x) SCM_PACRH_PACR57(x)
150 #define PACR58(x) SCM_PACRH_PACR58(x)
152 /* Bit definitions and macros for SCM_CWCR */
153 #define CWCR_RO (0x8000)
154 #define CWCR_CWR_WH (0x0100)
155 #define CWCR_CWE (0x0080)
156 #define CWRI_WINDOW (0x0060)
157 #define CWRI_RESET (0x0040)
158 #define CWRI_INT_RESET (0x0020)
159 #define CWRI_INT (0x0000)
160 #define CWCR_CWT(x) (((x)&0x001F))
162 /* Bit definitions and macros for SCM_ISR */
163 #define SCMISR_CFEI (0x02)
164 #define SCMISR_CWIC (0x01)
166 /* Bit definitions and macros for SCM_BCR */
167 #define BCR_GBR (0x00000200)
168 #define BCR_GBW (0x00000100)
169 #define BCR_S7 (0x00000080)
170 #define BCR_S6 (0x00000040)
171 #define BCR_S4 (0x00000010)
172 #define BCR_S1 (0x00000002)
174 /* Bit definitions and macros for SCM_CFIER */
175 #define CFIER_ECFEI (0x01)
177 /* Bit definitions and macros for SCM_CFLOC */
178 #define CFLOC_LOC (0x80)
180 /* Bit definitions and macros for SCM_CFATR */
181 #define CFATR_WRITE (0x80)
182 #define CFATR_SZ32 (0x20)
183 #define CFATR_SZ16 (0x10)
184 #define CFATR_SZ08 (0x00)
185 #define CFATR_CACHE (0x08)
186 #define CFATR_MODE (0x02)
187 #define CFATR_TYPE (0x01)
189 /*********************************************************************
190 * FlexBus Chip Selects (FBCS)
191 *********************************************************************/
192 /* Bit definitions and macros for FBCS_CSAR */
193 #define CSAR_BA(x) (((x)&0xFFFF)<<16)
195 /* Bit definitions and macros for FBCS_CSMR */
196 #define CSMR_BAM(x) (((x)&0xFFFF)<<16)
197 #define CSMR_BAM_4G (0xFFFF0000)
198 #define CSMR_BAM_2G (0x7FFF0000)
199 #define CSMR_BAM_1G (0x3FFF0000)
200 #define CSMR_BAM_1024M (0x3FFF0000)
201 #define CSMR_BAM_512M (0x1FFF0000)
202 #define CSMR_BAM_256M (0x0FFF0000)
203 #define CSMR_BAM_128M (0x07FF0000)
204 #define CSMR_BAM_64M (0x03FF0000)
205 #define CSMR_BAM_32M (0x01FF0000)
206 #define CSMR_BAM_16M (0x00FF0000)
207 #define CSMR_BAM_8M (0x007F0000)
208 #define CSMR_BAM_4M (0x003F0000)
209 #define CSMR_BAM_2M (0x001F0000)
210 #define CSMR_BAM_1M (0x000F0000)
211 #define CSMR_BAM_1024K (0x000F0000)
212 #define CSMR_BAM_512K (0x00070000)
213 #define CSMR_BAM_256K (0x00030000)
214 #define CSMR_BAM_128K (0x00010000)
215 #define CSMR_BAM_64K (0x00000000)
216 #define CSMR_WP (0x00000100)
217 #define CSMR_V (0x00000001)
219 /* Bit definitions and macros for FBCS_CSCR */
220 #define CSCR_SWS(x) (((x)&0x3F)<<26)
221 #define CSCR_ASET(x) (((x)&0x03)<<20)
222 #define CSCR_SWSEN (0x00800000)
223 #define CSCR_ASET_4CLK (0x00300000)
224 #define CSCR_ASET_3CLK (0x00200000)
225 #define CSCR_ASET_2CLK (0x00100000)
226 #define CSCR_ASET_1CLK (0x00000000)
227 #define CSCR_RDAH(x) (((x)&0x03)<<18)
228 #define CSCR_RDAH_4CYC (0x000C0000)
229 #define CSCR_RDAH_3CYC (0x00080000)
230 #define CSCR_RDAH_2CYC (0x00040000)
231 #define CSCR_RDAH_1CYC (0x00000000)
232 #define CSCR_WRAH(x) (((x)&0x03)<<16)
233 #define CSCR_WDAH_4CYC (0x00003000)
234 #define CSCR_WDAH_3CYC (0x00002000)
235 #define CSCR_WDAH_2CYC (0x00001000)
236 #define CSCR_WDAH_1CYC (0x00000000)
237 #define CSCR_WS(x) (((x)&0x3F)<<10)
238 #define CSCR_SBM (0x00000200)
239 #define CSCR_AA (0x00000100)
240 #define CSCR_PS_MASK (0x000000C0)
241 #define CSCR_PS_32 (0x00000000)
242 #define CSCR_PS_16 (0x00000080)
243 #define CSCR_PS_8 (0x00000040)
244 #define CSCR_BEM (0x00000020)
245 #define CSCR_BSTR (0x00000010)
246 #define CSCR_BSTW (0x00000008)
248 /*********************************************************************
249 * FlexCAN Module (CAN)
250 *********************************************************************/
251 /* Bit definitions and macros for CAN_CANMCR */
252 #define CANMCR_MDIS (0x80000000)
253 #define CANMCR_FRZ (0x40000000)
254 #define CANMCR_HALT (0x10000000)
255 #define CANMCR_NORDY (0x08000000)
256 #define CANMCR_SOFTRST (0x02000000)
257 #define CANMCR_FRZACK (0x01000000)
258 #define CANMCR_SUPV (0x00800000)
259 #define CANMCR_LPMACK (0x00100000)
260 #define CANMCR_MAXMB(x) (((x)&0x0F))
262 /* Bit definitions and macros for CAN_CANCTRL */
263 #define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
264 #define CANCTRL_RJW(x) (((x)&0x03)<<22)
265 #define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
266 #define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
267 #define CANCTRL_BOFFMSK (0x00008000)
268 #define CANCTRL_ERRMSK (0x00004000)
269 #define CANCTRL_CLKSRC (0x00002000)
270 #define CANCTRL_LPB (0x00001000)
271 #define CANCTRL_SMP (0x00000080)
272 #define CANCTRL_BOFFREC (0x00000040)
273 #define CANCTRL_TSYNC (0x00000020)
274 #define CANCTRL_LBUF (0x00000010)
275 #define CANCTRL_LOM (0x00000008)
276 #define CANCTRL_PROPSEG(x) (((x)&0x07))
278 /* Bit definitions and macros for CAN_TIMER */
279 #define TIMER_TIMER(x) ((x)&0xFFFF)
281 /* Bit definitions and macros for CAN_RXGMASK */
282 #define RXGMASK_MI(x) ((x)&0x1FFFFFFF)
284 /* Bit definitions and macros for CAN_ERRCNT */
285 #define ERRCNT_TXECTR(x) (((x)&0xFF))
286 #define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
288 /* Bit definitions and macros for CAN_ERRSTAT */
289 #define ERRSTAT_BITERR1 (0x00008000)
290 #define ERRSTAT_BITERR0 (0x00004000)
291 #define ERRSTAT_ACKERR (0x00002000)
292 #define ERRSTAT_CRCERR (0x00001000)
293 #define ERRSTAT_FRMERR (0x00000800)
294 #define ERRSTAT_STFERR (0x00000400)
295 #define ERRSTAT_TXWRN (0x00000200)
296 #define ERRSTAT_RXWRN (0x00000100)
297 #define ERRSTAT_IDLE (0x00000080)
298 #define ERRSTAT_TXRX (0x00000040)
299 #define ERRSTAT_FLT_BUSOFF (0x00000020)
300 #define ERRSTAT_FLT_PASSIVE (0x00000010)
301 #define ERRSTAT_FLT_ACTIVE (0x00000000)
302 #define ERRSTAT_BOFFINT (0x00000004)
303 #define ERRSTAT_ERRINT (0x00000002)
304 #define ERRSTAT_WAKINT (0x00000001)
306 /* Bit definitions and macros for CAN_IMASK */
307 #define IMASK_BUF15M (0x00008000)
308 #define IMASK_BUF14M (0x00004000)
309 #define IMASK_BUF13M (0x00002000)
310 #define IMASK_BUF12M (0x00001000)
311 #define IMASK_BUF11M (0x00000800)
312 #define IMASK_BUF10M (0x00000400)
313 #define IMASK_BUF9M (0x00000200)
314 #define IMASK_BUF8M (0x00000100)
315 #define IMASK_BUF7M (0x00000080)
316 #define IMASK_BUF6M (0x00000040)
317 #define IMASK_BUF5M (0x00000020)
318 #define IMASK_BUF4M (0x00000010)
319 #define IMASK_BUF3M (0x00000008)
320 #define IMASK_BUF2M (0x00000004)
321 #define IMASK_BUF1M (0x00000002)
322 #define IMASK_BUF0M (0x00000001)
324 /* Bit definitions and macros for CAN_IFLAG */
325 #define IFLAG_BUF15I (0x00008000)
326 #define IFLAG_BUF14I (0x00004000)
327 #define IFLAG_BUF13I (0x00002000)
328 #define IFLAG_BUF12I (0x00001000)
329 #define IFLAG_BUF11I (0x00000800)
330 #define IFLAG_BUF10I (0x00000400)
331 #define IFLAG_BUF9I (0x00000200)
332 #define IFLAG_BUF8I (0x00000100)
333 #define IFLAG_BUF7I (0x00000080)
334 #define IFLAG_BUF6I (0x00000040)
335 #define IFLAG_BUF5I (0x00000020)
336 #define IFLAG_BUF4I (0x00000010)
337 #define IFLAG_BUF3I (0x00000008)
338 #define IFLAG_BUF2I (0x00000004)
339 #define IFLAG_BUF1I (0x00000002)
340 #define IFLAG_BUF0I (0x00000001)
342 /*********************************************************************
343 * Interrupt Controller (INTC)
344 *********************************************************************/
345 #define INTC0_EPORT INTC_IPRL_INT1
347 #define INT0_LO_RSVD0 (0)
348 #define INT0_LO_EPORT1 (1)
349 #define INT0_LO_EPORT2 (2)
350 #define INT0_LO_EPORT3 (3)
351 #define INT0_LO_EPORT4 (4)
352 #define INT0_LO_EPORT5 (5)
353 #define INT0_LO_EPORT6 (6)
354 #define INT0_LO_EPORT7 (7)
355 #define INT0_LO_EDMA_00 (8)
356 #define INT0_LO_EDMA_01 (9)
357 #define INT0_LO_EDMA_02 (10)
358 #define INT0_LO_EDMA_03 (11)
359 #define INT0_LO_EDMA_04 (12)
360 #define INT0_LO_EDMA_05 (13)
361 #define INT0_LO_EDMA_06 (14)
362 #define INT0_LO_EDMA_07 (15)
363 #define INT0_LO_EDMA_08 (16)
364 #define INT0_LO_EDMA_09 (17)
365 #define INT0_LO_EDMA_10 (18)
366 #define INT0_LO_EDMA_11 (19)
367 #define INT0_LO_EDMA_12 (20)
368 #define INT0_LO_EDMA_13 (21)
369 #define INT0_LO_EDMA_14 (22)
370 #define INT0_LO_EDMA_15 (23)
371 #define INT0_LO_EDMA_ERR (24)
372 #define INT0_LO_SCM (25)
373 #define INT0_LO_UART0 (26)
374 #define INT0_LO_UART1 (27)
375 #define INT0_LO_UART2 (28)
376 #define INT0_LO_RSVD1 (29)
377 #define INT0_LO_I2C (30)
378 #define INT0_LO_QSPI (31)
379 #define INT0_HI_DTMR0 (32)
380 #define INT0_HI_DTMR1 (33)
381 #define INT0_HI_DTMR2 (34)
382 #define INT0_HI_DTMR3 (35)
383 #define INT0_HI_FEC_TXF (36)
384 #define INT0_HI_FEC_TXB (37)
385 #define INT0_HI_FEC_UN (38)
386 #define INT0_HI_FEC_RL (39)
387 #define INT0_HI_FEC_RXF (40)
388 #define INT0_HI_FEC_RXB (41)
389 #define INT0_HI_FEC_MII (42)
390 #define INT0_HI_FEC_LC (43)
391 #define INT0_HI_FEC_HBERR (44)
392 #define INT0_HI_FEC_GRA (45)
393 #define INT0_HI_FEC_EBERR (46)
394 #define INT0_HI_FEC_BABT (47)
395 #define INT0_HI_FEC_BABR (48)
396 /* 49 - 61 Reserved */
397 #define INT0_HI_SCM (62)
399 /* Bit definitions and macros for INTC_IPRH */
400 #define INTC_IPRH_INT63 (0x80000000)
401 #define INTC_IPRH_INT62 (0x40000000)
402 #define INTC_IPRH_INT61 (0x20000000)
403 #define INTC_IPRH_INT60 (0x10000000)
404 #define INTC_IPRH_INT59 (0x08000000)
405 #define INTC_IPRH_INT58 (0x04000000)
406 #define INTC_IPRH_INT57 (0x02000000)
407 #define INTC_IPRH_INT56 (0x01000000)
408 #define INTC_IPRH_INT55 (0x00800000)
409 #define INTC_IPRH_INT54 (0x00400000)
410 #define INTC_IPRH_INT53 (0x00200000)
411 #define INTC_IPRH_INT52 (0x00100000)
412 #define INTC_IPRH_INT51 (0x00080000)
413 #define INTC_IPRH_INT50 (0x00040000)
414 #define INTC_IPRH_INT49 (0x00020000)
415 #define INTC_IPRH_INT48 (0x00010000)
416 #define INTC_IPRH_INT47 (0x00008000)
417 #define INTC_IPRH_INT46 (0x00004000)
418 #define INTC_IPRH_INT45 (0x00002000)
419 #define INTC_IPRH_INT44 (0x00001000)
420 #define INTC_IPRH_INT43 (0x00000800)
421 #define INTC_IPRH_INT42 (0x00000400)
422 #define INTC_IPRH_INT41 (0x00000200)
423 #define INTC_IPRH_INT40 (0x00000100)
424 #define INTC_IPRH_INT39 (0x00000080)
425 #define INTC_IPRH_INT38 (0x00000040)
426 #define INTC_IPRH_INT37 (0x00000020)
427 #define INTC_IPRH_INT36 (0x00000010)
428 #define INTC_IPRH_INT35 (0x00000008)
429 #define INTC_IPRH_INT34 (0x00000004)
430 #define INTC_IPRH_INT33 (0x00000002)
431 #define INTC_IPRH_INT32 (0x00000001)
433 /* Bit definitions and macros for INTC_IPRL */
434 #define INTC_IPRL_INT31 (0x80000000)
435 #define INTC_IPRL_INT30 (0x40000000)
436 #define INTC_IPRL_INT29 (0x20000000)
437 #define INTC_IPRL_INT28 (0x10000000)
438 #define INTC_IPRL_INT27 (0x08000000)
439 #define INTC_IPRL_INT26 (0x04000000)
440 #define INTC_IPRL_INT25 (0x02000000)
441 #define INTC_IPRL_INT24 (0x01000000)
442 #define INTC_IPRL_INT23 (0x00800000)
443 #define INTC_IPRL_INT22 (0x00400000)
444 #define INTC_IPRL_INT21 (0x00200000)
445 #define INTC_IPRL_INT20 (0x00100000)
446 #define INTC_IPRL_INT19 (0x00080000)
447 #define INTC_IPRL_INT18 (0x00040000)
448 #define INTC_IPRL_INT17 (0x00020000)
449 #define INTC_IPRL_INT16 (0x00010000)
450 #define INTC_IPRL_INT15 (0x00008000)
451 #define INTC_IPRL_INT14 (0x00004000)
452 #define INTC_IPRL_INT13 (0x00002000)
453 #define INTC_IPRL_INT12 (0x00001000)
454 #define INTC_IPRL_INT11 (0x00000800)
455 #define INTC_IPRL_INT10 (0x00000400)
456 #define INTC_IPRL_INT9 (0x00000200)
457 #define INTC_IPRL_INT8 (0x00000100)
458 #define INTC_IPRL_INT7 (0x00000080)
459 #define INTC_IPRL_INT6 (0x00000040)
460 #define INTC_IPRL_INT5 (0x00000020)
461 #define INTC_IPRL_INT4 (0x00000010)
462 #define INTC_IPRL_INT3 (0x00000008)
463 #define INTC_IPRL_INT2 (0x00000004)
464 #define INTC_IPRL_INT1 (0x00000002)
465 #define INTC_IPRL_INT0 (0x00000001)
467 /* Bit definitions and macros for INTC_ICONFIG */
468 #define INTC_ICFG_ELVLPRI7 (0x8000)
469 #define INTC_ICFG_ELVLPRI6 (0x4000)
470 #define INTC_ICFG_ELVLPRI5 (0x2000)
471 #define INTC_ICFG_ELVLPRI4 (0x1000)
472 #define INTC_ICFG_ELVLPRI3 (0x0800)
473 #define INTC_ICFG_ELVLPRI2 (0x0400)
474 #define INTC_ICFG_ELVLPRI1 (0x0200)
475 #define INTC_ICFG_EMASK (0x0020)
477 /* Bit definitions and macros for INTC_SIMR */
478 #define INTC_SIMR_SALL (0x40)
479 #define INTC_SIMR_SIMR(x) ((x)&0x3F)
481 /* Bit definitions and macros for INTC_CIMR */
482 #define INTC_CIMR_CALL (0x40)
483 #define INTC_CIMR_CIMR(x) ((x)&0x3F)
485 /* Bit definitions and macros for INTC_CLMASK */
486 #define INTC_CLMASK_CLMASK(x) ((x)&0x0F)
488 /* Bit definitions and macros for INTC_SLMASK */
489 #define INTC_SLMASK_SLMASK(x) ((x)&0x0F)
491 /* Bit definitions and macros for INTC_ICR */
492 #define INTC_ICR_IL(x) ((x)&0x07)
494 /*********************************************************************
495 * Queued Serial Peripheral Interface (QSPI)
496 *********************************************************************/
497 /* Bit definitions and macros for QSPI_QMR */
498 #define QSPI_QMR_MSTR (0x8000)
499 #define QSPI_QMR_DOHIE (0x4000)
500 #define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
501 #define QSPI_QMR_CPOL (0x0200)
502 #define QSPI_QMR_CPHA (0x0100)
503 #define QSPI_QMR_BAUD(x) ((x)&0x00FF)
505 /* Bit definitions and macros for QSPI_QDLYR */
506 #define QSPI_QDLYR_SPE (0x8000)
507 #define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
508 #define QSPI_QDLYR_DTL(x) ((x)&0x00FF)
510 /* Bit definitions and macros for QSPI_QWR */
511 #define QSPI_QWR_NEWQP(x) ((x)&0x000F)
512 #define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
513 #define QSPI_QWR_CSIV (0x1000)
514 #define QSPI_QWR_WRTO (0x2000)
515 #define QSPI_QWR_WREN (0x4000)
516 #define QSPI_QWR_HALT (0x8000)
518 /* Bit definitions and macros for QSPI_QIR */
519 #define QSPI_QIR_WCEFB (0x8000)
520 #define QSPI_QIR_ABRTB (0x4000)
521 #define QSPI_QIR_ABRTL (0x1000)
522 #define QSPI_QIR_WCEFE (0x0800)
523 #define QSPI_QIR_ABRTE (0x0400)
524 #define QSPI_QIR_SPIFE (0x0100)
525 #define QSPI_QIR_WCEF (0x0008)
526 #define QSPI_QIR_ABRT (0x0004)
527 #define QSPI_QIR_SPIF (0x0001)
529 /* Bit definitions and macros for QSPI_QAR */
530 #define QSPI_QAR_ADDR(x) ((x)&0x003F)
531 #define QSPI_QAR_TRANS (0x0000)
532 #define QSPI_QAR_RECV (0x0010)
533 #define QSPI_QAR_CMD (0x0020)
535 /* Bit definitions and macros for QSPI_QDR */
536 #define QSPI_QDR_CONT (0x8000)
537 #define QSPI_QDR_BITSE (0x4000)
538 #define QSPI_QDR_DT (0x2000)
539 #define QSPI_QDR_DSCK (0x1000)
540 #define QSPI_QDR_QSPI_CS3 (0x0800)
541 #define QSPI_QDR_QSPI_CS2 (0x0400)
542 #define QSPI_QDR_QSPI_CS1 (0x0200)
543 #define QSPI_QDR_QSPI_CS0 (0x0100)
545 /*********************************************************************
546 * Pulse Width Modulation (PWM)
547 *********************************************************************/
548 /* Bit definitions and macros for PWM_E */
549 #define PWM_EN_PWME7 (0x80)
550 #define PWM_EN_PWME5 (0x20)
551 #define PWM_EN_PWME3 (0x08)
552 #define PWM_EN_PWME1 (0x02)
554 /* Bit definitions and macros for PWM_POL */
555 #define PWM_POL_PPOL7 (0x80)
556 #define PWM_POL_PPOL5 (0x20)
557 #define PWM_POL_PPOL3 (0x08)
558 #define PWM_POL_PPOL1 (0x02)
560 /* Bit definitions and macros for PWM_CLK */
561 #define PWM_CLK_PCLK7 (0x80)
562 #define PWM_CLK_PCLK5 (0x20)
563 #define PWM_CLK_PCLK3 (0x08)
564 #define PWM_CLK_PCLK1 (0x02)
566 /* Bit definitions and macros for PWM_PRCLK */
567 #define PWM_PRCLK_PCKB(x) (((x)&0x07)<<4)
568 #define PWM_PRCLK_PCKA(x) ((x)&0x07)
570 /* Bit definitions and macros for PWM_CAE */
571 #define PWM_CAE_CAE7 (0x80)
572 #define PWM_CAE_CAE5 (0x20)
573 #define PWM_CAE_CAE3 (0x08)
574 #define PWM_CAE_CAE1 (0x02)
576 /* Bit definitions and macros for PWM_CTL */
577 #define PWM_CTL_CON67 (0x80)
578 #define PWM_CTL_CON45 (0x40)
579 #define PWM_CTL_CON23 (0x20)
580 #define PWM_CTL_CON01 (0x10)
581 #define PWM_CTL_PSWAR (0x08)
582 #define PWM_CTL_PFRZ (0x04)
584 /* Bit definitions and macros for PWM_SDN */
585 #define PWM_SDN_IF (0x80)
586 #define PWM_SDN_IE (0x40)
587 #define PWM_SDN_RESTART (0x20)
588 #define PWM_SDN_LVL (0x10)
589 #define PWM_SDN_PWM7IN (0x04)
590 #define PWM_SDN_PWM7IL (0x02)
591 #define PWM_SDN_SDNEN (0x01)
593 /*********************************************************************
594 * Watchdog Timer Modules (WTM)
595 *********************************************************************/
596 /* Bit definitions and macros for WTM_WCR */
597 #define WTM_WCR_WAIT (0x0008)
598 #define WTM_WCR_DOZE (0x0004)
599 #define WTM_WCR_HALTED (0x0002)
600 #define WTM_WCR_EN (0x0001)
602 /*********************************************************************
603 * Chip Configuration Module (CCM)
604 *********************************************************************/
605 /* Bit definitions and macros for CCM_CCR */
606 #define CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001)
607 #define CCM_CCR_LIMP (0x0041)
608 #define CCM_CCR_LOAD (0x0021)
609 #define CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
610 #define CCM_CCR_OSC_MODE (0x0005)
611 #define CCM_CCR_PLL_MODE (0x0003)
612 #define CCM_CCR_RESERVED (0x0001)
614 /* Bit definitions and macros for CCM_RCON */
615 #define CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001)
616 #define CCM_RCON_LIMP (0x0041)
617 #define CCM_RCON_LOAD (0x0021)
618 #define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
619 #define CCM_RCON_OSC_MODE (0x0005)
620 #define CCM_RCON_PLL_MODE (0x0003)
621 #define CCM_RCON_RESERVED (0x0001)
623 /* Bit definitions and macros for CCM_CIR */
624 #define CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
625 #define CCM_CIR_PRN(x) ((x)&0x003F)
627 /* Bit definitions and macros for CCM_MISCCR */
628 #define CCM_MISCCR_PLL_LOCK (0x2000)
629 #define CCM_MISCCR_LIMP (0x1000)
630 #define CCM_MISCCR_LCD_CHEN (0x0100)
631 #define CCM_MISCCR_SSI_PUE (0x0080)
632 #define CCM_MISCCR_SSI_PUS (0x0040)
633 #define CCM_MISCCR_TIM_DMA (0x0020)
634 #define CCM_MISCCR_SSI_SRC (0x0010)
635 #define CCM_MISCCR_USBDIV (0x0002)
636 #define CCM_MISCCR_USBSRC (0x0001)
638 /* Bit definitions and macros for CCM_CDR */
639 #define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8)
640 #define CCM_CDR_SSIDIV(x) ((x)&0x000F)
642 /* Bit definitions and macros for CCM_UHCSR */
643 #define CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14)
644 #define CCM_UHCSR_WKUP (0x0004)
645 #define CCM_UHCSR_UHMIE (0x0002)
646 #define CCM_UHCSR_XPDE (0x0001)
648 /* Bit definitions and macros for CCM_UOCSR */
649 #define CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14)
650 #define CCM_UOCSR_DPPD (0x2000)
651 #define CCM_UOCSR_DMPD (0x1000)
652 #define CCM_UOCSR_DRV_VBUS (0x0800)
653 #define CCM_UOCSR_CRG_VBUS (0x0400)
654 #define CCM_UOCSR_DCR_VBUS (0x0200)
655 #define CCM_UOCSR_DPPU (0x0100)
656 #define CCM_UOCSR_AVLD (0x0080)
657 #define CCM_UOCSR_BVLD (0x0040)
658 #define CCM_UOCSR_VVLD (0x0020)
659 #define CCM_UOCSR_SEND (0x0010)
660 #define CCM_UOCSR_PWRFLT (0x0008)
661 #define CCM_UOCSR_WKUP (0x0004)
662 #define CCM_UOCSR_UOMIE (0x0002)
663 #define CCM_UOCSR_XPDE (0x0001)
666 /*********************************************************************
667 * General Purpose I/O (GPIO)
668 *********************************************************************/
669 /* Bit definitions and macros for GPIO_PODR_FECH_L */
670 #define GPIO_PODR_FECH_L7 (0x80)
671 #define GPIO_PODR_FECH_L6 (0x40)
672 #define GPIO_PODR_FECH_L5 (0x20)
673 #define GPIO_PODR_FECH_L4 (0x10)
674 #define GPIO_PODR_FECH_L3 (0x08)
675 #define GPIO_PODR_FECH_L2 (0x04)
676 #define GPIO_PODR_FECH_L1 (0x02)
677 #define GPIO_PODR_FECH_L0 (0x01)
679 /* Bit definitions and macros for GPIO_PODR_SSI */
680 #define GPIO_PODR_SSI_4 (0x10)
681 #define GPIO_PODR_SSI_3 (0x08)
682 #define GPIO_PODR_SSI_2 (0x04)
683 #define GPIO_PODR_SSI_1 (0x02)
684 #define GPIO_PODR_SSI_0 (0x01)
686 /* Bit definitions and macros for GPIO_PODR_BUSCTL */
687 #define GPIO_PODR_BUSCTL_3 (0x08)
688 #define GPIO_PODR_BUSCTL_2 (0x04)
689 #define GPIO_PODR_BUSCTL_1 (0x02)
690 #define GPIO_PODR_BUSCTL_0 (0x01)
692 /* Bit definitions and macros for GPIO_PODR_BE */
693 #define GPIO_PODR_BE_3 (0x08)
694 #define GPIO_PODR_BE_2 (0x04)
695 #define GPIO_PODR_BE_1 (0x02)
696 #define GPIO_PODR_BE_0 (0x01)
698 /* Bit definitions and macros for GPIO_PODR_CS */
699 #define GPIO_PODR_CS_5 (0x20)
700 #define GPIO_PODR_CS_4 (0x10)
701 #define GPIO_PODR_CS_3 (0x08)
702 #define GPIO_PODR_CS_2 (0x04)
703 #define GPIO_PODR_CS_1 (0x02)
705 /* Bit definitions and macros for GPIO_PODR_PWM */
706 #define GPIO_PODR_PWM_5 (0x20)
707 #define GPIO_PODR_PWM_4 (0x10)
708 #define GPIO_PODR_PWM_3 (0x08)
709 #define GPIO_PODR_PWM_2 (0x04)
711 /* Bit definitions and macros for GPIO_PODR_FECI2C */
712 #define GPIO_PODR_FECI2C_3 (0x08)
713 #define GPIO_PODR_FECI2C_2 (0x04)
714 #define GPIO_PODR_FECI2C_1 (0x02)
715 #define GPIO_PODR_FECI2C_0 (0x01)
717 /* Bit definitions and macros for GPIO_PODR_UART */
718 #define GPIO_PODR_UART_7 (0x80)
719 #define GPIO_PODR_UART_6 (0x40)
720 #define GPIO_PODR_UART_5 (0x20)
721 #define GPIO_PODR_UART_4 (0x10)
722 #define GPIO_PODR_UART_3 (0x08)
723 #define GPIO_PODR_UART_2 (0x04)
724 #define GPIO_PODR_UART_1 (0x02)
725 #define GPIO_PODR_UART_0 (0x01)
727 /* Bit definitions and macros for GPIO_PODR_QSPI */
728 #define GPIO_PODR_QSPI_5 (0x20)
729 #define GPIO_PODR_QSPI_4 (0x10)
730 #define GPIO_PODR_QSPI_3 (0x08)
731 #define GPIO_PODR_QSPI_2 (0x04)
732 #define GPIO_PODR_QSPI_1 (0x02)
733 #define GPIO_PODR_QSPI_0 (0x01)
735 /* Bit definitions and macros for GPIO_PODR_TIMER */
736 #define GPIO_PODR_TIMER_3 (0x08)
737 #define GPIO_PODR_TIMER_2 (0x04)
738 #define GPIO_PODR_TIMER_1 (0x02)
739 #define GPIO_PODR_TIMER_0 (0x01)
741 /* Bit definitions and macros for GPIO_PODR_LCDDATAH */
742 #define GPIO_PODR_LCDDATAH_1 (0x02)
743 #define GPIO_PODR_LCDDATAH_0 (0x01)
745 /* Bit definitions and macros for GPIO_PODR_LCDDATAM */
746 #define GPIO_PODR_LCDDATAM_7 (0x80)
747 #define GPIO_PODR_LCDDATAM_6 (0x40)
748 #define GPIO_PODR_LCDDATAM_5 (0x20)
749 #define GPIO_PODR_LCDDATAM_4 (0x10)
750 #define GPIO_PODR_LCDDATAM_3 (0x08)
751 #define GPIO_PODR_LCDDATAM_2 (0x04)
752 #define GPIO_PODR_LCDDATAM_1 (0x02)
753 #define GPIO_PODR_LCDDATAM_0 (0x01)
755 /* Bit definitions and macros for GPIO_PODR_LCDDATAL */
756 #define GPIO_PODR_LCDDATAL_7 (0x80)
757 #define GPIO_PODR_LCDDATAL_6 (0x40)
758 #define GPIO_PODR_LCDDATAL_5 (0x20)
759 #define GPIO_PODR_LCDDATAL_4 (0x10)
760 #define GPIO_PODR_LCDDATAL_3 (0x08)
761 #define GPIO_PODR_LCDDATAL_2 (0x04)
762 #define GPIO_PODR_LCDDATAL_1 (0x02)
763 #define GPIO_PODR_LCDDATAL_0 (0x01)
765 /* Bit definitions and macros for GPIO_PODR_LCDCTLH */
766 #define GPIO_PODR_LCDCTLH_0 (0x01)
768 /* Bit definitions and macros for GPIO_PODR_LCDCTLL */
769 #define GPIO_PODR_LCDCTLL_7 (0x80)
770 #define GPIO_PODR_LCDCTLL_6 (0x40)
771 #define GPIO_PODR_LCDCTLL_5 (0x20)
772 #define GPIO_PODR_LCDCTLL_4 (0x10)
773 #define GPIO_PODR_LCDCTLL_3 (0x08)
774 #define GPIO_PODR_LCDCTLL_2 (0x04)
775 #define GPIO_PODR_LCDCTLL_1 (0x02)
776 #define GPIO_PODR_LCDCTLL_0 (0x01)
778 /* Bit definitions and macros for GPIO_PDDR_FECH */
779 #define GPIO_PDDR_FECH_L7 (0x80)
780 #define GPIO_PDDR_FECH_L6 (0x40)
781 #define GPIO_PDDR_FECH_L5 (0x20)
782 #define GPIO_PDDR_FECH_L4 (0x10)
783 #define GPIO_PDDR_FECH_L3 (0x08)
784 #define GPIO_PDDR_FECH_L2 (0x04)
785 #define GPIO_PDDR_FECH_L1 (0x02)
786 #define GPIO_PDDR_FECH_L0 (0x01)
788 /* Bit definitions and macros for GPIO_PDDR_SSI */
789 #define GPIO_PDDR_SSI_4 (0x10)
790 #define GPIO_PDDR_SSI_3 (0x08)
791 #define GPIO_PDDR_SSI_2 (0x04)
792 #define GPIO_PDDR_SSI_1 (0x02)
793 #define GPIO_PDDR_SSI_0 (0x01)
795 /* Bit definitions and macros for GPIO_PDDR_BUSCTL */
796 #define GPIO_PDDR_BUSCTL_3 (0x08)
797 #define GPIO_PDDR_BUSCTL_2 (0x04)
798 #define GPIO_PDDR_BUSCTL_1 (0x02)
799 #define GPIO_PDDR_BUSCTL_0 (0x01)
801 /* Bit definitions and macros for GPIO_PDDR_BE */
802 #define GPIO_PDDR_BE_3 (0x08)
803 #define GPIO_PDDR_BE_2 (0x04)
804 #define GPIO_PDDR_BE_1 (0x02)
805 #define GPIO_PDDR_BE_0 (0x01)
807 /* Bit definitions and macros for GPIO_PDDR_CS */
808 #define GPIO_PDDR_CS_1 (0x02)
809 #define GPIO_PDDR_CS_2 (0x04)
810 #define GPIO_PDDR_CS_3 (0x08)
811 #define GPIO_PDDR_CS_4 (0x10)
812 #define GPIO_PDDR_CS_5 (0x20)
814 /* Bit definitions and macros for GPIO_PDDR_PWM */
815 #define GPIO_PDDR_PWM_2 (0x04)
816 #define GPIO_PDDR_PWM_3 (0x08)
817 #define GPIO_PDDR_PWM_4 (0x10)
818 #define GPIO_PDDR_PWM_5 (0x20)
820 /* Bit definitions and macros for GPIO_PDDR_FECI2C */
821 #define GPIO_PDDR_FECI2C_0 (0x01)
822 #define GPIO_PDDR_FECI2C_1 (0x02)
823 #define GPIO_PDDR_FECI2C_2 (0x04)
824 #define GPIO_PDDR_FECI2C_3 (0x08)
826 /* Bit definitions and macros for GPIO_PDDR_UART */
827 #define GPIO_PDDR_UART_0 (0x01)
828 #define GPIO_PDDR_UART_1 (0x02)
829 #define GPIO_PDDR_UART_2 (0x04)
830 #define GPIO_PDDR_UART_3 (0x08)
831 #define GPIO_PDDR_UART_4 (0x10)
832 #define GPIO_PDDR_UART_5 (0x20)
833 #define GPIO_PDDR_UART_6 (0x40)
834 #define GPIO_PDDR_UART_7 (0x80)
836 /* Bit definitions and macros for GPIO_PDDR_QSPI */
837 #define GPIO_PDDR_QSPI_0 (0x01)
838 #define GPIO_PDDR_QSPI_1 (0x02)
839 #define GPIO_PDDR_QSPI_2 (0x04)
840 #define GPIO_PDDR_QSPI_3 (0x08)
841 #define GPIO_PDDR_QSPI_4 (0x10)
842 #define GPIO_PDDR_QSPI_5 (0x20)
844 /* Bit definitions and macros for GPIO_PDDR_TIMER */
845 #define GPIO_PDDR_TIMER_0 (0x01)
846 #define GPIO_PDDR_TIMER_1 (0x02)
847 #define GPIO_PDDR_TIMER_2 (0x04)
848 #define GPIO_PDDR_TIMER_3 (0x08)
850 /* Bit definitions and macros for GPIO_PDDR_LCDDATAH */
851 #define GPIO_PDDR_LCDDATAH_0 (0x01)
852 #define GPIO_PDDR_LCDDATAH_1 (0x02)
854 /* Bit definitions and macros for GPIO_PDDR_LCDDATAM */
855 #define GPIO_PDDR_LCDDATAM_0 (0x01)
856 #define GPIO_PDDR_LCDDATAM_1 (0x02)
857 #define GPIO_PDDR_LCDDATAM_2 (0x04)
858 #define GPIO_PDDR_LCDDATAM_3 (0x08)
859 #define GPIO_PDDR_LCDDATAM_4 (0x10)
860 #define GPIO_PDDR_LCDDATAM_5 (0x20)
861 #define GPIO_PDDR_LCDDATAM_6 (0x40)
862 #define GPIO_PDDR_LCDDATAM_7 (0x80)
864 /* Bit definitions and macros for GPIO_PDDR_LCDDATAL */
865 #define GPIO_PDDR_LCDDATAL_0 (0x01)
866 #define GPIO_PDDR_LCDDATAL_1 (0x02)
867 #define GPIO_PDDR_LCDDATAL_2 (0x04)
868 #define GPIO_PDDR_LCDDATAL_3 (0x08)
869 #define GPIO_PDDR_LCDDATAL_4 (0x10)
870 #define GPIO_PDDR_LCDDATAL_5 (0x20)
871 #define GPIO_PDDR_LCDDATAL_6 (0x40)
872 #define GPIO_PDDR_LCDDATAL_7 (0x80)
874 /* Bit definitions and macros for GPIO_PDDR_LCDCTLH */
875 #define GPIO_PDDR_LCDCTLH_0 (0x01)
877 /* Bit definitions and macros for GPIO_PDDR_LCDCTLL */
878 #define GPIO_PDDR_LCDCTLL_0 (0x01)
879 #define GPIO_PDDR_LCDCTLL_1 (0x02)
880 #define GPIO_PDDR_LCDCTLL_2 (0x04)
881 #define GPIO_PDDR_LCDCTLL_3 (0x08)
882 #define GPIO_PDDR_LCDCTLL_4 (0x10)
883 #define GPIO_PDDR_LCDCTLL_5 (0x20)
884 #define GPIO_PDDR_LCDCTLL_6 (0x40)
885 #define GPIO_PDDR_LCDCTLL_7 (0x80)
887 /* Bit definitions and macros for GPIO_PPDSDR_FECH */
888 #define GPIO_PPDSDR_FECH_L0 (0x01)
889 #define GPIO_PPDSDR_FECH_L1 (0x02)
890 #define GPIO_PPDSDR_FECH_L2 (0x04)
891 #define GPIO_PPDSDR_FECH_L3 (0x08)
892 #define GPIO_PPDSDR_FECH_L4 (0x10)
893 #define GPIO_PPDSDR_FECH_L5 (0x20)
894 #define GPIO_PPDSDR_FECH_L6 (0x40)
895 #define GPIO_PPDSDR_FECH_L7 (0x80)
897 /* Bit definitions and macros for GPIO_PPDSDR_SSI */
898 #define GPIO_PPDSDR_SSI_0 (0x01)
899 #define GPIO_PPDSDR_SSI_1 (0x02)
900 #define GPIO_PPDSDR_SSI_2 (0x04)
901 #define GPIO_PPDSDR_SSI_3 (0x08)
902 #define GPIO_PPDSDR_SSI_4 (0x10)
904 /* Bit definitions and macros for GPIO_PPDSDR_BUSCTL */
905 #define GPIO_PPDSDR_BUSCTL_0 (0x01)
906 #define GPIO_PPDSDR_BUSCTL_1 (0x02)
907 #define GPIO_PPDSDR_BUSCTL_2 (0x04)
908 #define GPIO_PPDSDR_BUSCTL_3 (0x08)
910 /* Bit definitions and macros for GPIO_PPDSDR_BE */
911 #define GPIO_PPDSDR_BE_0 (0x01)
912 #define GPIO_PPDSDR_BE_1 (0x02)
913 #define GPIO_PPDSDR_BE_2 (0x04)
914 #define GPIO_PPDSDR_BE_3 (0x08)
916 /* Bit definitions and macros for GPIO_PPDSDR_CS */
917 #define GPIO_PPDSDR_CS_1 (0x02)
918 #define GPIO_PPDSDR_CS_2 (0x04)
919 #define GPIO_PPDSDR_CS_3 (0x08)
920 #define GPIO_PPDSDR_CS_4 (0x10)
921 #define GPIO_PPDSDR_CS_5 (0x20)
923 /* Bit definitions and macros for GPIO_PPDSDR_PWM */
924 #define GPIO_PPDSDR_PWM_2 (0x04)
925 #define GPIO_PPDSDR_PWM_3 (0x08)
926 #define GPIO_PPDSDR_PWM_4 (0x10)
927 #define GPIO_PPDSDR_PWM_5 (0x20)
929 /* Bit definitions and macros for GPIO_PPDSDR_FECI2C */
930 #define GPIO_PPDSDR_FECI2C_0 (0x01)
931 #define GPIO_PPDSDR_FECI2C_1 (0x02)
932 #define GPIO_PPDSDR_FECI2C_2 (0x04)
933 #define GPIO_PPDSDR_FECI2C_3 (0x08)
935 /* Bit definitions and macros for GPIO_PPDSDR_UART */
936 #define GPIO_PPDSDR_UART_0 (0x01)
937 #define GPIO_PPDSDR_UART_1 (0x02)
938 #define GPIO_PPDSDR_UART_2 (0x04)
939 #define GPIO_PPDSDR_UART_3 (0x08)
940 #define GPIO_PPDSDR_UART_4 (0x10)
941 #define GPIO_PPDSDR_UART_5 (0x20)
942 #define GPIO_PPDSDR_UART_6 (0x40)
943 #define GPIO_PPDSDR_UART_7 (0x80)
945 /* Bit definitions and macros for GPIO_PPDSDR_QSPI */
946 #define GPIO_PPDSDR_QSPI_0 (0x01)
947 #define GPIO_PPDSDR_QSPI_1 (0x02)
948 #define GPIO_PPDSDR_QSPI_2 (0x04)
949 #define GPIO_PPDSDR_QSPI_3 (0x08)
950 #define GPIO_PPDSDR_QSPI_4 (0x10)
951 #define GPIO_PPDSDR_QSPI_5 (0x20)
953 /* Bit definitions and macros for GPIO_PPDSDR_TIMER */
954 #define GPIO_PPDSDR_TIMER_0 (0x01)
955 #define GPIO_PPDSDR_TIMER_1 (0x02)
956 #define GPIO_PPDSDR_TIMER_2 (0x04)
957 #define GPIO_PPDSDR_TIMER_3 (0x08)
959 /* Bit definitions and macros for GPIO_PPDSDR_LCDDATAH */
960 #define GPIO_PPDSDR_LCDDATAH_0 (0x01)
961 #define GPIO_PPDSDR_LCDDATAH_1 (0x02)
963 /* Bit definitions and macros for GPIO_PPDSDR_LCDDATAM */
964 #define GPIO_PPDSDR_LCDDATAM_0 (0x01)
965 #define GPIO_PPDSDR_LCDDATAM_1 (0x02)
966 #define GPIO_PPDSDR_LCDDATAM_2 (0x04)
967 #define GPIO_PPDSDR_LCDDATAM_3 (0x08)
968 #define GPIO_PPDSDR_LCDDATAM_4 (0x10)
969 #define GPIO_PPDSDR_LCDDATAM_5 (0x20)
970 #define GPIO_PPDSDR_LCDDATAM_6 (0x40)
971 #define GPIO_PPDSDR_LCDDATAM_7 (0x80)
973 /* Bit definitions and macros for GPIO_PPDSDR_LCDDATAL */
974 #define GPIO_PPDSDR_LCDDATAL_0 (0x01)
975 #define GPIO_PPDSDR_LCDDATAL_1 (0x02)
976 #define GPIO_PPDSDR_LCDDATAL_2 (0x04)
977 #define GPIO_PPDSDR_LCDDATAL_3 (0x08)
978 #define GPIO_PPDSDR_LCDDATAL_4 (0x10)
979 #define GPIO_PPDSDR_LCDDATAL_5 (0x20)
980 #define GPIO_PPDSDR_LCDDATAL_6 (0x40)
981 #define GPIO_PPDSDR_LCDDATAL_7 (0x80)
983 /* Bit definitions and macros for GPIO_PPDSDR_LCDCTLH */
984 #define GPIO_PPDSDR_LCDCTLH_0 (0x01)
986 /* Bit definitions and macros for GPIO_PPDSDR_LCDCTLL */
987 #define GPIO_PPDSDR_LCDCTLL_0 (0x01)
988 #define GPIO_PPDSDR_LCDCTLL_1 (0x02)
989 #define GPIO_PPDSDR_LCDCTLL_2 (0x04)
990 #define GPIO_PPDSDR_LCDCTLL_3 (0x08)
991 #define GPIO_PPDSDR_LCDCTLL_4 (0x10)
992 #define GPIO_PPDSDR_LCDCTLL_5 (0x20)
993 #define GPIO_PPDSDR_LCDCTLL_6 (0x40)
994 #define GPIO_PPDSDR_LCDCTLL_7 (0x80)
996 /* Bit definitions and macros for GPIO_PCLRR_FECH */
997 #define GPIO_PCLRR_FECH_L0 (0x01)
998 #define GPIO_PCLRR_FECH_L1 (0x02)
999 #define GPIO_PCLRR_FECH_L2 (0x04)
1000 #define GPIO_PCLRR_FECH_L3 (0x08)
1001 #define GPIO_PCLRR_FECH_L4 (0x10)
1002 #define GPIO_PCLRR_FECH_L5 (0x20)
1003 #define GPIO_PCLRR_FECH_L6 (0x40)
1004 #define GPIO_PCLRR_FECH_L7 (0x80)
1006 /* Bit definitions and macros for GPIO_PCLRR_SSI */
1007 #define GPIO_PCLRR_SSI_0 (0x01)
1008 #define GPIO_PCLRR_SSI_1 (0x02)
1009 #define GPIO_PCLRR_SSI_2 (0x04)
1010 #define GPIO_PCLRR_SSI_3 (0x08)
1011 #define GPIO_PCLRR_SSI_4 (0x10)
1013 /* Bit definitions and macros for GPIO_PCLRR_BUSCTL */
1014 #define GPIO_PCLRR_BUSCTL_L0 (0x01)
1015 #define GPIO_PCLRR_BUSCTL_L1 (0x02)
1016 #define GPIO_PCLRR_BUSCTL_L2 (0x04)
1017 #define GPIO_PCLRR_BUSCTL_L3 (0x08)
1019 /* Bit definitions and macros for GPIO_PCLRR_BE */
1020 #define GPIO_PCLRR_BE_0 (0x01)
1021 #define GPIO_PCLRR_BE_1 (0x02)
1022 #define GPIO_PCLRR_BE_2 (0x04)
1023 #define GPIO_PCLRR_BE_3 (0x08)
1025 /* Bit definitions and macros for GPIO_PCLRR_CS */
1026 #define GPIO_PCLRR_CS_1 (0x02)
1027 #define GPIO_PCLRR_CS_2 (0x04)
1028 #define GPIO_PCLRR_CS_3 (0x08)
1029 #define GPIO_PCLRR_CS_4 (0x10)
1030 #define GPIO_PCLRR_CS_5 (0x20)
1032 /* Bit definitions and macros for GPIO_PCLRR_PWM */
1033 #define GPIO_PCLRR_PWM_2 (0x04)
1034 #define GPIO_PCLRR_PWM_3 (0x08)
1035 #define GPIO_PCLRR_PWM_4 (0x10)
1036 #define GPIO_PCLRR_PWM_5 (0x20)
1038 /* Bit definitions and macros for GPIO_PCLRR_FECI2C */
1039 #define GPIO_PCLRR_FECI2C_0 (0x01)
1040 #define GPIO_PCLRR_FECI2C_1 (0x02)
1041 #define GPIO_PCLRR_FECI2C_2 (0x04)
1042 #define GPIO_PCLRR_FECI2C_3 (0x08)
1044 /* Bit definitions and macros for GPIO_PCLRR_UART */
1045 #define GPIO_PCLRR_UART0 (0x01)
1046 #define GPIO_PCLRR_UART1 (0x02)
1047 #define GPIO_PCLRR_UART2 (0x04)
1048 #define GPIO_PCLRR_UART3 (0x08)
1049 #define GPIO_PCLRR_UART4 (0x10)
1050 #define GPIO_PCLRR_UART5 (0x20)
1051 #define GPIO_PCLRR_UART6 (0x40)
1052 #define GPIO_PCLRR_UART7 (0x80)
1054 /* Bit definitions and macros for GPIO_PCLRR_QSPI */
1055 #define GPIO_PCLRR_QSPI0 (0x01)
1056 #define GPIO_PCLRR_QSPI1 (0x02)
1057 #define GPIO_PCLRR_QSPI2 (0x04)
1058 #define GPIO_PCLRR_QSPI3 (0x08)
1059 #define GPIO_PCLRR_QSPI4 (0x10)
1060 #define GPIO_PCLRR_QSPI5 (0x20)
1062 /* Bit definitions and macros for GPIO_PCLRR_TIMER */
1063 #define GPIO_PCLRR_TIMER0 (0x01)
1064 #define GPIO_PCLRR_TIMER1 (0x02)
1065 #define GPIO_PCLRR_TIMER2 (0x04)
1066 #define GPIO_PCLRR_TIMER3 (0x08)
1068 /* Bit definitions and macros for GPIO_PCLRR_LCDDATAH */
1069 #define GPIO_PCLRR_LCDDATAH0 (0x01)
1070 #define GPIO_PCLRR_LCDDATAH1 (0x02)
1072 /* Bit definitions and macros for GPIO_PCLRR_LCDDATAM */
1073 #define GPIO_PCLRR_LCDDATAM0 (0x01)
1074 #define GPIO_PCLRR_LCDDATAM1 (0x02)
1075 #define GPIO_PCLRR_LCDDATAM2 (0x04)
1076 #define GPIO_PCLRR_LCDDATAM3 (0x08)
1077 #define GPIO_PCLRR_LCDDATAM4 (0x10)
1078 #define GPIO_PCLRR_LCDDATAM5 (0x20)
1079 #define GPIO_PCLRR_LCDDATAM6 (0x40)
1080 #define GPIO_PCLRR_LCDDATAM7 (0x80)
1082 /* Bit definitions and macros for GPIO_PCLRR_LCDDATAL */
1083 #define GPIO_PCLRR_LCDDATAL0 (0x01)
1084 #define GPIO_PCLRR_LCDDATAL1 (0x02)
1085 #define GPIO_PCLRR_LCDDATAL2 (0x04)
1086 #define GPIO_PCLRR_LCDDATAL3 (0x08)
1087 #define GPIO_PCLRR_LCDDATAL4 (0x10)
1088 #define GPIO_PCLRR_LCDDATAL5 (0x20)
1089 #define GPIO_PCLRR_LCDDATAL6 (0x40)
1090 #define GPIO_PCLRR_LCDDATAL7 (0x80)
1092 /* Bit definitions and macros for GPIO_PCLRR_LCDCTLH */
1093 #define GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01)
1095 /* Bit definitions and macros for GPIO_PCLRR_LCDCTLL */
1096 #define GPIO_PCLRR_LCDCTLL0 (0x01)
1097 #define GPIO_PCLRR_LCDCTLL1 (0x02)
1098 #define GPIO_PCLRR_LCDCTLL2 (0x04)
1099 #define GPIO_PCLRR_LCDCTLL3 (0x08)
1100 #define GPIO_PCLRR_LCDCTLL4 (0x10)
1101 #define GPIO_PCLRR_LCDCTLL5 (0x20)
1102 #define GPIO_PCLRR_LCDCTLL6 (0x40)
1103 #define GPIO_PCLRR_LCDCTLL7 (0x80)
1105 /* Bit definitions and macros for GPIO_PAR_FEC */
1106 #define GPIO_PAR_FEC_MII(x) (((x)&0x03)<<0)
1107 #define GPIO_PAR_FEC_7W(x) (((x)&0x03)<<2)
1108 #define GPIO_PAR_FEC_7W_GPIO (0x00)
1109 #define GPIO_PAR_FEC_7W_URTS1 (0x04)
1110 #define GPIO_PAR_FEC_7W_FEC (0x0C)
1111 #define GPIO_PAR_FEC_MII_GPIO (0x00)
1112 #define GPIO_PAR_FEC_MII_UART (0x01)
1113 #define GPIO_PAR_FEC_MII_FEC (0x03)
1115 /* Bit definitions and macros for GPIO_PAR_PWM */
1116 #define GPIO_PAR_PWM1(x) (((x)&0x03)<<0)
1117 #define GPIO_PAR_PWM3(x) (((x)&0x03)<<2)
1118 #define GPIO_PAR_PWM5 (0x10)
1119 #define GPIO_PAR_PWM7 (0x20)
1121 /* Bit definitions and macros for GPIO_PAR_BUSCTL */
1122 #define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<3)
1123 #define GPIO_PAR_BUSCTL_RWB (0x20)
1124 #define GPIO_PAR_BUSCTL_TA (0x40)
1125 #define GPIO_PAR_BUSCTL_OE (0x80)
1126 #define GPIO_PAR_BUSCTL_OE_GPIO (0x00)
1127 #define GPIO_PAR_BUSCTL_OE_OE (0x80)
1128 #define GPIO_PAR_BUSCTL_TA_GPIO (0x00)
1129 #define GPIO_PAR_BUSCTL_TA_TA (0x40)
1130 #define GPIO_PAR_BUSCTL_RWB_GPIO (0x00)
1131 #define GPIO_PAR_BUSCTL_RWB_RWB (0x20)
1132 #define GPIO_PAR_BUSCTL_TS_GPIO (0x00)
1133 #define GPIO_PAR_BUSCTL_TS_DACK0 (0x10)
1134 #define GPIO_PAR_BUSCTL_TS_TS (0x18)
1136 /* Bit definitions and macros for GPIO_PAR_FECI2C */
1137 #define GPIO_PAR_FECI2C_SDA(x) (((x)&0x03)<<0)
1138 #define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2)
1139 #define GPIO_PAR_FECI2C_MDIO(x) (((x)&0x03)<<4)
1140 #define GPIO_PAR_FECI2C_MDC(x) (((x)&0x03)<<6)
1141 #define GPIO_PAR_FECI2C_MDC_GPIO (0x00)
1142 #define GPIO_PAR_FECI2C_MDC_UTXD2 (0x40)
1143 #define GPIO_PAR_FECI2C_MDC_SCL (0x80)
1144 #define GPIO_PAR_FECI2C_MDC_EMDC (0xC0)
1145 #define GPIO_PAR_FECI2C_MDIO_GPIO (0x00)
1146 #define GPIO_PAR_FECI2C_MDIO_URXD2 (0x10)
1147 #define GPIO_PAR_FECI2C_MDIO_SDA (0x20)
1148 #define GPIO_PAR_FECI2C_MDIO_EMDIO (0x30)
1149 #define GPIO_PAR_FECI2C_SCL_GPIO (0x00)
1150 #define GPIO_PAR_FECI2C_SCL_UTXD2 (0x04)
1151 #define GPIO_PAR_FECI2C_SCL_SCL (0x0C)
1152 #define GPIO_PAR_FECI2C_SDA_GPIO (0x00)
1153 #define GPIO_PAR_FECI2C_SDA_URXD2 (0x02)
1154 #define GPIO_PAR_FECI2C_SDA_SDA (0x03)
1156 /* Bit definitions and macros for GPIO_PAR_BE */
1157 #define GPIO_PAR_BE0 (0x01)
1158 #define GPIO_PAR_BE1 (0x02)
1159 #define GPIO_PAR_BE2 (0x04)
1160 #define GPIO_PAR_BE3 (0x08)
1162 /* Bit definitions and macros for GPIO_PAR_CS */
1163 #define GPIO_PAR_CS1 (0x02)
1164 #define GPIO_PAR_CS2 (0x04)
1165 #define GPIO_PAR_CS3 (0x08)
1166 #define GPIO_PAR_CS4 (0x10)
1167 #define GPIO_PAR_CS5 (0x20)
1168 #define GPIO_PAR_CS1_GPIO (0x00)
1169 #define GPIO_PAR_CS1_SDCS1 (0x01)
1170 #define GPIO_PAR_CS1_CS1 (0x03)
1172 /* Bit definitions and macros for GPIO_PAR_SSI */
1173 #define GPIO_PAR_SSI_MCLK (0x0080)
1174 #define GPIO_PAR_SSI_TXD(x) (((x)&0x0003)<<8)
1175 #define GPIO_PAR_SSI_RXD(x) (((x)&0x0003)<<10)
1176 #define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<12)
1177 #define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<14)
1179 /* Bit definitions and macros for GPIO_PAR_UART */
1180 #define GPIO_PAR_UART_TXD0 (0x0001)
1181 #define GPIO_PAR_UART_RXD0 (0x0002)
1182 #define GPIO_PAR_UART_RTS0 (0x0004)
1183 #define GPIO_PAR_UART_CTS0 (0x0008)
1184 #define GPIO_PAR_UART_TXD1(x) (((x)&0x0003)<<4)
1185 #define GPIO_PAR_UART_RXD1(x) (((x)&0x0003)<<6)
1186 #define GPIO_PAR_UART_RTS1(x) (((x)&0x0003)<<8)
1187 #define GPIO_PAR_UART_CTS1(x) (((x)&0x0003)<<10)
1188 #define GPIO_PAR_UART_CTS1_GPIO (0x0000)
1189 #define GPIO_PAR_UART_CTS1_SSI_BCLK (0x0800)
1190 #define GPIO_PAR_UART_CTS1_ULPI_D7 (0x0400)
1191 #define GPIO_PAR_UART_CTS1_UCTS1 (0x0C00)
1192 #define GPIO_PAR_UART_RTS1_GPIO (0x0000)
1193 #define GPIO_PAR_UART_RTS1_SSI_FS (0x0200)
1194 #define GPIO_PAR_UART_RTS1_ULPI_D6 (0x0100)
1195 #define GPIO_PAR_UART_RTS1_URTS1 (0x0300)
1196 #define GPIO_PAR_UART_RXD1_GPIO (0x0000)
1197 #define GPIO_PAR_UART_RXD1_SSI_RXD (0x0080)
1198 #define GPIO_PAR_UART_RXD1_ULPI_D5 (0x0040)
1199 #define GPIO_PAR_UART_RXD1_URXD1 (0x00C0)
1200 #define GPIO_PAR_UART_TXD1_GPIO (0x0000)
1201 #define GPIO_PAR_UART_TXD1_SSI_TXD (0x0020)
1202 #define GPIO_PAR_UART_TXD1_ULPI_D4 (0x0010)
1203 #define GPIO_PAR_UART_TXD1_UTXD1 (0x0030)
1205 /* Bit definitions and macros for GPIO_PAR_QSPI */
1206 #define GPIO_PAR_QSPI_SCK(x) (((x)&0x0003)<<4)
1207 #define GPIO_PAR_QSPI_DOUT(x) (((x)&0x0003)<<6)
1208 #define GPIO_PAR_QSPI_DIN(x) (((x)&0x0003)<<8)
1209 #define GPIO_PAR_QSPI_PCS0(x) (((x)&0x0003)<<10)
1210 #define GPIO_PAR_QSPI_PCS1(x) (((x)&0x0003)<<12)
1211 #define GPIO_PAR_QSPI_PCS2(x) (((x)&0x0003)<<14)
1213 /* Bit definitions and macros for GPIO_PAR_TIMER */
1214 #define GPIO_PAR_TIN0(x) (((x)&0x03)<<0)
1215 #define GPIO_PAR_TIN1(x) (((x)&0x03)<<2)
1216 #define GPIO_PAR_TIN2(x) (((x)&0x03)<<4)
1217 #define GPIO_PAR_TIN3(x) (((x)&0x03)<<6)
1218 #define GPIO_PAR_TIN3_GPIO (0x00)
1219 #define GPIO_PAR_TIN3_TOUT3 (0x80)
1220 #define GPIO_PAR_TIN3_URXD2 (0x40)
1221 #define GPIO_PAR_TIN3_TIN3 (0xC0)
1222 #define GPIO_PAR_TIN2_GPIO (0x00)
1223 #define GPIO_PAR_TIN2_TOUT2 (0x20)
1224 #define GPIO_PAR_TIN2_UTXD2 (0x10)
1225 #define GPIO_PAR_TIN2_TIN2 (0x30)
1226 #define GPIO_PAR_TIN1_GPIO (0x00)
1227 #define GPIO_PAR_TIN1_TOUT1 (0x08)
1228 #define GPIO_PAR_TIN1_DACK1 (0x04)
1229 #define GPIO_PAR_TIN1_TIN1 (0x0C)
1230 #define GPIO_PAR_TIN0_GPIO (0x00)
1231 #define GPIO_PAR_TIN0_TOUT0 (0x02)
1232 #define GPIO_PAR_TIN0_DREQ0 (0x01)
1233 #define GPIO_PAR_TIN0_TIN0 (0x03)
1235 /* Bit definitions and macros for GPIO_PAR_LCDDATA */
1236 #define GPIO_PAR_LCDDATA_LD7_0(x) ((x)&0x03)
1237 #define GPIO_PAR_LCDDATA_LD15_8(x) (((x)&0x03)<<2)
1238 #define GPIO_PAR_LCDDATA_LD16(x) (((x)&0x03)<<4)
1239 #define GPIO_PAR_LCDDATA_LD17(x) (((x)&0x03)<<6)
1241 /* Bit definitions and macros for GPIO_PAR_LCDCTL */
1242 #define GPIO_PAR_LCDCTL_CLS (0x0001)
1243 #define GPIO_PAR_LCDCTL_PS (0x0002)
1244 #define GPIO_PAR_LCDCTL_REV (0x0004)
1245 #define GPIO_PAR_LCDCTL_SPL_SPR (0x0008)
1246 #define GPIO_PAR_LCDCTL_CONTRAST (0x0010)
1247 #define GPIO_PAR_LCDCTL_LSCLK (0x0020)
1248 #define GPIO_PAR_LCDCTL_LP_HSYNC (0x0040)
1249 #define GPIO_PAR_LCDCTL_FLM_VSYNC (0x0080)
1250 #define GPIO_PAR_LCDCTL_ACD_OE (0x0100)
1252 /* Bit definitions and macros for GPIO_PAR_IRQ */
1253 #define GPIO_PAR_IRQ1(x) (((x)&0x0003)<<4)
1254 #define GPIO_PAR_IRQ2(x) (((x)&0x0003)<<6)
1255 #define GPIO_PAR_IRQ4(x) (((x)&0x0003)<<8)
1256 #define GPIO_PAR_IRQ5(x) (((x)&0x0003)<<10)
1257 #define GPIO_PAR_IRQ6(x) (((x)&0x0003)<<12)
1259 /* Bit definitions and macros for GPIO_MSCR_FLEXBUS */
1260 #define GPIO_MSCR_FLEXBUS_ADDRCTL(x) ((x)&0x03)
1261 #define GPIO_MSCR_FLEXBUS_DLOWER(x) (((x)&0x03)<<2)
1262 #define GPIO_MSCR_FLEXBUS_DUPPER(x) (((x)&0x03)<<4)
1264 /* Bit definitions and macros for GPIO_MSCR_SDRAM */
1265 #define GPIO_MSCR_SDRAM_SDRAM(x) ((x)&0x03)
1266 #define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2)
1267 #define GPIO_MSCR_SDRAM_SDCLKB(x) (((x)&0x03)<<4)
1269 /* Bit definitions and macros for GPIO_DSCR_I2C */
1270 #define GPIO_DSCR_I2C_DSE(x) ((x)&0x03)
1272 /* Bit definitions and macros for GPIO_DSCR_PWM */
1273 #define GPIO_DSCR_PWM_DSE(x) ((x)&0x03)
1275 /* Bit definitions and macros for GPIO_DSCR_FEC */
1276 #define GPIO_DSCR_FEC_DSE(x) ((x)&0x03)
1278 /* Bit definitions and macros for GPIO_DSCR_UART */
1279 #define GPIO_DSCR_UART0_DSE(x) ((x)&0x03)
1280 #define GPIO_DSCR_UART1_DSE(x) (((x)&0x03)<<2)
1282 /* Bit definitions and macros for GPIO_DSCR_QSPI */
1283 #define GPIO_DSCR_QSPI_DSE(x) ((x)&0x03)
1285 /* Bit definitions and macros for GPIO_DSCR_TIMER */
1286 #define GPIO_DSCR_TIMER_DSE(x) ((x)&0x03)
1288 /* Bit definitions and macros for GPIO_DSCR_SSI */
1289 #define GPIO_DSCR_SSI_DSE(x) ((x)&0x03)
1291 /* Bit definitions and macros for GPIO_DSCR_LCD */
1292 #define GPIO_DSCR_LCD_DSE(x) ((x)&0x03)
1294 /* Bit definitions and macros for GPIO_DSCR_DEBUG */
1295 #define GPIO_DSCR_DEBUG_DSE(x) ((x)&0x03)
1297 /* Bit definitions and macros for GPIO_DSCR_CLKRST */
1298 #define GPIO_DSCR_CLKRST_DSE(x) ((x)&0x03)
1300 /* Bit definitions and macros for GPIO_DSCR_IRQ */
1301 #define GPIO_DSCR_IRQ_DSE(x) ((x)&0x03)
1304 /*********************************************************************
1305 * LCD Controller (LCDC)
1306 *********************************************************************/
1307 /* Bit definitions and macros for LCDC_LSSAR */
1308 #define LCDC_LSSAR_SSA(x) (((x)&0x3FFFFFFF)<<2)
1310 /* Bit definitions and macros for LCDC_LSR */
1311 #define LCDC_LSR_YMAX(x) (((x)&0x000003FF)<<0)
1312 #define LCDC_LSR_XMAX(x) (((x)&0x0000003F)<<20)
1314 /* Bit definitions and macros for LCDC_LVPWR */
1315 #define LCDC_LVPWR_VPW(x) (((x)&0x000003FF)<<0)
1317 /* Bit definitions and macros for LCDC_LCPR */
1318 #define LCDC_LCPR_CYP(x) (((x)&0x000003FF)<<0)
1319 #define LCDC_LCPR_CXP(x) (((x)&0x000003FF)<<16)
1320 #define LCDC_LCPR_OP (0x10000000)
1321 #define LCDC_LCPR_CC(x) (((x)&0x00000003)<<30)
1322 #define LCDC_LCPR_CC_TRANSPARENT (0x00000000)
1323 #define LCDC_LCPR_CC_OR (0x40000000)
1324 #define LCDC_LCPR_CC_XOR (0x80000000)
1325 #define LCDC_LCPR_CC_AND (0xC0000000)
1326 #define LCDC_LCPR_OP_ON (0x10000000)
1327 #define LCDC_LCPR_OP_OFF (0x00000000)
1329 /* Bit definitions and macros for LCDC_LCWHBR */
1330 #define LCDC_LCWHBR_BD(x) (((x)&0x000000FF)<<0)
1331 #define LCDC_LCWHBR_CH(x) (((x)&0x0000001F)<<16)
1332 #define LCDC_LCWHBR_CW(x) (((x)&0x0000001F)<<24)
1333 #define LCDC_LCWHBR_BK_EN (0x80000000)
1334 #define LCDC_LCWHBR_BK_EN_ON (0x80000000)
1335 #define LCDC_LCWHBR_BK_EN_OFF (0x00000000)
1337 /* Bit definitions and macros for LCDC_LCCMR */
1338 #define LCDC_LCCMR_CUR_COL_B(x) (((x)&0x0000003F)<<0)
1339 #define LCDC_LCCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6)
1340 #define LCDC_LCCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12)
1342 /* Bit definitions and macros for LCDC_LPCR */
1343 #define LCDC_LPCR_PCD(x) (((x)&0x0000003F)<<0)
1344 #define LCDC_LPCR_SHARP (0x00000040)
1345 #define LCDC_LPCR_SCLKSEL (0x00000080)
1346 #define LCDC_LPCR_ACD(x) (((x)&0x0000007F)<<8)
1347 #define LCDC_LPCR_ACDSEL (0x00008000)
1348 #define LCDC_LPCR_REV_VS (0x00010000)
1349 #define LCDC_LPCR_SWAP_SEL (0x00020000)
1350 #define LCDC_LPCR_ENDSEL (0x00040000)
1351 #define LCDC_LPCR_SCLKIDLE (0x00080000)
1352 #define LCDC_LPCR_OEPOL (0x00100000)
1353 #define LCDC_LPCR_CLKPOL (0x00200000)
1354 #define LCDC_LPCR_LPPOL (0x00400000)
1355 #define LCDC_LPCR_FLM (0x00800000)
1356 #define LCDC_LPCR_PIXPOL (0x01000000)
1357 #define LCDC_LPCR_BPIX(x) (((x)&0x00000007)<<25)
1358 #define LCDC_LPCR_PBSIZ(x) (((x)&0x00000003)<<28)
1359 #define LCDC_LPCR_COLOR (0x40000000)
1360 #define LCDC_LPCR_TFT (0x80000000)
1361 #define LCDC_LPCR_MODE_MONOCHROME (0x00000000)
1362 #define LCDC_LPCR_MODE_CSTN (0x40000000)
1363 #define LCDC_LPCR_MODE_TFT (0xC0000000)
1364 #define LCDC_LPCR_PBSIZ_1 (0x00000000)
1365 #define LCDC_LPCR_PBSIZ_2 (0x10000000)
1366 #define LCDC_LPCR_PBSIZ_4 (0x20000000)
1367 #define LCDC_LPCR_PBSIZ_8 (0x30000000)
1368 #define LCDC_LPCR_BPIX_1bpp (0x00000000)
1369 #define LCDC_LPCR_BPIX_2bpp (0x02000000)
1370 #define LCDC_LPCR_BPIX_4bpp (0x04000000)
1371 #define LCDC_LPCR_BPIX_8bpp (0x06000000)
1372 #define LCDC_LPCR_BPIX_12bpp (0x08000000)
1373 #define LCDC_LPCR_BPIX_16bpp (0x0A000000)
1374 #define LCDC_LPCR_BPIX_18bpp (0x0C000000)
1376 #define LCDC_LPCR_PANEL_TYPE(x) (((x)&0x00000003)<<30)
1378 /* Bit definitions and macros for LCDC_LHCR */
1379 #define LCDC_LHCR_H_WAIT_2(x) (((x)&0x000000FF)<<0)
1380 #define LCDC_LHCR_H_WAIT_1(x) (((x)&0x000000FF)<<8)
1381 #define LCDC_LHCR_H_WIDTH(x) (((x)&0x0000003F)<<26)
1383 /* Bit definitions and macros for LCDC_LVCR */
1384 #define LCDC_LVCR_V_WAIT_2(x) (((x)&0x000000FF)<<0)
1385 #define LCDC_LVCR_V_WAIT_1(x) (((x)&0x000000FF)<<8)
1386 #define LCDC_LVCR_V_WIDTH(x) (((x)&0x0000003F)<<26)
1388 /* Bit definitions and macros for LCDC_LPOR */
1389 #define LCDC_LPOR_POS(x) (((x)&0x0000001F)<<0)
1391 /* Bit definitions and macros for LCDC_LPCCR */
1392 #define LCDC_LPCCR_PW(x) (((x)&0x000000FF)<<0)
1393 #define LCDC_LPCCR_CC_EN (0x00000100)
1394 #define LCDC_LPCCR_SCR(x) (((x)&0x00000003)<<9)
1395 #define LCDC_LPCCR_LDMSK (0x00008000)
1396 #define LCDC_LPCCR_CLS_HI_WIDTH(x) (((x)&0x000001FF)<<16)
1397 #define LCDC_LPCCR_SCR_LINEPULSE (0x00000000)
1398 #define LCDC_LPCCR_SCR_PIXELCLK (0x00002000)
1399 #define LCDC_LPCCR_SCR_LCDCLOCK (0x00004000)
1401 /* Bit definitions and macros for LCDC_LDCR */
1402 #define LCDC_LDCR_TM(x) (((x)&0x0000001F)<<0)
1403 #define LCDC_LDCR_HM(x) (((x)&0x0000001F)<<16)
1404 #define LCDC_LDCR_BURST (0x80000000)
1406 /* Bit definitions and macros for LCDC_LRMCR */
1407 #define LCDC_LRMCR_SEL_REF (0x00000001)
1409 /* Bit definitions and macros for LCDC_LICR */
1410 #define LCDC_LICR_INTCON (0x00000001)
1411 #define LCDC_LICR_INTSYN (0x00000004)
1412 #define LCDC_LICR_GW_INT_CON (0x00000010)
1414 /* Bit definitions and macros for LCDC_LIER */
1415 #define LCDC_LIER_BOF_EN (0x00000001)
1416 #define LCDC_LIER_EOF_EN (0x00000002)
1417 #define LCDC_LIER_ERR_RES_EN (0x00000004)
1418 #define LCDC_LIER_UDR_ERR_EN (0x00000008)
1419 #define LCDC_LIER_GW_BOF_EN (0x00000010)
1420 #define LCDC_LIER_GW_EOF_EN (0x00000020)
1421 #define LCDC_LIER_GW_ERR_RES_EN (0x00000040)
1422 #define LCDC_LIER_GW_UDR_ERR_EN (0x00000080)
1424 /* Bit definitions and macros for LCDC_LISR */
1425 #define LCDC_LISR_BOF (0x00000001)
1426 #define LCDC_LISR_EOF (0x00000002)
1427 #define LCDC_LISR_ERR_RES (0x00000004)
1428 #define LCDC_LISR_UDR_ERR (0x00000008)
1429 #define LCDC_LISR_GW_BOF (0x00000010)
1430 #define LCDC_LISR_GW_EOF (0x00000020)
1431 #define LCDC_LISR_GW_ERR_RES (0x00000040)
1432 #define LCDC_LISR_GW_UDR_ERR (0x00000080)
1434 /* Bit definitions and macros for LCDC_LGWSAR */
1435 #define LCDC_LGWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2)
1437 /* Bit definitions and macros for LCDC_LGWSR */
1438 #define LCDC_LGWSR_GWH(x) (((x)&0x000003FF)<<0)
1439 #define LCDC_LGWSR_GWW(x) (((x)&0x0000003F)<<20)
1441 /* Bit definitions and macros for LCDC_LGWVPWR */
1442 #define LCDC_LGWVPWR_GWVPW(x) (((x)&0x000003FF)<<0)
1444 /* Bit definitions and macros for LCDC_LGWPOR */
1445 #define LCDC_LGWPOR_GWPO(x) (((x)&0x0000001F)<<0)
1447 /* Bit definitions and macros for LCDC_LGWPR */
1448 #define LCDC_LGWPR_GWYP(x) (((x)&0x000003FF)<<0)
1449 #define LCDC_LGWPR_GWXP(x) (((x)&0x000003FF)<<16)
1451 /* Bit definitions and macros for LCDC_LGWCR */
1452 #define LCDC_LGWCR_GWCKB(x) (((x)&0x0000003F)<<0)
1453 #define LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6)
1454 #define LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12)
1455 #define LCDC_LGWCR_GW_RVS (0x00200000)
1456 #define LCDC_LGWCR_GWE (0x00400000)
1457 #define LCDC_LGWCR_GWCKE (0x00800000)
1458 #define LCDC_LGWCR_GWAV(x) (((x)&0x000000FF)<<24)
1460 /* Bit definitions and macros for LCDC_LGWDCR */
1461 #define LCDC_LGWDCR_GWTM(x) (((x)&0x0000001F)<<0)
1462 #define LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16)
1463 #define LCDC_LGWDCR_GWBT (0x80000000)
1465 /*********************************************************************
1466 * SDRAM Controller (SDRAMC)
1467 *********************************************************************/
1468 /* Bit definitions and macros for SDRAMC_SDMR */
1469 #define SDRAMC_SDMR_BNKAD_LEMR (0x40000000)
1470 #define SDRAMC_SDMR_BNKAD_LMR (0x00000000)
1471 #define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18)
1472 #define SDRAMC_SDMR_CMD (0x00010000)
1474 /* Bit definitions and macros for SDRAMC_SDCR */
1475 #define SDRAMC_SDCR_MODE_EN (0x80000000)
1476 #define SDRAMC_SDCR_CKE (0x40000000)
1477 #define SDRAMC_SDCR_DDR (0x20000000)
1478 #define SDRAMC_SDCR_REF (0x10000000)
1479 #define SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24)
1480 #define SDRAMC_SDCR_OE_RULE (0x00400000)
1481 #define SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16)
1482 #define SDRAMC_SDCR_PS_32 (0x00000000)
1483 #define SDRAMC_SDCR_PS_16 (0x00002000)
1484 #define SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8)
1485 #define SDRAMC_SDCR_IREF (0x00000004)
1486 #define SDRAMC_SDCR_IPALL (0x00000002)
1488 /* Bit definitions and macros for SDRAMC_SDCFG1 */
1489 #define SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28)
1490 #define SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24)
1491 #define SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20)
1492 #define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16)
1493 #define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12)
1494 #define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8)
1495 #define SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4)
1497 /* Bit definitions and macros for SDRAMC_SDCFG2 */
1498 #define SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28)
1499 #define SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24)
1500 #define SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20)
1501 #define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16)
1503 /* Bit definitions and macros for SDRAMC_SDDS */
1504 #define SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8)
1505 #define SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6)
1506 #define SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4)
1507 #define SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2)
1508 #define SDRAMC_SDDS_SB_D(x) ((x)&0x00000003)
1510 /* Bit definitions and macros for SDRAMC_SDCS */
1511 #define SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20)
1512 #define SDRAMC_SDCS_CSSZ(x) ((x)&0x0000001F)
1513 #define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
1514 #define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
1515 #define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
1516 #define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
1517 #define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
1518 #define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
1519 #define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
1520 #define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
1521 #define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
1522 #define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
1523 #define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
1524 #define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
1525 #define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
1526 #define SDRAMC_SDCS_CSSZ_DIABLE (0x00000000)
1528 /*********************************************************************
1529 * Synchronous Serial Interface (SSI)
1530 *********************************************************************/
1531 /* Bit definitions and macros for SSI_CR */
1532 #define SSI_CR_CIS (0x00000200)
1533 #define SSI_CR_TCH (0x00000100)
1534 #define SSI_CR_MCE (0x00000080)
1535 #define SSI_CR_I2S_SLAVE (0x00000040)
1536 #define SSI_CR_I2S_MASTER (0x00000020)
1537 #define SSI_CR_I2S_NORMAL (0x00000000)
1538 #define SSI_CR_SYN (0x00000010)
1539 #define SSI_CR_NET (0x00000008)
1540 #define SSI_CR_RE (0x00000004)
1541 #define SSI_CR_TE (0x00000002)
1542 #define SSI_CR_SSI_EN (0x00000001)
1544 /* Bit definitions and macros for SSI_ISR */
1545 #define SSI_ISR_CMDAU (0x00040000)
1546 #define SSI_ISR_CMDDU (0x00020000)
1547 #define SSI_ISR_RXT (0x00010000)
1548 #define SSI_ISR_RDR1 (0x00008000)
1549 #define SSI_ISR_RDR0 (0x00004000)
1550 #define SSI_ISR_TDE1 (0x00002000)
1551 #define SSI_ISR_TDE0 (0x00001000)
1552 #define SSI_ISR_ROE1 (0x00000800)
1553 #define SSI_ISR_ROE0 (0x00000400)
1554 #define SSI_ISR_TUE1 (0x00000200)
1555 #define SSI_ISR_TUE0 (0x00000100)
1556 #define SSI_ISR_TFS (0x00000080)
1557 #define SSI_ISR_RFS (0x00000040)
1558 #define SSI_ISR_TLS (0x00000020)
1559 #define SSI_ISR_RLS (0x00000010)
1560 #define SSI_ISR_RFF1 (0x00000008)
1561 #define SSI_ISR_RFF0 (0x00000004)
1562 #define SSI_ISR_TFE1 (0x00000002)
1563 #define SSI_ISR_TFE0 (0x00000001)
1565 /* Bit definitions and macros for SSI_IER */
1566 #define SSI_IER_RDMAE (0x00400000)
1567 #define SSI_IER_RIE (0x00200000)
1568 #define SSI_IER_TDMAE (0x00100000)
1569 #define SSI_IER_TIE (0x00080000)
1570 #define SSI_IER_CMDAU (0x00040000)
1571 #define SSI_IER_CMDU (0x00020000)
1572 #define SSI_IER_RXT (0x00010000)
1573 #define SSI_IER_RDR1 (0x00008000)
1574 #define SSI_IER_RDR0 (0x00004000)
1575 #define SSI_IER_TDE1 (0x00002000)
1576 #define SSI_IER_TDE0 (0x00001000)
1577 #define SSI_IER_ROE1 (0x00000800)
1578 #define SSI_IER_ROE0 (0x00000400)
1579 #define SSI_IER_TUE1 (0x00000200)
1580 #define SSI_IER_TUE0 (0x00000100)
1581 #define SSI_IER_TFS (0x00000080)
1582 #define SSI_IER_RFS (0x00000040)
1583 #define SSI_IER_TLS (0x00000020)
1584 #define SSI_IER_RLS (0x00000010)
1585 #define SSI_IER_RFF1 (0x00000008)
1586 #define SSI_IER_RFF0 (0x00000004)
1587 #define SSI_IER_TFE1 (0x00000002)
1588 #define SSI_IER_TFE0 (0x00000001)
1590 /* Bit definitions and macros for SSI_TCR */
1591 #define SSI_TCR_TXBIT0 (0x00000200)
1592 #define SSI_TCR_TFEN1 (0x00000100)
1593 #define SSI_TCR_TFEN0 (0x00000080)
1594 #define SSI_TCR_TFDIR (0x00000040)
1595 #define SSI_TCR_TXDIR (0x00000020)
1596 #define SSI_TCR_TSHFD (0x00000010)
1597 #define SSI_TCR_TSCKP (0x00000008)
1598 #define SSI_TCR_TFSI (0x00000004)
1599 #define SSI_TCR_TFSL (0x00000002)
1600 #define SSI_TCR_TEFS (0x00000001)
1602 /* Bit definitions and macros for SSI_RCR */
1603 #define SSI_RCR_RXEXT (0x00000400)
1604 #define SSI_RCR_RXBIT0 (0x00000200)
1605 #define SSI_RCR_RFEN1 (0x00000100)
1606 #define SSI_RCR_RFEN0 (0x00000080)
1607 #define SSI_RCR_RSHFD (0x00000010)
1608 #define SSI_RCR_RSCKP (0x00000008)
1609 #define SSI_RCR_RFSI (0x00000004)
1610 #define SSI_RCR_RFSL (0x00000002)
1611 #define SSI_RCR_REFS (0x00000001)
1613 /* Bit definitions and macros for SSI_CCR */
1614 #define SSI_CCR_DIV2 (0x00040000)
1615 #define SSI_CCR_PSR (0x00020000)
1616 #define SSI_CCR_WL(x) (((x)&0x0000000F)<<13)
1617 #define SSI_CCR_DC(x) (((x)&0x0000001F)<<8)
1618 #define SSI_CCR_PM(x) ((x)&0x000000FF)
1620 /* Bit definitions and macros for SSI_FCSR */
1621 #define SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28)
1622 #define SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24)
1623 #define SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20)
1624 #define SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16)
1625 #define SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12)
1626 #define SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8)
1627 #define SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4)
1628 #define SSI_FCSR_TFWM0(x) ((x)&0x0000000F)
1630 /* Bit definitions and macros for SSI_ACR */
1631 #define SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5)
1632 #define SSI_ACR_WR (0x00000010)
1633 #define SSI_ACR_RD (0x00000008)
1634 #define SSI_ACR_TIF (0x00000004)
1635 #define SSI_ACR_FV (0x00000002)
1636 #define SSI_ACR_AC97EN (0x00000001)
1638 /* Bit definitions and macros for SSI_ACADD */
1639 #define SSI_ACADD_SSI_ACADD(x) ((x)&0x0007FFFF)
1641 /* Bit definitions and macros for SSI_ACDAT */
1642 #define SSI_ACDAT_SSI_ACDAT(x) ((x)&0x0007FFFF)
1644 /* Bit definitions and macros for SSI_ATAG */
1645 #define SSI_ATAG_DDI_ATAG(x) ((x)&0x0000FFFF)
1647 /*********************************************************************
1648 * Phase Locked Loop (PLL)
1649 *********************************************************************/
1650 /* Bit definitions and macros for PLL_PODR */
1651 #define PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4)
1652 #define PLL_PODR_BUSDIV(x) ((x)&0x0F)
1654 /* Bit definitions and macros for PLL_PLLCR */
1655 #define PLL_PLLCR_DITHEN (0x80)
1656 #define PLL_PLLCR_DITHDEV(x) ((x)&0x07)
1658 #endif /* mcf5329_h */