3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1k CPU.
6 * Copyright 2000,2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
39 /* cpu pipeline flush */
40 void static inline au_sync(void)
42 __asm__ volatile ("sync");
45 void static inline au_sync_udelay(int us)
47 __asm__ volatile ("sync");
51 void static inline au_writeb(u8 val, int reg)
53 *(volatile u8 *)(reg) = val;
56 void static inline au_writew(u16 val, int reg)
58 *(volatile u16 *)(reg) = val;
61 void static inline au_writel(u32 val, int reg)
63 *(volatile u32 *)(reg) = val;
66 static inline u8 au_readb(unsigned long port)
68 return (*(volatile u8 *)port);
71 static inline u16 au_readw(unsigned long port)
73 return (*(volatile u16 *)port);
76 static inline u32 au_readl(unsigned long port)
78 return (*(volatile u32 *)port);
81 /* These next three functions should be a generic part of the MIPS
82 * kernel (with the 'au_' removed from the name) and selected for
83 * processors that support the instructions.
84 * Taken from PPC tree. -- Dan
86 /* Return the bit position of the most significant 1 bit in a word */
87 static __inline__ int __ilog2(unsigned int x)
105 static __inline__ int au_ffz(unsigned int x)
109 return __ilog2(x & -x);
113 * ffs: find first bit set. This is defined the same way as
114 * the libc and compiler builtin ffs routines, therefore
115 * differs in spirit from the above ffz (man ffs).
117 static __inline__ int au_ffs(int x)
119 return __ilog2(x & -x) + 1;
122 #endif /* !ASSEMBLY */
125 /* no CP0 timer irq */
126 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
128 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
131 /* SDRAM Controller */
132 #define MEM_SDMODE0 0xB4000000
133 #define MEM_SDMODE1 0xB4000004
134 #define MEM_SDMODE2 0xB4000008
136 #define MEM_SDADDR0 0xB400000C
137 #define MEM_SDADDR1 0xB4000010
138 #define MEM_SDADDR2 0xB4000014
140 #define MEM_SDREFCFG 0xB4000018
141 #define MEM_SDPRECMD 0xB400001C
142 #define MEM_SDAUTOREF 0xB4000020
144 #define MEM_SDWRMD0 0xB4000024
145 #define MEM_SDWRMD1 0xB4000028
146 #define MEM_SDWRMD2 0xB400002C
148 #define MEM_SDSLEEP 0xB4000030
149 #define MEM_SDSMCKE 0xB4000034
151 /* Static Bus Controller */
152 #define MEM_STCFG0 0xB4001000
153 #define MEM_STTIME0 0xB4001004
154 #define MEM_STADDR0 0xB4001008
156 #define MEM_STCFG1 0xB4001010
157 #define MEM_STTIME1 0xB4001014
158 #define MEM_STADDR1 0xB4001018
160 #define MEM_STCFG2 0xB4001020
161 #define MEM_STTIME2 0xB4001024
162 #define MEM_STADDR2 0xB4001028
164 #define MEM_STCFG3 0xB4001030
165 #define MEM_STTIME3 0xB4001034
166 #define MEM_STADDR3 0xB4001038
168 /* Interrupt Controller 0 */
169 #define IC0_CFG0RD 0xB0400040
170 #define IC0_CFG0SET 0xB0400040
171 #define IC0_CFG0CLR 0xB0400044
173 #define IC0_CFG1RD 0xB0400048
174 #define IC0_CFG1SET 0xB0400048
175 #define IC0_CFG1CLR 0xB040004C
177 #define IC0_CFG2RD 0xB0400050
178 #define IC0_CFG2SET 0xB0400050
179 #define IC0_CFG2CLR 0xB0400054
181 #define IC0_REQ0INT 0xB0400054
182 #define IC0_SRCRD 0xB0400058
183 #define IC0_SRCSET 0xB0400058
184 #define IC0_SRCCLR 0xB040005C
185 #define IC0_REQ1INT 0xB040005C
187 #define IC0_ASSIGNRD 0xB0400060
188 #define IC0_ASSIGNSET 0xB0400060
189 #define IC0_ASSIGNCLR 0xB0400064
191 #define IC0_WAKERD 0xB0400068
192 #define IC0_WAKESET 0xB0400068
193 #define IC0_WAKECLR 0xB040006C
195 #define IC0_MASKRD 0xB0400070
196 #define IC0_MASKSET 0xB0400070
197 #define IC0_MASKCLR 0xB0400074
199 #define IC0_RISINGRD 0xB0400078
200 #define IC0_RISINGCLR 0xB0400078
201 #define IC0_FALLINGRD 0xB040007C
202 #define IC0_FALLINGCLR 0xB040007C
204 #define IC0_TESTBIT 0xB0400080
206 /* Interrupt Controller 1 */
207 #define IC1_CFG0RD 0xB1800040
208 #define IC1_CFG0SET 0xB1800040
209 #define IC1_CFG0CLR 0xB1800044
211 #define IC1_CFG1RD 0xB1800048
212 #define IC1_CFG1SET 0xB1800048
213 #define IC1_CFG1CLR 0xB180004C
215 #define IC1_CFG2RD 0xB1800050
216 #define IC1_CFG2SET 0xB1800050
217 #define IC1_CFG2CLR 0xB1800054
219 #define IC1_REQ0INT 0xB1800054
220 #define IC1_SRCRD 0xB1800058
221 #define IC1_SRCSET 0xB1800058
222 #define IC1_SRCCLR 0xB180005C
223 #define IC1_REQ1INT 0xB180005C
225 #define IC1_ASSIGNRD 0xB1800060
226 #define IC1_ASSIGNSET 0xB1800060
227 #define IC1_ASSIGNCLR 0xB1800064
229 #define IC1_WAKERD 0xB1800068
230 #define IC1_WAKESET 0xB1800068
231 #define IC1_WAKECLR 0xB180006C
233 #define IC1_MASKRD 0xB1800070
234 #define IC1_MASKSET 0xB1800070
235 #define IC1_MASKCLR 0xB1800074
237 #define IC1_RISINGRD 0xB1800078
238 #define IC1_RISINGCLR 0xB1800078
239 #define IC1_FALLINGRD 0xB180007C
240 #define IC1_FALLINGCLR 0xB180007C
242 #define IC1_TESTBIT 0xB1800080
244 /* Interrupt Configuration Modes */
245 #define INTC_INT_DISABLED 0
246 #define INTC_INT_RISE_EDGE 0x1
247 #define INTC_INT_FALL_EDGE 0x2
248 #define INTC_INT_RISE_AND_FALL_EDGE 0x3
249 #define INTC_INT_HIGH_LEVEL 0x5
250 #define INTC_INT_LOW_LEVEL 0x6
251 #define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
253 /* Interrupt Numbers */
254 #define AU1X00_UART0_INT 0
255 #define AU1000_UART1_INT 1 /* au1000 */
256 #define AU1000_UART2_INT 2 /* au1000 */
258 #define AU1500_PCI_INTA 1 /* au1500 */
259 #define AU1500_PCI_INTB 2 /* au1500 */
261 #define AU1X00_UART3_INT 3
263 #define AU1000_SSI0_INT 4 /* au1000 */
264 #define AU1000_SSI1_INT 5 /* au1000 */
266 #define AU1500_PCI_INTC 4 /* au1500 */
267 #define AU1500_PCI_INTD 5 /* au1500 */
269 #define AU1X00_DMA_INT_BASE 6
270 #define AU1X00_TOY_INT 14
271 #define AU1X00_TOY_MATCH0_INT 15
272 #define AU1X00_TOY_MATCH1_INT 16
273 #define AU1X00_TOY_MATCH2_INT 17
274 #define AU1X00_RTC_INT 18
275 #define AU1X00_RTC_MATCH0_INT 19
276 #define AU1X00_RTC_MATCH1_INT 20
277 #define AU1X00_RTC_MATCH2_INT 21
278 #define AU1000_IRDA_TX_INT 22 /* au1000 */
279 #define AU1000_IRDA_RX_INT 23 /* au1000 */
280 #define AU1X00_USB_DEV_REQ_INT 24
281 #define AU1X00_USB_DEV_SUS_INT 25
282 #define AU1X00_USB_HOST_INT 26
283 #define AU1X00_ACSYNC_INT 27
284 #define AU1X00_MAC0_DMA_INT 28
285 #define AU1X00_MAC1_DMA_INT 29
286 #define AU1X00_ETH0_IRQ AU1X00_MAC0_DMA_INT
287 #define AU1X00_ETH1_IRQ AU1X00_MAC1_DMA_INT
288 #define AU1000_I2S_UO_INT 30 /* au1000 */
289 #define AU1X00_AC97C_INT 31
290 #define AU1X00_LAST_INTC0_INT AU1X00_AC97C_INT
291 #define AU1X00_GPIO_0 32
292 #define AU1X00_GPIO_1 33
293 #define AU1X00_GPIO_2 34
294 #define AU1X00_GPIO_3 35
295 #define AU1X00_GPIO_4 36
296 #define AU1X00_GPIO_5 37
297 #define AU1X00_GPIO_6 38
298 #define AU1X00_GPIO_7 39
299 #define AU1X00_GPIO_8 40
300 #define AU1X00_GPIO_9 41
301 #define AU1X00_GPIO_10 42
302 #define AU1X00_GPIO_11 43
303 #define AU1X00_GPIO_12 44
304 #define AU1X00_GPIO_13 45
305 #define AU1X00_GPIO_14 46
306 #define AU1X00_GPIO_15 47
309 #define AU1000_GPIO_16 48
310 #define AU1000_GPIO_17 49
311 #define AU1000_GPIO_18 50
312 #define AU1000_GPIO_19 51
313 #define AU1000_GPIO_20 52
314 #define AU1000_GPIO_21 53
315 #define AU1000_GPIO_22 54
316 #define AU1000_GPIO_23 55
317 #define AU1000_GPIO_24 56
318 #define AU1000_GPIO_25 57
319 #define AU1000_GPIO_26 58
320 #define AU1000_GPIO_27 59
321 #define AU1000_GPIO_28 60
322 #define AU1000_GPIO_29 61
323 #define AU1000_GPIO_30 62
324 #define AU1000_GPIO_31 63
327 #define AU1500_GPIO_200 48
328 #define AU1500_GPIO_201 49
329 #define AU1500_GPIO_202 50
330 #define AU1500_GPIO_203 51
331 #define AU1500_GPIO_20 52
332 #define AU1500_GPIO_204 53
333 #define AU1500_GPIO_205 54
334 #define AU1500_GPIO_23 55
335 #define AU1500_GPIO_24 56
336 #define AU1500_GPIO_25 57
337 #define AU1500_GPIO_26 58
338 #define AU1500_GPIO_27 59
339 #define AU1500_GPIO_28 60
340 #define AU1500_GPIO_206 61
341 #define AU1500_GPIO_207 62
342 #define AU1500_GPIO_208_215 63
344 #define AU1X00_MAX_INTR 63
347 #define AU1100_GPIO_208_215 29
348 /* REDEFINE SECONDARY GPIO BLOCK INTO IC1 CONTROLLER HERE */
350 /* Programmable Counters 0 and 1 */
351 #define SYS_BASE 0xB1900000
352 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
353 #define SYS_CNTRL_E1S (1<<23)
354 #define SYS_CNTRL_T1S (1<<20)
355 #define SYS_CNTRL_M21 (1<<19)
356 #define SYS_CNTRL_M11 (1<<18)
357 #define SYS_CNTRL_M01 (1<<17)
358 #define SYS_CNTRL_C1S (1<<16)
359 #define SYS_CNTRL_BP (1<<14)
360 #define SYS_CNTRL_EN1 (1<<13)
361 #define SYS_CNTRL_BT1 (1<<12)
362 #define SYS_CNTRL_EN0 (1<<11)
363 #define SYS_CNTRL_BT0 (1<<10)
364 #define SYS_CNTRL_E0 (1<<8)
365 #define SYS_CNTRL_E0S (1<<7)
366 #define SYS_CNTRL_32S (1<<5)
367 #define SYS_CNTRL_T0S (1<<4)
368 #define SYS_CNTRL_M20 (1<<3)
369 #define SYS_CNTRL_M10 (1<<2)
370 #define SYS_CNTRL_M00 (1<<1)
371 #define SYS_CNTRL_C0S (1<<0)
373 /* Programmable Counter 0 Registers */
374 #define SYS_TOYTRIM (SYS_BASE + 0)
375 #define SYS_TOYWRITE (SYS_BASE + 4)
376 #define SYS_TOYMATCH0 (SYS_BASE + 8)
377 #define SYS_TOYMATCH1 (SYS_BASE + 0xC)
378 #define SYS_TOYMATCH2 (SYS_BASE + 0x10)
379 #define SYS_TOYREAD (SYS_BASE + 0x40)
381 /* Programmable Counter 1 Registers */
382 #define SYS_RTCTRIM (SYS_BASE + 0x44)
383 #define SYS_RTCWRITE (SYS_BASE + 0x48)
384 #define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
385 #define SYS_RTCMATCH1 (SYS_BASE + 0x50)
386 #define SYS_RTCMATCH2 (SYS_BASE + 0x54)
387 #define SYS_RTCREAD (SYS_BASE + 0x58)
390 #define I2S_DATA 0xB1000000
391 #define I2S_DATA_MASK (0xffffff)
392 #define I2S_CONFIG 0xB1000004
393 #define I2S_CONFIG_XU (1<<25)
394 #define I2S_CONFIG_XO (1<<24)
395 #define I2S_CONFIG_RU (1<<23)
396 #define I2S_CONFIG_RO (1<<22)
397 #define I2S_CONFIG_TR (1<<21)
398 #define I2S_CONFIG_TE (1<<20)
399 #define I2S_CONFIG_TF (1<<19)
400 #define I2S_CONFIG_RR (1<<18)
401 #define I2S_CONFIG_RE (1<<17)
402 #define I2S_CONFIG_RF (1<<16)
403 #define I2S_CONFIG_PD (1<<11)
404 #define I2S_CONFIG_LB (1<<10)
405 #define I2S_CONFIG_IC (1<<9)
406 #define I2S_CONFIG_FM_BIT 7
407 #define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
408 #define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
409 #define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
410 #define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
411 #define I2S_CONFIG_TN (1<<6)
412 #define I2S_CONFIG_RN (1<<5)
413 #define I2S_CONFIG_SZ_BIT 0
414 #define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
416 #define I2S_CONTROL 0xB1000008
417 #define I2S_CONTROL_D (1<<1)
418 #define I2S_CONTROL_CE (1<<0)
420 /* USB Host Controller */
421 /* We pass USB_OHCI_BASE to ioremap, so it needs to be a physical address */
422 #define USB_OHCI_BASE 0x10100000
423 #define USB_OHCI_LEN 0x00100000
424 #define USB_HOST_CONFIG 0xB017fffc
426 /* USB Device Controller */
427 #define USBD_EP0RD 0xB0200000
428 #define USBD_EP0WR 0xB0200004
429 #define USBD_EP2WR 0xB0200008
430 #define USBD_EP3WR 0xB020000C
431 #define USBD_EP4RD 0xB0200010
432 #define USBD_EP5RD 0xB0200014
433 #define USBD_INTEN 0xB0200018
434 #define USBD_INTSTAT 0xB020001C
435 #define USBDEV_INT_SOF (1<<12)
436 #define USBDEV_INT_HF_BIT 6
437 #define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
438 #define USBDEV_INT_CMPLT_BIT 0
439 #define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
440 #define USBD_CONFIG 0xB0200020
441 #define USBD_EP0CS 0xB0200024
442 #define USBD_EP2CS 0xB0200028
443 #define USBD_EP3CS 0xB020002C
444 #define USBD_EP4CS 0xB0200030
445 #define USBD_EP5CS 0xB0200034
446 #define USBDEV_CS_SU (1<<14)
447 #define USBDEV_CS_NAK (1<<13)
448 #define USBDEV_CS_ACK (1<<12)
449 #define USBDEV_CS_BUSY (1<<11)
450 #define USBDEV_CS_TSIZE_BIT 1
451 #define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
452 #define USBDEV_CS_STALL (1<<0)
453 #define USBD_EP0RDSTAT 0xB0200040
454 #define USBD_EP0WRSTAT 0xB0200044
455 #define USBD_EP2WRSTAT 0xB0200048
456 #define USBD_EP3WRSTAT 0xB020004C
457 #define USBD_EP4RDSTAT 0xB0200050
458 #define USBD_EP5RDSTAT 0xB0200054
459 #define USBDEV_FSTAT_FLUSH (1<<6)
460 #define USBDEV_FSTAT_UF (1<<5)
461 #define USBDEV_FSTAT_OF (1<<4)
462 #define USBDEV_FSTAT_FCNT_BIT 0
463 #define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
464 #define USBD_ENABLE 0xB0200058
465 #define USBDEV_ENABLE (1<<1)
466 #define USBDEV_CE (1<<0)
468 /* Ethernet Controllers */
469 #define AU1000_ETH0_BASE 0xB0500000
470 #define AU1000_ETH1_BASE 0xB0510000
471 #define AU1500_ETH0_BASE 0xB1500000
472 #define AU1500_ETH1_BASE 0xB1510000
473 #define AU1100_ETH0_BASE 0xB0500000
475 /* 4 byte offsets from AU1000_ETH_BASE */
476 #define MAC_CONTROL 0x0
477 #define MAC_RX_ENABLE (1<<2)
478 #define MAC_TX_ENABLE (1<<3)
479 #define MAC_DEF_CHECK (1<<5)
480 #define MAC_SET_BL(X) (((X)&0x3)<<6)
481 #define MAC_AUTO_PAD (1<<8)
482 #define MAC_DISABLE_RETRY (1<<10)
483 #define MAC_DISABLE_BCAST (1<<11)
484 #define MAC_LATE_COL (1<<12)
485 #define MAC_HASH_MODE (1<<13)
486 #define MAC_HASH_ONLY (1<<15)
487 #define MAC_PASS_ALL (1<<16)
488 #define MAC_INVERSE_FILTER (1<<17)
489 #define MAC_PROMISCUOUS (1<<18)
490 #define MAC_PASS_ALL_MULTI (1<<19)
491 #define MAC_FULL_DUPLEX (1<<20)
492 #define MAC_NORMAL_MODE 0
493 #define MAC_INT_LOOPBACK (1<<21)
494 #define MAC_EXT_LOOPBACK (1<<22)
495 #define MAC_DISABLE_RX_OWN (1<<23)
496 #define MAC_BIG_ENDIAN (1<<30)
497 #define MAC_RX_ALL (1<<31)
498 #define MAC_ADDRESS_HIGH 0x4
499 #define MAC_ADDRESS_LOW 0x8
500 #define MAC_MCAST_HIGH 0xC
501 #define MAC_MCAST_LOW 0x10
502 #define MAC_MII_CNTRL 0x14
503 #define MAC_MII_BUSY (1<<0)
504 #define MAC_MII_READ 0
505 #define MAC_MII_WRITE (1<<1)
506 #define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6)
507 #define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11)
508 #define MAC_MII_DATA 0x18
509 #define MAC_FLOW_CNTRL 0x1C
510 #define MAC_FLOW_CNTRL_BUSY (1<<0)
511 #define MAC_FLOW_CNTRL_ENABLE (1<<1)
512 #define MAC_PASS_CONTROL (1<<2)
513 #define MAC_SET_PAUSE(X) (((X)&0xffff)<<16)
514 #define MAC_VLAN1_TAG 0x20
515 #define MAC_VLAN2_TAG 0x24
517 /* Ethernet Controller Enable */
518 #define AU1000_MAC0_ENABLE 0xB0520000
519 #define AU1000_MAC1_ENABLE 0xB0520004
520 #define AU1500_MAC0_ENABLE 0xB1520000
521 #define AU1500_MAC1_ENABLE 0xB1520004
522 #define AU1100_MAC0_ENABLE 0xB0520000
524 #define MAC_EN_CLOCK_ENABLE (1<<0)
525 #define MAC_EN_RESET0 (1<<1)
526 #define MAC_EN_TOSS (0<<2)
527 #define MAC_EN_CACHEABLE (1<<3)
528 #define MAC_EN_RESET1 (1<<4)
529 #define MAC_EN_RESET2 (1<<5)
530 #define MAC_DMA_RESET (1<<6)
532 /* Ethernet Controller DMA Channels */
534 #define MAC0_TX_DMA_ADDR 0xB4004000
535 #define MAC1_TX_DMA_ADDR 0xB4004200
536 /* offsets from MAC_TX_RING_ADDR address */
537 #define MAC_TX_BUFF0_STATUS 0x0
538 #define TX_FRAME_ABORTED (1<<0)
539 #define TX_JAB_TIMEOUT (1<<1)
540 #define TX_NO_CARRIER (1<<2)
541 #define TX_LOSS_CARRIER (1<<3)
542 #define TX_EXC_DEF (1<<4)
543 #define TX_LATE_COLL_ABORT (1<<5)
544 #define TX_EXC_COLL (1<<6)
545 #define TX_UNDERRUN (1<<7)
546 #define TX_DEFERRED (1<<8)
547 #define TX_LATE_COLL (1<<9)
548 #define TX_COLL_CNT_MASK (0xF<<10)
549 #define TX_PKT_RETRY (1<<31)
550 #define MAC_TX_BUFF0_ADDR 0x4
551 #define TX_DMA_ENABLE (1<<0)
552 #define TX_T_DONE (1<<1)
553 #define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
554 #define MAC_TX_BUFF0_LEN 0x8
555 #define MAC_TX_BUFF1_STATUS 0x10
556 #define MAC_TX_BUFF1_ADDR 0x14
557 #define MAC_TX_BUFF1_LEN 0x18
558 #define MAC_TX_BUFF2_STATUS 0x20
559 #define MAC_TX_BUFF2_ADDR 0x24
560 #define MAC_TX_BUFF2_LEN 0x28
561 #define MAC_TX_BUFF3_STATUS 0x30
562 #define MAC_TX_BUFF3_ADDR 0x34
563 #define MAC_TX_BUFF3_LEN 0x38
565 #define MAC0_RX_DMA_ADDR 0xB4004100
566 #define MAC1_RX_DMA_ADDR 0xB4004300
567 /* offsets from MAC_RX_RING_ADDR */
568 #define MAC_RX_BUFF0_STATUS 0x0
569 #define RX_FRAME_LEN_MASK 0x3fff
570 #define RX_WDOG_TIMER (1<<14)
571 #define RX_RUNT (1<<15)
572 #define RX_OVERLEN (1<<16)
573 #define RX_COLL (1<<17)
574 #define RX_ETHER (1<<18)
575 #define RX_MII_ERROR (1<<19)
576 #define RX_DRIBBLING (1<<20)
577 #define RX_CRC_ERROR (1<<21)
578 #define RX_VLAN1 (1<<22)
579 #define RX_VLAN2 (1<<23)
580 #define RX_LEN_ERROR (1<<24)
581 #define RX_CNTRL_FRAME (1<<25)
582 #define RX_U_CNTRL_FRAME (1<<26)
583 #define RX_MCAST_FRAME (1<<27)
584 #define RX_BCAST_FRAME (1<<28)
585 #define RX_FILTER_FAIL (1<<29)
586 #define RX_PACKET_FILTER (1<<30)
587 #define RX_MISSED_FRAME (1<<31)
589 #define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
590 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
591 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
592 #define MAC_RX_BUFF0_ADDR 0x4
593 #define RX_DMA_ENABLE (1<<0)
594 #define RX_T_DONE (1<<1)
595 #define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
596 #define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0)
597 #define MAC_RX_BUFF1_STATUS 0x10
598 #define MAC_RX_BUFF1_ADDR 0x14
599 #define MAC_RX_BUFF2_STATUS 0x20
600 #define MAC_RX_BUFF2_ADDR 0x24
601 #define MAC_RX_BUFF3_STATUS 0x30
602 #define MAC_RX_BUFF3_ADDR 0x34
606 #define UART0_ADDR 0xB1100000
607 #define UART1_ADDR 0xB1200000
608 #define UART2_ADDR 0xB1300000
609 #define UART3_ADDR 0xB1400000
610 #define UART_BASE UART0_ADDR
611 #define UART_DEBUG_BASE UART2_ADDR
613 #define UART_RX 0 /* Receive buffer */
614 #define UART_TX 4 /* Transmit buffer */
615 #define UART_IER 8 /* Interrupt Enable Register */
616 #define UART_IIR 0xC /* Interrupt ID Register */
617 #define UART_FCR 0x10 /* FIFO Control Register */
618 #define UART_LCR 0x14 /* Line Control Register */
619 #define UART_MCR 0x18 /* Modem Control Register */
620 #define UART_LSR 0x1C /* Line Status Register */
621 #define UART_MSR 0x20 /* Modem Status Register */
622 #define UART_CLK 0x28 /* Baud Rate Clock Divider */
623 #define UART_ENABLE 0x100 /* Uart enable */
625 #define UART_EN_CE 1 /* Clock enable */
626 #define UART_EN_E 2 /* Enable */
628 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
629 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
630 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
631 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
632 #define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */
633 #define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */
634 #define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */
635 #define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */
636 #define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */
637 #define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */
638 #define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */
639 #define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */
640 #define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */
643 * These are the definitions for the Line Control Register
645 #define UART_LCR_SBC 0x40 /* Set break control */
646 #define UART_LCR_SPAR 0x20 /* Stick parity (?) */
647 #define UART_LCR_EPAR 0x10 /* Even parity select */
648 #define UART_LCR_PARITY 0x08 /* Parity Enable */
649 #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
650 #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
651 #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
652 #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
653 #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
656 * These are the definitions for the Line Status Register
658 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
659 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
660 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
661 #define UART_LSR_FE 0x08 /* Frame error indicator */
662 #define UART_LSR_PE 0x04 /* Parity error indicator */
663 #define UART_LSR_OE 0x02 /* Overrun error indicator */
664 #define UART_LSR_DR 0x01 /* Receiver data ready */
667 * These are the definitions for the Interrupt Identification Register
669 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
670 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
671 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
672 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
673 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
674 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
677 * These are the definitions for the Interrupt Enable Register
679 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
680 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
681 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
682 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
685 * These are the definitions for the Modem Control Register
687 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
688 #define UART_MCR_OUT2 0x08 /* Out2 complement */
689 #define UART_MCR_OUT1 0x04 /* Out1 complement */
690 #define UART_MCR_RTS 0x02 /* RTS complement */
691 #define UART_MCR_DTR 0x01 /* DTR complement */
694 * These are the definitions for the Modem Status Register
696 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
697 #define UART_MSR_RI 0x40 /* Ring Indicator */
698 #define UART_MSR_DSR 0x20 /* Data Set Ready */
699 #define UART_MSR_CTS 0x10 /* Clear to Send */
700 #define UART_MSR_DDCD 0x08 /* Delta DCD */
701 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
702 #define UART_MSR_DDSR 0x02 /* Delta DSR */
703 #define UART_MSR_DCTS 0x01 /* Delta CTS */
704 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
709 #define SSI0_STATUS 0xB1600000
710 #define SSI_STATUS_BF (1<<4)
711 #define SSI_STATUS_OF (1<<3)
712 #define SSI_STATUS_UF (1<<2)
713 #define SSI_STATUS_D (1<<1)
714 #define SSI_STATUS_B (1<<0)
715 #define SSI0_INT 0xB1600004
716 #define SSI_INT_OI (1<<3)
717 #define SSI_INT_UI (1<<2)
718 #define SSI_INT_DI (1<<1)
719 #define SSI0_INT_ENABLE 0xB1600008
720 #define SSI_INTE_OIE (1<<3)
721 #define SSI_INTE_UIE (1<<2)
722 #define SSI_INTE_DIE (1<<1)
723 #define SSI0_CONFIG 0xB1600020
724 #define SSI_CONFIG_AO (1<<24)
725 #define SSI_CONFIG_DO (1<<23)
726 #define SSI_CONFIG_ALEN_BIT 20
727 #define SSI_CONFIG_ALEN_MASK (0x7<<20)
728 #define SSI_CONFIG_DLEN_BIT 16
729 #define SSI_CONFIG_DLEN_MASK (0x7<<16)
730 #define SSI_CONFIG_DD (1<<11)
731 #define SSI_CONFIG_AD (1<<10)
732 #define SSI_CONFIG_BM_BIT 8
733 #define SSI_CONFIG_BM_MASK (0x3<<8)
734 #define SSI_CONFIG_CE (1<<7)
735 #define SSI_CONFIG_DP (1<<6)
736 #define SSI_CONFIG_DL (1<<5)
737 #define SSI_CONFIG_EP (1<<4)
738 #define SSI0_ADATA 0xB1600024
739 #define SSI_AD_D (1<<24)
740 #define SSI_AD_ADDR_BIT 16
741 #define SSI_AD_ADDR_MASK (0xff<<16)
742 #define SSI_AD_DATA_BIT 0
743 #define SSI_AD_DATA_MASK (0xfff<<0)
744 #define SSI0_CLKDIV 0xB1600028
745 #define SSI0_CONTROL 0xB1600100
746 #define SSI_CONTROL_CD (1<<1)
747 #define SSI_CONTROL_E (1<<0)
750 #define SSI1_STATUS 0xB1680000
751 #define SSI1_INT 0xB1680004
752 #define SSI1_INT_ENABLE 0xB1680008
753 #define SSI1_CONFIG 0xB1680020
754 #define SSI1_ADATA 0xB1680024
755 #define SSI1_CLKDIV 0xB1680028
756 #define SSI1_ENABLE 0xB1680100
759 * Register content definitions
761 #define SSI_STATUS_BF (1<<4)
762 #define SSI_STATUS_OF (1<<3)
763 #define SSI_STATUS_UF (1<<2)
764 #define SSI_STATUS_D (1<<1)
765 #define SSI_STATUS_B (1<<0)
768 #define SSI_INT_OI (1<<3)
769 #define SSI_INT_UI (1<<2)
770 #define SSI_INT_DI (1<<1)
773 #define SSI_INTEN_OIE (1<<3)
774 #define SSI_INTEN_UIE (1<<2)
775 #define SSI_INTEN_DIE (1<<1)
777 #define SSI_CONFIG_AO (1<<24)
778 #define SSI_CONFIG_DO (1<<23)
779 #define SSI_CONFIG_ALEN (7<<20)
780 #define SSI_CONFIG_DLEN (15<<16)
781 #define SSI_CONFIG_DD (1<<11)
782 #define SSI_CONFIG_AD (1<<10)
783 #define SSI_CONFIG_BM (3<<8)
784 #define SSI_CONFIG_CE (1<<7)
785 #define SSI_CONFIG_DP (1<<6)
786 #define SSI_CONFIG_DL (1<<5)
787 #define SSI_CONFIG_EP (1<<4)
788 #define SSI_CONFIG_ALEN_N(N) ((N-1)<<20)
789 #define SSI_CONFIG_DLEN_N(N) ((N-1)<<16)
790 #define SSI_CONFIG_BM_HI (0<<8)
791 #define SSI_CONFIG_BM_LO (1<<8)
792 #define SSI_CONFIG_BM_CY (2<<8)
794 #define SSI_ADATA_D (1<<24)
795 #define SSI_ADATA_ADDR (0xFF<<16)
796 #define SSI_ADATA_DATA (0x0FFF)
797 #define SSI_ADATA_ADDR_N(N) (N<<16)
799 #define SSI_ENABLE_CD (1<<1)
800 #define SSI_ENABLE_E (1<<0)
803 /* IrDA Controller */
804 #define IRDA_BASE 0xB0300000
805 #define IR_RING_PTR_STATUS (IRDA_BASE+0x00)
806 #define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04)
807 #define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08)
808 #define IR_RING_SIZE (IRDA_BASE+0x0C)
809 #define IR_RING_PROMPT (IRDA_BASE+0x10)
810 #define IR_RING_ADDR_CMPR (IRDA_BASE+0x14)
811 #define IR_INT_CLEAR (IRDA_BASE+0x18)
812 #define IR_CONFIG_1 (IRDA_BASE+0x20)
813 #define IR_RX_INVERT_LED (1<<0)
814 #define IR_TX_INVERT_LED (1<<1)
817 #define IR_SIR (1<<4)
818 #define IR_MIR (1<<5)
819 #define IR_FIR (1<<6)
820 #define IR_16CRC (1<<7)
822 #define IR_RX_ALL (1<<9)
823 #define IR_DMA_ENABLE (1<<10)
824 #define IR_RX_ENABLE (1<<11)
825 #define IR_TX_ENABLE (1<<12)
826 #define IR_LOOPBACK (1<<14)
827 #define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
828 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
829 #define IR_SIR_FLAGS (IRDA_BASE+0x24)
830 #define IR_ENABLE (IRDA_BASE+0x28)
831 #define IR_RX_STATUS (1<<9)
832 #define IR_TX_STATUS (1<<10)
833 #define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C)
834 #define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30)
835 #define IR_MAX_PKT_LEN (IRDA_BASE+0x34)
836 #define IR_RX_BYTE_CNT (IRDA_BASE+0x38)
837 #define IR_CONFIG_2 (IRDA_BASE+0x3C)
838 #define IR_MODE_INV (1<<0)
839 #define IR_ONE_PIN (1<<1)
840 #define IR_INTERFACE_CONFIG (IRDA_BASE+0x40)
843 #define SYS_PINFUNC 0xB190002C
844 #define SYS_PF_USB (1<<15) /* 2nd USB device/host */
845 #define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */
846 #define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */
847 #define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */
848 #define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */
849 #define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */
850 #define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */
851 #define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */
852 #define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */
853 #define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */
854 #define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */
855 #define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */
856 #define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */
857 #define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */
858 #define SYS_PF_A97 (1<<1) /* AC97/SSL1 */
859 #define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */
860 #define SYS_TRIOUTRD 0xB1900100
861 #define SYS_TRIOUTCLR 0xB1900100
862 #define SYS_OUTPUTRD 0xB1900108
863 #define SYS_OUTPUTSET 0xB1900108
864 #define SYS_OUTPUTCLR 0xB190010C
865 #define SYS_PINSTATERD 0xB1900110
866 #define SYS_PININPUTEN 0xB1900110
868 /* GPIO2, Au1500 only */
869 #define GPIO2_BASE 0xB1700000
870 #define GPIO2_DIR (GPIO2_BASE + 0)
871 #define GPIO2_DATA_EN (GPIO2_BASE + 8)
872 #define GPIO2_PIN_STATE (GPIO2_BASE + 0xC)
873 #define GPIO2_INT_ENABLE (GPIO2_BASE + 0x10)
874 #define GPIO2_ENABLE (GPIO2_BASE + 0x14)
876 /* Power Management */
877 #define SYS_SCRATCH0 0xB1900018
878 #define SYS_SCRATCH1 0xB190001C
879 #define SYS_WAKEMSK 0xB1900034
880 #define SYS_ENDIAN 0xB1900038
881 #define SYS_POWERCTRL 0xB190003C
882 #define SYS_WAKESRC 0xB190005C
883 #define SYS_SLPPWR 0xB1900078
884 #define SYS_SLEEP 0xB190007C
886 /* Clock Controller */
887 #define SYS_FREQCTRL0 0xB1900020
888 #define SYS_FC_FRDIV2_BIT 22
889 #define SYS_FC_FRDIV2_MASK (0xff << FQC2_FRDIV2_BIT)
890 #define SYS_FC_FE2 (1<<21)
891 #define SYS_FC_FS2 (1<<20)
892 #define SYS_FC_FRDIV1_BIT 12
893 #define SYS_FC_FRDIV1_MASK (0xff << FQC2_FRDIV1_BIT)
894 #define SYS_FC_FE1 (1<<11)
895 #define SYS_FC_FS1 (1<<10)
896 #define SYS_FC_FRDIV0_BIT 2
897 #define SYS_FC_FRDIV0_MASK (0xff << FQC2_FRDIV0_BIT)
898 #define SYS_FC_FE0 (1<<1)
899 #define SYS_FC_FS0 (1<<0)
900 #define SYS_FREQCTRL1 0xB1900024
901 #define SYS_FC_FRDIV5_BIT 22
902 #define SYS_FC_FRDIV5_MASK (0xff << FQC2_FRDIV5_BIT)
903 #define SYS_FC_FE5 (1<<21)
904 #define SYS_FC_FS5 (1<<20)
905 #define SYS_FC_FRDIV4_BIT 12
906 #define SYS_FC_FRDIV4_MASK (0xff << FQC2_FRDIV4_BIT)
907 #define SYS_FC_FE4 (1<<11)
908 #define SYS_FC_FS4 (1<<10)
909 #define SYS_FC_FRDIV3_BIT 2
910 #define SYS_FC_FRDIV3_MASK (0xff << FQC2_FRDIV3_BIT)
911 #define SYS_FC_FE3 (1<<1)
912 #define SYS_FC_FS3 (1<<0)
913 #define SYS_CLKSRC 0xB1900028
914 #define SYS_CS_ME1_BIT 27
915 #define SYS_CS_ME1_MASK (0x7<<CSC_ME1_BIT)
916 #define SYS_CS_DE1 (1<<26)
917 #define SYS_CS_CE1 (1<<25)
918 #define SYS_CS_ME0_BIT 22
919 #define SYS_CS_ME0_MASK (0x7<<CSC_ME0_BIT)
920 #define SYS_CS_DE0 (1<<21)
921 #define SYS_CS_CE0 (1<<20)
922 #define SYS_CS_MI2_BIT 17
923 #define SYS_CS_MI2_MASK (0x7<<CSC_MI2_BIT)
924 #define SYS_CS_DI2 (1<<16)
925 #define SYS_CS_CI2 (1<<15)
926 #define SYS_CS_MUH_BIT 12
927 #define SYS_CS_MUH_MASK (0x7<<CSC_MUH_BIT)
928 #define SYS_CS_DUH (1<<11)
929 #define SYS_CS_CUH (1<<10)
930 #define SYS_CS_MUD_BIT 7
931 #define SYS_CS_MUD_MASK (0x7<<CSC_MUD_BIT)
932 #define SYS_CS_DUD (1<<6)
933 #define SYS_CS_CUD (1<<5)
934 #define SYS_CS_MIR_BIT 2
935 #define SYS_CS_MIR_MASK (0x7<<CSC_MIR_BIT)
936 #define SYS_CS_DIR (1<<1)
937 #define SYS_CS_CIR (1<<0)
939 #define SYS_CS_MUX_AUX 0x1
940 #define SYS_CS_MUX_FQ0 0x2
941 #define SYS_CS_MUX_FQ1 0x3
942 #define SYS_CS_MUX_FQ2 0x4
943 #define SYS_CS_MUX_FQ3 0x5
944 #define SYS_CS_MUX_FQ4 0x6
945 #define SYS_CS_MUX_FQ5 0x7
946 #define SYS_CPUPLL 0xB1900060
947 #define SYS_AUXPLL 0xB1900064
949 /* AC97 Controller */
950 #define AC97C_CONFIG 0xB0000000
951 #define AC97C_RECV_SLOTS_BIT 13
952 #define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
953 #define AC97C_XMIT_SLOTS_BIT 3
954 #define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
955 #define AC97C_SG (1<<2)
956 #define AC97C_SYNC (1<<1)
957 #define AC97C_RESET (1<<0)
958 #define AC97C_STATUS 0xB0000004
959 #define AC97C_XU (1<<11)
960 #define AC97C_XO (1<<10)
961 #define AC97C_RU (1<<9)
962 #define AC97C_RO (1<<8)
963 #define AC97C_READY (1<<7)
964 #define AC97C_CP (1<<6)
965 #define AC97C_TR (1<<5)
966 #define AC97C_TE (1<<4)
967 #define AC97C_TF (1<<3)
968 #define AC97C_RR (1<<2)
969 #define AC97C_RE (1<<1)
970 #define AC97C_RF (1<<0)
971 #define AC97C_DATA 0xB0000008
972 #define AC97C_CMD 0xB000000C
973 #define AC97C_WD_BIT 16
974 #define AC97C_READ (1<<7)
975 #define AC97C_INDEX_MASK 0x7f
976 #define AC97C_CNTRL 0xB0000010
977 #define AC97C_RS (1<<1)
978 #define AC97C_CE (1<<0)
980 #ifdef CONFIG_SOC_AU1500
981 /* Au1500 PCI Controller */
982 #define Au1500_CFG_BASE 0xB4005000 /* virtual, kseg0 addr */
983 #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
984 #define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
985 #define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27))
986 #define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
987 #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
988 #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
989 #define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
990 #define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
991 #define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
992 #define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
993 #define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
994 #define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
995 #define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
996 #define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
997 #define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
999 #define Au1500_PCI_HDR 0xB4005100 /* virtual, kseg0 addr */
1001 /* All of our structures, like pci resource, have 32 bit members.
1002 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
1003 * hard to store 0x4 0000 0000 in a 32 bit type. We require a small patch
1004 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
1005 * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM
1006 * addresses. For PCI IO, it's simpler because we get to do the ioremap
1007 * ourselves and then adjust the device's resources.
1009 #define Au1500_EXT_CFG 0x600000000
1010 #define Au1500_EXT_CFG_TYPE1 0x680000000
1011 #define Au1500_PCI_IO_START 0x500000000
1012 #define Au1500_PCI_IO_END 0x5000FFFFF
1013 #define Au1500_PCI_MEM_START 0x440000000
1014 #define Au1500_PCI_MEM_END 0x443FFFFFF
1016 #define PCI_IO_START (Au1500_PCI_IO_START + 0x300)
1017 #define PCI_IO_END (Au1500_PCI_IO_END)
1018 #define PCI_MEM_START (Au1500_PCI_MEM_START)
1019 #define PCI_MEM_END (Au1500_PCI_MEM_END)
1020 #define PCI_FIRST_DEVFN (0<<3)
1021 #define PCI_LAST_DEVFN (19<<3)
1025 #if defined(CONFIG_SOC_AU1100) || (defined(CONFIG_SOC_AU1000) && !defined(CONFIG_MIPS_PB1000))
1026 /* no PCI bus controller */
1027 #define PCI_IO_START 0
1028 #define PCI_IO_END 0
1029 #define PCI_MEM_START 0
1030 #define PCI_MEM_END 0
1031 #define PCI_FIRST_DEVFN 0
1032 #define PCI_LAST_DEVFN 0
1034 #define AU1X_SOCK0_IO 0xF00000000
1035 #define AU1X_SOCK0_PHYS_ATTR 0xF40000000
1036 #define AU1X_SOCK0_PHYS_MEM 0xF80000000
1038 /* pcmcia socket 1 needs external glue logic so the memory map
1039 * differs from board to board.
1042 /* Only for db board, not older pb */
1043 #define AU1X_SOCK1_IO 0xF04000000
1044 #define AU1X_SOCK1_PHYS_ATTR 0xF44000000
1045 #define AU1X_SOCK1_PHYS_MEM 0xF84000000