2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
11 * Copyright (C) 2003 Maciej W. Rozycki
13 #ifndef _ASM_MIPSREGS_H
14 #define _ASM_MIPSREGS_H
17 #include <linux/linkage.h>
21 * The following macros are especially useful for __asm__
28 #define STR(x) __STR(x)
32 * Coprocessor 0 register names
36 #define CP0_ENTRYLO0 $2
37 #define CP0_ENTRYLO1 $3
39 #define CP0_CONTEXT $4
40 #define CP0_PAGEMASK $5
43 #define CP0_BADVADDR $8
45 #define CP0_ENTRYHI $10
46 #define CP0_COMPARE $11
47 #define CP0_STATUS $12
51 #define CP0_CONFIG $16
52 #define CP0_LLADDR $17
53 #define CP0_WATCHLO $18
54 #define CP0_WATCHHI $19
55 #define CP0_XCONTEXT $20
56 #define CP0_FRAMEMASK $21
57 #define CP0_DIAGNOSTIC $22
58 #define CP0_PERFORMANCE $25
60 #define CP0_CACHEERR $27
63 #define CP0_ERROREPC $30
66 * R4640/R4650 cp0 register names. These registers are listed
67 * here only for completeness; without MMU these CPUs are not useable
68 * by Linux. A future ELKS port might take make Linux run on them
76 #define CP0_IWATCH $18
77 #define CP0_DWATCH $19
80 * Coprocessor 0 Set 1 register names
82 #define CP0_S1_DERRADDR0 $26
83 #define CP0_S1_DERRADDR1 $27
84 #define CP0_S1_INTCONTROL $20
86 * Coprocessor 1 (FPU) register names
88 #define CP1_REVISION $0
89 #define CP1_STATUS $31
92 * FPU Status Register Values
95 * Status Register Values
98 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
99 #define FPU_CSR_COND 0x00800000 /* $fcc0 */
100 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */
101 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */
102 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */
103 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */
104 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */
105 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */
106 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */
107 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */
110 * X the exception cause indicator
111 * E the exception enable
112 * S the sticky/flag bit
114 #define FPU_CSR_ALL_X 0x0003f000
115 #define FPU_CSR_UNI_X 0x00020000
116 #define FPU_CSR_INV_X 0x00010000
117 #define FPU_CSR_DIV_X 0x00008000
118 #define FPU_CSR_OVF_X 0x00004000
119 #define FPU_CSR_UDF_X 0x00002000
120 #define FPU_CSR_INE_X 0x00001000
122 #define FPU_CSR_ALL_E 0x00000f80
123 #define FPU_CSR_INV_E 0x00000800
124 #define FPU_CSR_DIV_E 0x00000400
125 #define FPU_CSR_OVF_E 0x00000200
126 #define FPU_CSR_UDF_E 0x00000100
127 #define FPU_CSR_INE_E 0x00000080
129 #define FPU_CSR_ALL_S 0x0000007c
130 #define FPU_CSR_INV_S 0x00000040
131 #define FPU_CSR_DIV_S 0x00000020
132 #define FPU_CSR_OVF_S 0x00000010
133 #define FPU_CSR_UDF_S 0x00000008
134 #define FPU_CSR_INE_S 0x00000004
137 #define FPU_CSR_RN 0x0 /* nearest */
138 #define FPU_CSR_RZ 0x1 /* towards zero */
139 #define FPU_CSR_RU 0x2 /* towards +Infinity */
140 #define FPU_CSR_RD 0x3 /* towards -Infinity */
144 * Values for PageMask register
146 #include <linux/config.h>
147 #ifdef CONFIG_CPU_VR41XX
148 #define PM_1K 0x00000000
149 #define PM_4K 0x00001800
150 #define PM_16K 0x00007800
151 #define PM_64K 0x0001f800
152 #define PM_256K 0x0007f800
154 #define PM_4K 0x00000000
155 #define PM_16K 0x00006000
156 #define PM_64K 0x0001e000
157 #define PM_256K 0x0007e000
158 #define PM_1M 0x001fe000
159 #define PM_4M 0x007fe000
160 #define PM_16M 0x01ffe000
164 * Values used for computation of new tlb entries
175 * Macros to access the system control coprocessor
177 #define read_32bit_cp0_register(source) \
179 __asm__ __volatile__( \
181 ".set\treorder\n\t" \
182 "mfc0\t%0,"STR(source)"\n\t" \
187 #define read_32bit_cp0_set1_register(source) \
189 __asm__ __volatile__( \
191 ".set\treorder\n\t" \
192 "cfc0\t%0,"STR(source)"\n\t" \
198 * For now use this only with interrupts disabled!
200 #define read_64bit_cp0_register(source) \
202 __asm__ __volatile__( \
204 "dmfc0\t%0,"STR(source)"\n\t" \
209 #define write_32bit_cp0_register(register,value) \
210 __asm__ __volatile__( \
211 "mtc0\t%0,"STR(register)"\n\t" \
215 #define write_32bit_cp0_set1_register(register,value) \
216 __asm__ __volatile__( \
217 "ctc0\t%0,"STR(register)"\n\t" \
221 #define write_64bit_cp0_register(register,value) \
222 __asm__ __volatile__( \
224 "dmtc0\t%0,"STR(register)"\n\t" \
229 * This should be changed when we get a compiler that support the MIPS32 ISA.
231 #define read_mips32_cp0_config1() \
233 __asm__ __volatile__( \
234 ".set\tnoreorder\n\t" \
236 ".word\t0x40018001\n\t" \
243 #define tlb_write_indexed() \
244 __asm__ __volatile__( \
245 ".set noreorder\n\t" \
250 * R4x00 interrupt enable / cause bits
252 #define IE_SW0 (1<< 8)
253 #define IE_SW1 (1<< 9)
254 #define IE_IRQ0 (1<<10)
255 #define IE_IRQ1 (1<<11)
256 #define IE_IRQ2 (1<<12)
257 #define IE_IRQ3 (1<<13)
258 #define IE_IRQ4 (1<<14)
259 #define IE_IRQ5 (1<<15)
262 * R4x00 interrupt cause bits
264 #define C_SW0 (1<< 8)
265 #define C_SW1 (1<< 9)
266 #define C_IRQ0 (1<<10)
267 #define C_IRQ1 (1<<11)
268 #define C_IRQ2 (1<<12)
269 #define C_IRQ3 (1<<13)
270 #define C_IRQ4 (1<<14)
271 #define C_IRQ5 (1<<15)
273 #ifndef _LANGUAGE_ASSEMBLY
275 * Manipulate the status register.
276 * Mostly used to access the interrupt bits.
278 #define __BUILD_SET_CP0(name,register) \
279 extern __inline__ unsigned int \
280 set_cp0_##name(unsigned int set) \
284 res = read_32bit_cp0_register(register); \
286 write_32bit_cp0_register(register, res); \
291 extern __inline__ unsigned int \
292 clear_cp0_##name(unsigned int clear) \
296 res = read_32bit_cp0_register(register); \
298 write_32bit_cp0_register(register, res); \
303 extern __inline__ unsigned int \
304 change_cp0_##name(unsigned int change, unsigned int new) \
308 res = read_32bit_cp0_register(register); \
310 res |= (new & change); \
312 write_32bit_cp0_register(register, res); \
317 __BUILD_SET_CP0(status,CP0_STATUS)
318 __BUILD_SET_CP0(cause,CP0_CAUSE)
319 __BUILD_SET_CP0(config,CP0_CONFIG)
321 #endif /* defined (_LANGUAGE_ASSEMBLY) */
324 * Bitfields in the R4xx0 cp0 status register
326 #define ST0_IE 0x00000001
327 #define ST0_EXL 0x00000002
328 #define ST0_ERL 0x00000004
329 #define ST0_KSU 0x00000018
330 # define KSU_USER 0x00000010
331 # define KSU_SUPERVISOR 0x00000008
332 # define KSU_KERNEL 0x00000000
333 #define ST0_UX 0x00000020
334 #define ST0_SX 0x00000040
335 #define ST0_KX 0x00000080
336 #define ST0_DE 0x00010000
337 #define ST0_CE 0x00020000
340 * Bitfields in the R[23]000 cp0 status register.
342 #define ST0_IEC 0x00000001
343 #define ST0_KUC 0x00000002
344 #define ST0_IEP 0x00000004
345 #define ST0_KUP 0x00000008
346 #define ST0_IEO 0x00000010
347 #define ST0_KUO 0x00000020
348 /* bits 6 & 7 are reserved on R[23]000 */
349 #define ST0_ISC 0x00010000
350 #define ST0_SWC 0x00020000
351 #define ST0_CM 0x00080000
354 * Bits specific to the R4640/R4650
356 #define ST0_UM (1 << 4)
357 #define ST0_IL (1 << 23)
358 #define ST0_DL (1 << 24)
361 * Bitfields in the TX39 family CP0 Configuration Register 3
363 #define TX39_CONF_ICS_SHIFT 19
364 #define TX39_CONF_ICS_MASK 0x00380000
365 #define TX39_CONF_ICS_1KB 0x00000000
366 #define TX39_CONF_ICS_2KB 0x00080000
367 #define TX39_CONF_ICS_4KB 0x00100000
368 #define TX39_CONF_ICS_8KB 0x00180000
369 #define TX39_CONF_ICS_16KB 0x00200000
371 #define TX39_CONF_DCS_SHIFT 16
372 #define TX39_CONF_DCS_MASK 0x00070000
373 #define TX39_CONF_DCS_1KB 0x00000000
374 #define TX39_CONF_DCS_2KB 0x00010000
375 #define TX39_CONF_DCS_4KB 0x00020000
376 #define TX39_CONF_DCS_8KB 0x00030000
377 #define TX39_CONF_DCS_16KB 0x00040000
379 #define TX39_CONF_CWFON 0x00004000
380 #define TX39_CONF_WBON 0x00002000
381 #define TX39_CONF_RF_SHIFT 10
382 #define TX39_CONF_RF_MASK 0x00000c00
383 #define TX39_CONF_DOZE 0x00000200
384 #define TX39_CONF_HALT 0x00000100
385 #define TX39_CONF_LOCK 0x00000080
386 #define TX39_CONF_ICE 0x00000020
387 #define TX39_CONF_DCE 0x00000010
388 #define TX39_CONF_IRSIZE_SHIFT 2
389 #define TX39_CONF_IRSIZE_MASK 0x0000000c
390 #define TX39_CONF_DRSIZE_SHIFT 0
391 #define TX39_CONF_DRSIZE_MASK 0x00000003
394 * Status register bits available in all MIPS CPUs.
396 #define ST0_IM 0x0000ff00
397 #define STATUSB_IP0 8
398 #define STATUSF_IP0 (1 << 8)
399 #define STATUSB_IP1 9
400 #define STATUSF_IP1 (1 << 9)
401 #define STATUSB_IP2 10
402 #define STATUSF_IP2 (1 << 10)
403 #define STATUSB_IP3 11
404 #define STATUSF_IP3 (1 << 11)
405 #define STATUSB_IP4 12
406 #define STATUSF_IP4 (1 << 12)
407 #define STATUSB_IP5 13
408 #define STATUSF_IP5 (1 << 13)
409 #define STATUSB_IP6 14
410 #define STATUSF_IP6 (1 << 14)
411 #define STATUSB_IP7 15
412 #define STATUSF_IP7 (1 << 15)
413 #define STATUSB_IP8 0
414 #define STATUSF_IP8 (1 << 0)
415 #define STATUSB_IP9 1
416 #define STATUSF_IP9 (1 << 1)
417 #define STATUSB_IP10 2
418 #define STATUSF_IP10 (1 << 2)
419 #define STATUSB_IP11 3
420 #define STATUSF_IP11 (1 << 3)
421 #define STATUSB_IP12 4
422 #define STATUSF_IP12 (1 << 4)
423 #define STATUSB_IP13 5
424 #define STATUSF_IP13 (1 << 5)
425 #define STATUSB_IP14 6
426 #define STATUSF_IP14 (1 << 6)
427 #define STATUSB_IP15 7
428 #define STATUSF_IP15 (1 << 7)
429 #define ST0_CH 0x00040000
430 #define ST0_SR 0x00100000
431 #define ST0_BEV 0x00400000
432 #define ST0_RE 0x02000000
433 #define ST0_FR 0x04000000
434 #define ST0_CU 0xf0000000
435 #define ST0_CU0 0x10000000
436 #define ST0_CU1 0x20000000
437 #define ST0_CU2 0x40000000
438 #define ST0_CU3 0x80000000
439 #define ST0_XX 0x80000000 /* MIPS IV naming */
442 * Bitfields and bit numbers in the coprocessor 0 cause register.
444 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
446 #define CAUSEB_EXCCODE 2
447 #define CAUSEF_EXCCODE (31 << 2)
449 #define CAUSEF_IP (255 << 8)
451 #define CAUSEF_IP0 (1 << 8)
453 #define CAUSEF_IP1 (1 << 9)
454 #define CAUSEB_IP2 10
455 #define CAUSEF_IP2 (1 << 10)
456 #define CAUSEB_IP3 11
457 #define CAUSEF_IP3 (1 << 11)
458 #define CAUSEB_IP4 12
459 #define CAUSEF_IP4 (1 << 12)
460 #define CAUSEB_IP5 13
461 #define CAUSEF_IP5 (1 << 13)
462 #define CAUSEB_IP6 14
463 #define CAUSEF_IP6 (1 << 14)
464 #define CAUSEB_IP7 15
465 #define CAUSEF_IP7 (1 << 15)
467 #define CAUSEF_IV (1 << 23)
469 #define CAUSEF_CE (3 << 28)
471 #define CAUSEF_BD (1 << 31)
474 * Bits in the coprozessor 0 config register.
476 #define CONF_CM_CACHABLE_NO_WA 0
477 #define CONF_CM_CACHABLE_WA 1
478 #define CONF_CM_UNCACHED 2
479 #define CONF_CM_CACHABLE_NONCOHERENT 3
480 #define CONF_CM_CACHABLE_CE 4
481 #define CONF_CM_CACHABLE_COW 5
482 #define CONF_CM_CACHABLE_CUW 6
483 #define CONF_CM_CACHABLE_ACCELERATED 7
484 #define CONF_CM_CMASK 7
485 #define CONF_DB (1 << 4)
486 #define CONF_IB (1 << 5)
487 #define CONF_SC (1 << 17)
488 #define CONF_AC (1 << 23)
489 #define CONF_HALT (1 << 25)
492 * R10000 performance counter definitions.
494 * FIXME: The R10000 performance counter opens a nice way to implement CPU
495 * time accounting with a precission of one cycle. I don't have
496 * R10000 silicon but just a manual, so ...
500 * Events counted by counter #0
503 #define CE0_INSN_ISSUED 1
504 #define CE0_LPSC_ISSUED 2
505 #define CE0_S_ISSUED 3
506 #define CE0_SC_ISSUED 4
507 #define CE0_SC_FAILED 5
508 #define CE0_BRANCH_DECODED 6
509 #define CE0_QW_WB_SECONDARY 7
510 #define CE0_CORRECTED_ECC_ERRORS 8
511 #define CE0_ICACHE_MISSES 9
512 #define CE0_SCACHE_I_MISSES 10
513 #define CE0_SCACHE_I_WAY_MISSPREDICTED 11
514 #define CE0_EXT_INTERVENTIONS_REQ 12
515 #define CE0_EXT_INVALIDATE_REQ 13
516 #define CE0_VIRTUAL_COHERENCY_COND 14
517 #define CE0_INSN_GRADUATED 15
520 * Events counted by counter #1
523 #define CE1_INSN_GRADUATED 1
524 #define CE1_LPSC_GRADUATED 2
525 #define CE1_S_GRADUATED 3
526 #define CE1_SC_GRADUATED 4
527 #define CE1_FP_INSN_GRADUATED 5
528 #define CE1_QW_WB_PRIMARY 6
529 #define CE1_TLB_REFILL 7
530 #define CE1_BRANCH_MISSPREDICTED 8
531 #define CE1_DCACHE_MISS 9
532 #define CE1_SCACHE_D_MISSES 10
533 #define CE1_SCACHE_D_WAY_MISSPREDICTED 11
534 #define CE1_EXT_INTERVENTION_HITS 12
535 #define CE1_EXT_INVALIDATE_REQ 13
536 #define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
537 #define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
540 * These flags define in which priviledge mode the counters count events
542 #define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
543 #define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
544 #define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
545 #define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
547 #endif /* _ASM_MIPSREGS_H */