git.sur5r.net Git - u-boot/blob - include/asm-mips/mipsregs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2000 Silicon Graphics, Inc.
   8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
  12  */
  13 #ifndef _ASM_MIPSREGS_H
  14 #define _ASM_MIPSREGS_H
  15
  16 #if 0
  17 #include <linux/linkage.h>
  18 #endif
  19
  20 /*
  21  * The following macros are especially useful for __asm__
  22  * inline assembler.
  23  */
  24 #ifndef __STR
  25 #define __STR(x) #x
  26 #endif
  27 #ifndef STR
  28 #define STR(x) __STR(x)
  29 #endif
  30
  31 /*
  32  *  Configure language
  33  */
  34 #ifdef __ASSEMBLY__
  35 #define _ULCAST_
  36 #else
  37 #define _ULCAST_ (unsigned long)
  38 #endif
  39
  40 /*
  41  * Coprocessor 0 register names
  42  */
  43 #define CP0_INDEX $0
  44 #define CP0_RANDOM $1
  45 #define CP0_ENTRYLO0 $2
  46 #define CP0_ENTRYLO1 $3
  47 #define CP0_CONF $3
  48 #define CP0_CONTEXT $4
  49 #define CP0_PAGEMASK $5
  50 #define CP0_WIRED $6
  51 #define CP0_INFO $7
  52 #define CP0_BADVADDR $8
  53 #define CP0_COUNT $9
  54 #define CP0_ENTRYHI $10
  55 #define CP0_COMPARE $11
  56 #define CP0_STATUS $12
  57 #define CP0_CAUSE $13
  58 #define CP0_EPC $14
  59 #define CP0_PRID $15
  60 #define CP0_CONFIG $16
  61 #define CP0_LLADDR $17
  62 #define CP0_WATCHLO $18
  63 #define CP0_WATCHHI $19
  64 #define CP0_XCONTEXT $20
  65 #define CP0_FRAMEMASK $21
  66 #define CP0_DIAGNOSTIC $22
  67 #define CP0_DEBUG $23
  68 #define CP0_DEPC $24
  69 #define CP0_PERFORMANCE $25
  70 #define CP0_ECC $26
  71 #define CP0_CACHEERR $27
  72 #define CP0_TAGLO $28
  73 #define CP0_TAGHI $29
  74 #define CP0_ERROREPC $30
  75 #define CP0_DESAVE $31
  76
  77 /*
  78  * R4640/R4650 cp0 register names.  These registers are listed
  79  * here only for completeness; without MMU these CPUs are not useable
  80  * by Linux.  A future ELKS port might take make Linux run on them
  81  * though ...
  82  */
  83 #define CP0_IBASE $0
  84 #define CP0_IBOUND $1
  85 #define CP0_DBASE $2
  86 #define CP0_DBOUND $3
  87 #define CP0_CALG $17
  88 #define CP0_IWATCH $18
  89 #define CP0_DWATCH $19
  90
  91 /*
  92  * Coprocessor 0 Set 1 register names
  93  */
  94 #define CP0_S1_DERRADDR0  $26
  95 #define CP0_S1_DERRADDR1  $27
  96 #define CP0_S1_INTCONTROL $20
  97
  98 /*
  99  * Coprocessor 0 Set 2 register names
 100  */
 101 #define CP0_S2_SRSCTL   $12     /* MIPSR2 */
 102
 103 /*
 104  * Coprocessor 0 Set 3 register names
 105  */
 106 #define CP0_S3_SRSMAP   $12     /* MIPSR2 */
 107
 108 /*
 109  *  TX39 Series
 110  */
 111 #define CP0_TX39_CACHE  $7
 112
 113 /*
 114  * Coprocessor 1 (FPU) register names
 115  */
 116 #define CP1_REVISION    $0
 117 #define CP1_STATUS      $31
 118
 119 /*
 120  * FPU Status Register Values
 121  */
 122 /*
 123  * Status Register Values
 124  */
 125
 126 #define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
 127 #define FPU_CSR_COND    0x00800000      /* $fcc0 */
 128 #define FPU_CSR_COND0   0x00800000      /* $fcc0 */
 129 #define FPU_CSR_COND1   0x02000000      /* $fcc1 */
 130 #define FPU_CSR_COND2   0x04000000      /* $fcc2 */
 131 #define FPU_CSR_COND3   0x08000000      /* $fcc3 */
 132 #define FPU_CSR_COND4   0x10000000      /* $fcc4 */
 133 #define FPU_CSR_COND5   0x20000000      /* $fcc5 */
 134 #define FPU_CSR_COND6   0x40000000      /* $fcc6 */
 135 #define FPU_CSR_COND7   0x80000000      /* $fcc7 */
 136
 137 /*
 138  * X the exception cause indicator
 139  * E the exception enable
 140  * S the sticky/flag bit
 141  */
 142 #define FPU_CSR_ALL_X   0x0003f000
 143 #define FPU_CSR_UNI_X   0x00020000
 144 #define FPU_CSR_INV_X   0x00010000
 145 #define FPU_CSR_DIV_X   0x00008000
 146 #define FPU_CSR_OVF_X   0x00004000
 147 #define FPU_CSR_UDF_X   0x00002000
 148 #define FPU_CSR_INE_X   0x00001000
 149
 150 #define FPU_CSR_ALL_E   0x00000f80
 151 #define FPU_CSR_INV_E   0x00000800
 152 #define FPU_CSR_DIV_E   0x00000400
 153 #define FPU_CSR_OVF_E   0x00000200
 154 #define FPU_CSR_UDF_E   0x00000100
 155 #define FPU_CSR_INE_E   0x00000080
 156
 157 #define FPU_CSR_ALL_S   0x0000007c
 158 #define FPU_CSR_INV_S   0x00000040
 159 #define FPU_CSR_DIV_S   0x00000020
 160 #define FPU_CSR_OVF_S   0x00000010
 161 #define FPU_CSR_UDF_S   0x00000008
 162 #define FPU_CSR_INE_S   0x00000004
 163
 164 /* rounding mode */
 165 #define FPU_CSR_RN      0x0     /* nearest */
 166 #define FPU_CSR_RZ      0x1     /* towards zero */
 167 #define FPU_CSR_RU      0x2     /* towards +Infinity */
 168 #define FPU_CSR_RD      0x3     /* towards -Infinity */
 169
 170 /*
 171  * Values for PageMask register
 172  */
 173 #ifdef CONFIG_CPU_VR41XX
 174
 175 /* Why doesn't stupidity hurt ... */
 176
 177 #define PM_1K           0x00000000
 178 #define PM_4K           0x00001800
 179 #define PM_16K          0x00007800
 180 #define PM_64K          0x0001f800
 181 #define PM_256K         0x0007f800
 182
 183 #else
 184
 185 #define PM_4K           0x00000000
 186 #define PM_16K          0x00006000
 187 #define PM_64K          0x0001e000
 188 #define PM_256K         0x0007e000
 189 #define PM_1M           0x001fe000
 190 #define PM_4M           0x007fe000
 191 #define PM_16M          0x01ffe000
 192 #define PM_64M          0x07ffe000
 193 #define PM_256M         0x1fffe000
 194
 195 #endif
 196
 197 /*
 198  * Values used for computation of new tlb entries
 199  */
 200 #define PL_4K           12
 201 #define PL_16K          14
 202 #define PL_64K          16
 203 #define PL_256K         18
 204 #define PL_1M           20
 205 #define PL_4M           22
 206 #define PL_16M          24
 207 #define PL_64M          26
 208 #define PL_256M         28
 209
 210 /*
 211  * R4x00 interrupt enable / cause bits
 212  */
 213 #define IE_SW0          (_ULCAST_(1) <<  8)
 214 #define IE_SW1          (_ULCAST_(1) <<  9)
 215 #define IE_IRQ0         (_ULCAST_(1) << 10)
 216 #define IE_IRQ1         (_ULCAST_(1) << 11)
 217 #define IE_IRQ2         (_ULCAST_(1) << 12)
 218 #define IE_IRQ3         (_ULCAST_(1) << 13)
 219 #define IE_IRQ4         (_ULCAST_(1) << 14)
 220 #define IE_IRQ5         (_ULCAST_(1) << 15)
 221
 222 /*
 223  * R4x00 interrupt cause bits
 224  */
 225 #define C_SW0           (_ULCAST_(1) <<  8)
 226 #define C_SW1           (_ULCAST_(1) <<  9)
 227 #define C_IRQ0          (_ULCAST_(1) << 10)
 228 #define C_IRQ1          (_ULCAST_(1) << 11)
 229 #define C_IRQ2          (_ULCAST_(1) << 12)
 230 #define C_IRQ3          (_ULCAST_(1) << 13)
 231 #define C_IRQ4          (_ULCAST_(1) << 14)
 232 #define C_IRQ5          (_ULCAST_(1) << 15)
 233
 234 /*
 235  * Bitfields in the R4xx0 cp0 status register
 236  */
 237 #define ST0_IE                  0x00000001
 238 #define ST0_EXL                 0x00000002
 239 #define ST0_ERL                 0x00000004
 240 #define ST0_KSU                 0x00000018
 241 #  define KSU_USER              0x00000010
 242 #  define KSU_SUPERVISOR        0x00000008
 243 #  define KSU_KERNEL            0x00000000
 244 #define ST0_UX                  0x00000020
 245 #define ST0_SX                  0x00000040
 246 #define ST0_KX                  0x00000080
 247 #define ST0_DE                  0x00010000
 248 #define ST0_CE                  0x00020000
 249
 250 /*
 251  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 252  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 253  * processors.
 254  */
 255 #define ST0_CO                  0x08000000
 256
 257 /*
 258  * Bitfields in the R[23]000 cp0 status register.
 259  */
 260 #define ST0_IEC                 0x00000001
 261 #define ST0_KUC                 0x00000002
 262 #define ST0_IEP                 0x00000004
 263 #define ST0_KUP                 0x00000008
 264 #define ST0_IEO                 0x00000010
 265 #define ST0_KUO                 0x00000020
 266 /* bits 6 & 7 are reserved on R[23]000 */
 267 #define ST0_ISC                 0x00010000
 268 #define ST0_SWC                 0x00020000
 269 #define ST0_CM                  0x00080000
 270
 271 /*
 272  * Bits specific to the R4640/R4650
 273  */
 274 #define ST0_UM                  (_ULCAST_(1) <<  4)
 275 #define ST0_IL                  (_ULCAST_(1) << 23)
 276 #define ST0_DL                  (_ULCAST_(1) << 24)
 277
 278 /*
 279  * Enable the MIPS MDMX and DSP ASEs
 280  */
 281 #define ST0_MX                  0x01000000
 282
 283 /*
 284  * Bitfields in the TX39 family CP0 Configuration Register 3
 285  */
 286 #define TX39_CONF_ICS_SHIFT     19
 287 #define TX39_CONF_ICS_MASK      0x00380000
 288 #define TX39_CONF_ICS_1KB       0x00000000
 289 #define TX39_CONF_ICS_2KB       0x00080000
 290 #define TX39_CONF_ICS_4KB       0x00100000
 291 #define TX39_CONF_ICS_8KB       0x00180000
 292 #define TX39_CONF_ICS_16KB      0x00200000
 293
 294 #define TX39_CONF_DCS_SHIFT     16
 295 #define TX39_CONF_DCS_MASK      0x00070000
 296 #define TX39_CONF_DCS_1KB       0x00000000
 297 #define TX39_CONF_DCS_2KB       0x00010000
 298 #define TX39_CONF_DCS_4KB       0x00020000
 299 #define TX39_CONF_DCS_8KB       0x00030000
 300 #define TX39_CONF_DCS_16KB      0x00040000
 301
 302 #define TX39_CONF_CWFON         0x00004000
 303 #define TX39_CONF_WBON          0x00002000
 304 #define TX39_CONF_RF_SHIFT      10
 305 #define TX39_CONF_RF_MASK       0x00000c00
 306 #define TX39_CONF_DOZE          0x00000200
 307 #define TX39_CONF_HALT          0x00000100
 308 #define TX39_CONF_LOCK          0x00000080
 309 #define TX39_CONF_ICE           0x00000020
 310 #define TX39_CONF_DCE           0x00000010
 311 #define TX39_CONF_IRSIZE_SHIFT  2
 312 #define TX39_CONF_IRSIZE_MASK   0x0000000c
 313 #define TX39_CONF_DRSIZE_SHIFT  0
 314 #define TX39_CONF_DRSIZE_MASK   0x00000003
 315
 316 /*
 317  * Status register bits available in all MIPS CPUs.
 318  */
 319 #define ST0_IM                  0x0000ff00
 320 #define  STATUSB_IP0            8
 321 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
 322 #define  STATUSB_IP1            9
 323 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
 324 #define  STATUSB_IP2            10
 325 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
 326 #define  STATUSB_IP3            11
 327 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
 328 #define  STATUSB_IP4            12
 329 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
 330 #define  STATUSB_IP5            13
 331 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
 332 #define  STATUSB_IP6            14
 333 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
 334 #define  STATUSB_IP7            15
 335 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
 336 #define  STATUSB_IP8            0
 337 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
 338 #define  STATUSB_IP9            1
 339 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
 340 #define  STATUSB_IP10           2
 341 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
 342 #define  STATUSB_IP11           3
 343 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
 344 #define  STATUSB_IP12           4
 345 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
 346 #define  STATUSB_IP13           5
 347 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
 348 #define  STATUSB_IP14           6
 349 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
 350 #define  STATUSB_IP15           7
 351 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 352 #define ST0_CH                  0x00040000
 353 #define ST0_SR                  0x00100000
 354 #define ST0_TS                  0x00200000
 355 #define ST0_BEV                 0x00400000
 356 #define ST0_RE                  0x02000000
 357 #define ST0_FR                  0x04000000
 358 #define ST0_CU                  0xf0000000
 359 #define ST0_CU0                 0x10000000
 360 #define ST0_CU1                 0x20000000
 361 #define ST0_CU2                 0x40000000
 362 #define ST0_CU3                 0x80000000
 363 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 364
 365 /*
 366  * Bitfields and bit numbers in the coprocessor 0 cause register.
 367  *
 368  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 369  */
 370 #define  CAUSEB_EXCCODE         2
 371 #define  CAUSEF_EXCCODE         (_ULCAST_(31)  <<  2)
 372 #define  CAUSEB_IP              8
 373 #define  CAUSEF_IP              (_ULCAST_(255) <<  8)
 374 #define  CAUSEB_IP0             8
 375 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
 376 #define  CAUSEB_IP1             9
 377 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
 378 #define  CAUSEB_IP2             10
 379 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
 380 #define  CAUSEB_IP3             11
 381 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
 382 #define  CAUSEB_IP4             12
 383 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
 384 #define  CAUSEB_IP5             13
 385 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
 386 #define  CAUSEB_IP6             14
 387 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
 388 #define  CAUSEB_IP7             15
 389 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 390 #define  CAUSEB_IV              23
 391 #define  CAUSEF_IV              (_ULCAST_(1)   << 23)
 392 #define  CAUSEB_CE              28
 393 #define  CAUSEF_CE              (_ULCAST_(3)   << 28)
 394 #define  CAUSEB_BD              31
 395 #define  CAUSEF_BD              (_ULCAST_(1)   << 31)
 396
 397 /*
 398  * Bits in the coprocessor 0 config register.
 399  */
 400 /* Generic bits.  */
 401 #define CONF_CM_CACHABLE_NO_WA          0
 402 #define CONF_CM_CACHABLE_WA             1
 403 #define CONF_CM_UNCACHED                2
 404 #define CONF_CM_CACHABLE_NONCOHERENT    3
 405 #define CONF_CM_CACHABLE_CE             4
 406 #define CONF_CM_CACHABLE_COW            5
 407 #define CONF_CM_CACHABLE_CUW            6
 408 #define CONF_CM_CACHABLE_ACCELERATED    7
 409 #define CONF_CM_CMASK                   7
 410 #define CONF_BE                 (_ULCAST_(1) << 15)
 411
 412 /* Bits common to various processors.  */
 413 #define CONF_CU                 (_ULCAST_(1) <<  3)
 414 #define CONF_DB                 (_ULCAST_(1) <<  4)
 415 #define CONF_IB                 (_ULCAST_(1) <<  5)
 416 #define CONF_DC                 (_ULCAST_(7) <<  6)
 417 #define CONF_IC                 (_ULCAST_(7) <<  9)
 418 #define CONF_EB                 (_ULCAST_(1) << 13)
 419 #define CONF_EM                 (_ULCAST_(1) << 14)
 420 #define CONF_SM                 (_ULCAST_(1) << 16)
 421 #define CONF_SC                 (_ULCAST_(1) << 17)
 422 #define CONF_EW                 (_ULCAST_(3) << 18)
 423 #define CONF_EP                 (_ULCAST_(15)<< 24)
 424 #define CONF_EC                 (_ULCAST_(7) << 28)
 425 #define CONF_CM                 (_ULCAST_(1) << 31)
 426
 427 /* Bits specific to the R4xx0.  */
 428 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
 429 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
 430 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
 431
 432 /* Bits specific to the R5000.  */
 433 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 434 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
 435
 436 /* Bits specific to the RM7000.  */
 437 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
 438 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
 439 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
 440 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
 441 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
 442 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
 443
 444 /* Bits specific to the R10000.  */
 445 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 446 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
 447 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
 448 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
 449 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
 450 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
 451 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
 452 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
 453 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
 454 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
 455 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
 456
 457 /* Bits specific to the VR41xx.  */
 458 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
 459 #define VR41_CONF_P4K           (_ULCAST_(1) << 13)
 460 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
 461 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
 462 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
 463
 464 /* Bits specific to the R30xx.  */
 465 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
 466 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
 467 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
 468 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
 469 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
 470 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
 471 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
 472 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
 473 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
 474
 475 /* Bits specific to the TX49.  */
 476 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
 477 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 478 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
 479 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
 480
 481 /* Bits specific to the MIPS32/64 PRA.  */
 482 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
 483 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
 484 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
 485 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 486
 487 /*
 488  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 489  */
 490 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
 491 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
 492 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
 493 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
 494 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
 495 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
 496 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
 497 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
 498 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
 499 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
 500 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
 501 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
 502 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
 503 #define MIPS_CONF1_TLBS         (_ULCAST_(63)<< 25)
 504
 505 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
 506 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
 507 #define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
 508 #define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
 509 #define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
 510 #define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
 511 #define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
 512 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
 513
 514 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
 515 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
 516 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
 517 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
 518 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
 519 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 520 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 521 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
 522 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 523
 524 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 525
 526 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
 527
 528 /*
 529  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
 530  */
 531 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
 532 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
 533 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
 534 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
 535 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
 536 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
 537 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
 538
 539 #ifndef __ASSEMBLY__
 540
 541 /*
 542  * Functions to access the R10000 performance counters.  These are basically
 543  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
 544  * performance counter number encoded into bits 1 ... 5 of the instruction.
 545  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
 546  * disassembler these will look like an access to sel 0 or 1.
 547  */
 548 #define read_r10k_perf_cntr(counter)                            \
 549 ({                                                              \
 550         unsigned int __res;                                     \
 551         __asm__ __volatile__(                                   \
 552         "mfpc\t%0, %1"                                          \
 553         : "=r" (__res)                                          \
 554         : "i" (counter));                                       \
 555                                                                 \
 556         __res;                                                  \
 557 })
 558
 559 #define write_r10k_perf_cntr(counter,val)                       \
 560 do {                                                            \
 561         __asm__ __volatile__(                                   \
 562         "mtpc\t%0, %1"                                          \
 563         :                                                       \
 564         : "r" (val), "i" (counter));                            \
 565 } while (0)
 566
 567 #define read_r10k_perf_event(counter)                           \
 568 ({                                                              \
 569         unsigned int __res;                                     \
 570         __asm__ __volatile__(                                   \
 571         "mfps\t%0, %1"                                          \
 572         : "=r" (__res)                                          \
 573         : "i" (counter));                                       \
 574                                                                 \
 575         __res;                                                  \
 576 })
 577
 578 #define write_r10k_perf_cntl(counter,val)                       \
 579 do {                                                            \
 580         __asm__ __volatile__(                                   \
 581         "mtps\t%0, %1"                                          \
 582         :                                                       \
 583         : "r" (val), "i" (counter));                            \
 584 } while (0)
 585
 586 /*
 587  * Macros to access the system control coprocessor
 588  */
 589
 590 #define __read_32bit_c0_register(source, sel)                           \
 591 ({ int __res;                                                           \
 592         if (sel == 0)                                                   \
 593                 __asm__ __volatile__(                                   \
 594                         "mfc0\t%0, " #source "\n\t"                     \
 595                         : "=r" (__res));                                \
 596         else                                                            \
 597                 __asm__ __volatile__(                                   \
 598                         ".set\tmips32\n\t"                              \
 599                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
 600                         ".set\tmips0\n\t"                               \
 601                         : "=r" (__res));                                \
 602         __res;                                                          \
 603 })
 604
 605 #define __read_64bit_c0_register(source, sel)                           \
 606 ({ unsigned long long __res;                                            \
 607         if (sizeof(unsigned long) == 4)                                 \
 608                 __res = __read_64bit_c0_split(source, sel);             \
 609         else if (sel == 0)                                              \
 610                 __asm__ __volatile__(                                   \
 611                         ".set\tmips3\n\t"                               \
 612                         "dmfc0\t%0, " #source "\n\t"                    \
 613                         ".set\tmips0"                                   \
 614                         : "=r" (__res));                                \
 615         else                                                            \
 616                 __asm__ __volatile__(                                   \
 617                         ".set\tmips64\n\t"                              \
 618                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
 619                         ".set\tmips0"                                   \
 620                         : "=r" (__res));                                \
 621         __res;                                                          \
 622 })
 623
 624 #define __write_32bit_c0_register(register, sel, value)                 \
 625 do {                                                                    \
 626         if (sel == 0)                                                   \
 627                 __asm__ __volatile__(                                   \
 628                         "mtc0\t%z0, " #register "\n\t"                  \
 629                         : : "Jr" ((unsigned int)(value)));              \
 630         else                                                            \
 631                 __asm__ __volatile__(                                   \
 632                         ".set\tmips32\n\t"                              \
 633                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
 634                         ".set\tmips0"                                   \
 635                         : : "Jr" ((unsigned int)(value)));              \
 636 } while (0)
 637
 638 #define __write_64bit_c0_register(register, sel, value)                 \
 639 do {                                                                    \
 640         if (sizeof(unsigned long) == 4)                                 \
 641                 __write_64bit_c0_split(register, sel, value);           \
 642         else if (sel == 0)                                              \
 643                 __asm__ __volatile__(                                   \
 644                         ".set\tmips3\n\t"                               \
 645                         "dmtc0\t%z0, " #register "\n\t"                 \
 646                         ".set\tmips0"                                   \
 647                         : : "Jr" (value));                              \
 648         else                                                            \
 649                 __asm__ __volatile__(                                   \
 650                         ".set\tmips64\n\t"                              \
 651                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
 652                         ".set\tmips0"                                   \
 653                         : : "Jr" (value));                              \
 654 } while (0)
 655
 656 #define __read_ulong_c0_register(reg, sel)                              \
 657         ((sizeof(unsigned long) == 4) ?                                 \
 658         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
 659         (unsigned long) __read_64bit_c0_register(reg, sel))
 660
 661 #define __write_ulong_c0_register(reg, sel, val)                        \
 662 do {                                                                    \
 663         if (sizeof(unsigned long) == 4)                                 \
 664                 __write_32bit_c0_register(reg, sel, val);               \
 665         else                                                            \
 666                 __write_64bit_c0_register(reg, sel, val);               \
 667 } while (0)
 668
 669 /*
 670  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
 671  */
 672 #define __read_32bit_c0_ctrl_register(source)                           \
 673 ({ int __res;                                                           \
 674         __asm__ __volatile__(                                           \
 675                 "cfc0\t%0, " #source "\n\t"                             \
 676                 : "=r" (__res));                                        \
 677         __res;                                                          \
 678 })
 679
 680 #define __write_32bit_c0_ctrl_register(register, value)                 \
 681 do {                                                                    \
 682         __asm__ __volatile__(                                           \
 683                 "ctc0\t%z0, " #register "\n\t"                          \
 684                 : : "Jr" ((unsigned int)(value)));                      \
 685 } while (0)
 686
 687 /*
 688  * These versions are only needed for systems with more than 38 bits of
 689  * physical address space running the 32-bit kernel.  That's none atm :-)
 690  */
 691 #define __read_64bit_c0_split(source, sel)                              \
 692 ({                                                                      \
 693         unsigned long long __val;                                       \
 694         unsigned long __flags;                                          \
 695                                                                         \
 696         local_irq_save(__flags);                                        \
 697         if (sel == 0)                                                   \
 698                 __asm__ __volatile__(                                   \
 699                         ".set\tmips64\n\t"                              \
 700                         "dmfc0\t%M0, " #source "\n\t"                   \
 701                         "dsll\t%L0, %M0, 32\n\t"                        \
 702                         "dsrl\t%M0, %M0, 32\n\t"                        \
 703                         "dsrl\t%L0, %L0, 32\n\t"                        \
 704                         ".set\tmips0"                                   \
 705                         : "=r" (__val));                                \
 706         else                                                            \
 707                 __asm__ __volatile__(                                   \
 708                         ".set\tmips64\n\t"                              \
 709                         "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
 710                         "dsll\t%L0, %M0, 32\n\t"                        \
 711                         "dsrl\t%M0, %M0, 32\n\t"                        \
 712                         "dsrl\t%L0, %L0, 32\n\t"                        \
 713                         ".set\tmips0"                                   \
 714                         : "=r" (__val));                                \
 715         local_irq_restore(__flags);                                     \
 716                                                                         \
 717         __val;                                                          \
 718 })
 719
 720 #define __write_64bit_c0_split(source, sel, val)                        \
 721 do {                                                                    \
 722         unsigned long __flags;                                          \
 723                                                                         \
 724         local_irq_save(__flags);                                        \
 725         if (sel == 0)                                                   \
 726                 __asm__ __volatile__(                                   \
 727                         ".set\tmips64\n\t"                              \
 728                         "dsll\t%L0, %L0, 32\n\t"                        \
 729                         "dsrl\t%L0, %L0, 32\n\t"                        \
 730                         "dsll\t%M0, %M0, 32\n\t"                        \
 731                         "or\t%L0, %L0, %M0\n\t"                         \
 732                         "dmtc0\t%L0, " #source "\n\t"                   \
 733                         ".set\tmips0"                                   \
 734                         : : "r" (val));                                 \
 735         else                                                            \
 736                 __asm__ __volatile__(                                   \
 737                         ".set\tmips64\n\t"                              \
 738                         "dsll\t%L0, %L0, 32\n\t"                        \
 739                         "dsrl\t%L0, %L0, 32\n\t"                        \
 740                         "dsll\t%M0, %M0, 32\n\t"                        \
 741                         "or\t%L0, %L0, %M0\n\t"                         \
 742                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
 743                         ".set\tmips0"                                   \
 744                         : : "r" (val));                                 \
 745         local_irq_restore(__flags);                                     \
 746 } while (0)
 747
 748 #define read_c0_index()         __read_32bit_c0_register($0, 0)
 749 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
 750
 751 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
 752 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
 753
 754 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
 755 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
 756
 757 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
 758 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
 759
 760 #define read_c0_context()       __read_ulong_c0_register($4, 0)
 761 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
 762
 763 #define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
 764 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
 765
 766 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
 767 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
 768
 769 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
 770 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
 771
 772 #define read_c0_info()          __read_32bit_c0_register($7, 0)
 773
 774 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
 775 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
 776
 777 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
 778 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
 779
 780 #define read_c0_count()         __read_32bit_c0_register($9, 0)
 781 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
 782
 783 #define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
 784 #define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
 785
 786 #define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
 787 #define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
 788
 789 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
 790 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
 791
 792 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
 793 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
 794
 795 #define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
 796 #define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
 797
 798 #define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
 799 #define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
 800
 801 #define read_c0_status()        __read_32bit_c0_register($12, 0)
 802 #ifdef CONFIG_MIPS_MT_SMTC
 803 #define write_c0_status(val)                                            \
 804 do {                                                                    \
 805         __write_32bit_c0_register($12, 0, val);                         \
 806         __ehb();                                                        \
 807 } while (0)
 808 #else
 809 /*
 810  * Legacy non-SMTC code, which may be hazardous
 811  * but which might not support EHB
 812  */
 813 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
 814 #endif /* CONFIG_MIPS_MT_SMTC */
 815
 816 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
 817 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
 818
 819 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
 820 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
 821
 822 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
 823
 824 #define read_c0_config()        __read_32bit_c0_register($16, 0)
 825 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
 826 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
 827 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
 828 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
 829 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
 830 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
 831 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
 832 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
 833 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
 834 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
 835 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
 836 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
 837 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
 838 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
 839 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
 840
 841 /*
 842  * The WatchLo register.  There may be upto 8 of them.
 843  */
 844 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
 845 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
 846 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
 847 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
 848 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
 849 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
 850 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
 851 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
 852 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
 853 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
 854 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
 855 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
 856 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
 857 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
 858 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
 859 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
 860
 861 /*
 862  * The WatchHi register.  There may be upto 8 of them.
 863  */
 864 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
 865 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
 866 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
 867 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
 868 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
 869 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
 870 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
 871 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
 872
 873 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
 874 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
 875 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
 876 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
 877 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
 878 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
 879 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
 880 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
 881
 882 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
 883 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
 884
 885 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
 886 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
 887
 888 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
 889 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
 890
 891 /* RM9000 PerfControl performance counter control register */
 892 #define read_c0_perfcontrol()   __read_32bit_c0_register($22, 0)
 893 #define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
 894
 895 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
 896 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
 897
 898 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
 899 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
 900
 901 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
 902 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
 903
 904 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
 905 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
 906
 907 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
 908 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
 909
 910 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
 911 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
 912
 913 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
 914 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
 915
 916 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
 917 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
 918
 919 /*
 920  * MIPS32 / MIPS64 performance counters
 921  */
 922 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
 923 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
 924 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
 925 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
 926 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
 927 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
 928 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
 929 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
 930 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
 931 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
 932 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
 933 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
 934 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
 935 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
 936 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
 937 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
 938
 939 /* RM9000 PerfCount performance counter register */
 940 #define read_c0_perfcount()     __read_64bit_c0_register($25, 0)
 941 #define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
 942
 943 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
 944 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
 945
 946 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
 947 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
 948
 949 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
 950
 951 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
 952 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
 953
 954 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
 955 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
 956
 957 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
 958 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
 959
 960 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
 961 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
 962
 963 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
 964 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
 965
 966 /* MIPSR2 */
 967 #define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
 968 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
 969
 970 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
 971 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
 972
 973 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
 974 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
 975
 976 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
 977 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
 978
 979 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
 980 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
 981
 982 /*
 983  * Macros to access the floating point coprocessor control registers
 984  */
 985 #define read_32bit_cp1_register(source)                         \
 986 ({ int __res;                                                   \
 987         __asm__ __volatile__(                                   \
 988         ".set\tpush\n\t"                                        \
 989         ".set\treorder\n\t"                                     \
 990         "cfc1\t%0,"STR(source)"\n\t"                            \
 991         ".set\tpop"                                             \
 992         : "=r" (__res));                                        \
 993         __res;})
 994
 995 #define rddsp(mask)                                                     \
 996 ({                                                                      \
 997         unsigned int __res;                                             \
 998                                                                         \
 999         __asm__ __volatile__(                                           \
1000         "       .set    push                            \n"             \
1001         "       .set    noat                            \n"             \
1002         "       # rddsp $1, %x1                         \n"             \
1003         "       .word   0x7c000cb8 | (%x1 << 16)        \n"             \
1004         "       move    %0, $1                          \n"             \
1005         "       .set    pop                             \n"             \
1006         : "=r" (__res)                                                  \
1007         : "i" (mask));                                                  \
1008         __res;                                                          \
1009 })
1010
1011 #define wrdsp(val, mask)                                                \
1012 do {                                                                    \
1013         __asm__ __volatile__(                                           \
1014         "       .set    push                                    \n"     \
1015         "       .set    noat                                    \n"     \
1016         "       move    $1, %0                                  \n"     \
1017         "       # wrdsp $1, %x1                                 \n"     \
1018         "       .word   0x7c2004f8 | (%x1 << 11)                \n"     \
1019         "       .set    pop                                     \n"     \
1020         :                                                               \
1021         : "r" (val), "i" (mask));                                       \
1022 } while (0)
1023
1024 #define mfhi0()                                                         \
1025 ({                                                                      \
1026         unsigned long __treg;                                           \
1027                                                                         \
1028         __asm__ __volatile__(                                           \
1029         "       .set    push                    \n"                     \
1030         "       .set    noat                    \n"                     \
1031         "       # mfhi  %0, $ac0                \n"                     \
1032         "       .word   0x00000810              \n"                     \
1033         "       move    %0, $1                  \n"                     \
1034         "       .set    pop                     \n"                     \
1035         : "=r" (__treg));                                               \
1036         __treg;                                                         \
1037 })
1038
1039 #define mfhi1()                                                         \
1040 ({                                                                      \
1041         unsigned long __treg;                                           \
1042                                                                         \
1043         __asm__ __volatile__(                                           \
1044         "       .set    push                    \n"                     \
1045         "       .set    noat                    \n"                     \
1046         "       # mfhi  %0, $ac1                \n"                     \
1047         "       .word   0x00200810              \n"                     \
1048         "       move    %0, $1                  \n"                     \
1049         "       .set    pop                     \n"                     \
1050         : "=r" (__treg));                                               \
1051         __treg;                                                         \
1052 })
1053
1054 #define mfhi2()                                                         \
1055 ({                                                                      \
1056         unsigned long __treg;                                           \
1057                                                                         \
1058         __asm__ __volatile__(                                           \
1059         "       .set    push                    \n"                     \
1060         "       .set    noat                    \n"                     \
1061         "       # mfhi  %0, $ac2                \n"                     \
1062         "       .word   0x00400810              \n"                     \
1063         "       move    %0, $1                  \n"                     \
1064         "       .set    pop                     \n"                     \
1065         : "=r" (__treg));                                               \
1066         __treg;                                                         \
1067 })
1068
1069 #define mfhi3()                                                         \
1070 ({                                                                      \
1071         unsigned long __treg;                                           \
1072                                                                         \
1073         __asm__ __volatile__(                                           \
1074         "       .set    push                    \n"                     \
1075         "       .set    noat                    \n"                     \
1076         "       # mfhi  %0, $ac3                \n"                     \
1077         "       .word   0x00600810              \n"                     \
1078         "       move    %0, $1                  \n"                     \
1079         "       .set    pop                     \n"                     \
1080         : "=r" (__treg));                                               \
1081         __treg;                                                         \
1082 })
1083
1084 #define mflo0()                                                         \
1085 ({                                                                      \
1086         unsigned long __treg;                                           \
1087                                                                         \
1088         __asm__ __volatile__(                                           \
1089         "       .set    push                    \n"                     \
1090         "       .set    noat                    \n"                     \
1091         "       # mflo  %0, $ac0                \n"                     \
1092         "       .word   0x00000812              \n"                     \
1093         "       move    %0, $1                  \n"                     \
1094         "       .set    pop                     \n"                     \
1095         : "=r" (__treg));                                               \
1096         __treg;                                                         \
1097 })
1098
1099 #define mflo1()                                                         \
1100 ({                                                                      \
1101         unsigned long __treg;                                           \
1102                                                                         \
1103         __asm__ __volatile__(                                           \
1104         "       .set    push                    \n"                     \
1105         "       .set    noat                    \n"                     \
1106         "       # mflo  %0, $ac1                \n"                     \
1107         "       .word   0x00200812              \n"                     \
1108         "       move    %0, $1                  \n"                     \
1109         "       .set    pop                     \n"                     \
1110         : "=r" (__treg));                                               \
1111         __treg;                                                         \
1112 })
1113
1114 #define mflo2()                                                         \
1115 ({                                                                      \
1116         unsigned long __treg;                                           \
1117                                                                         \
1118         __asm__ __volatile__(                                           \
1119         "       .set    push                    \n"                     \
1120         "       .set    noat                    \n"                     \
1121         "       # mflo  %0, $ac2                \n"                     \
1122         "       .word   0x00400812              \n"                     \
1123         "       move    %0, $1                  \n"                     \
1124         "       .set    pop                     \n"                     \
1125         : "=r" (__treg));                                               \
1126         __treg;                                                         \
1127 })
1128
1129 #define mflo3()                                                         \
1130 ({                                                                      \
1131         unsigned long __treg;                                           \
1132                                                                         \
1133         __asm__ __volatile__(                                           \
1134         "       .set    push                    \n"                     \
1135         "       .set    noat                    \n"                     \
1136         "       # mflo  %0, $ac3                \n"                     \
1137         "       .word   0x00600812              \n"                     \
1138         "       move    %0, $1                  \n"                     \
1139         "       .set    pop                     \n"                     \
1140         : "=r" (__treg));                                               \
1141         __treg;                                                         \
1142 })
1143
1144 #define mthi0(x)                                                        \
1145 do {                                                                    \
1146         __asm__ __volatile__(                                           \
1147         "       .set    push                                    \n"     \
1148         "       .set    noat                                    \n"     \
1149         "       move    $1, %0                                  \n"     \
1150         "       # mthi  $1, $ac0                                \n"     \
1151         "       .word   0x00200011                              \n"     \
1152         "       .set    pop                                     \n"     \
1153         :                                                               \
1154         : "r" (x));                                                     \
1155 } while (0)
1156
1157 #define mthi1(x)                                                        \
1158 do {                                                                    \
1159         __asm__ __volatile__(                                           \
1160         "       .set    push                                    \n"     \
1161         "       .set    noat                                    \n"     \
1162         "       move    $1, %0                                  \n"     \
1163         "       # mthi  $1, $ac1                                \n"     \
1164         "       .word   0x00200811                              \n"     \
1165         "       .set    pop                                     \n"     \
1166         :                                                               \
1167         : "r" (x));                                                     \
1168 } while (0)
1169
1170 #define mthi2(x)                                                        \
1171 do {                                                                    \
1172         __asm__ __volatile__(                                           \
1173         "       .set    push                                    \n"     \
1174         "       .set    noat                                    \n"     \
1175         "       move    $1, %0                                  \n"     \
1176         "       # mthi  $1, $ac2                                \n"     \
1177         "       .word   0x00201011                              \n"     \
1178         "       .set    pop                                     \n"     \
1179         :                                                               \
1180         : "r" (x));                                                     \
1181 } while (0)
1182
1183 #define mthi3(x)                                                        \
1184 do {                                                                    \
1185         __asm__ __volatile__(                                           \
1186         "       .set    push                                    \n"     \
1187         "       .set    noat                                    \n"     \
1188         "       move    $1, %0                                  \n"     \
1189         "       # mthi  $1, $ac3                                \n"     \
1190         "       .word   0x00201811                              \n"     \
1191         "       .set    pop                                     \n"     \
1192         :                                                               \
1193         : "r" (x));                                                     \
1194 } while (0)
1195
1196 #define mtlo0(x)                                                        \
1197 do {                                                                    \
1198         __asm__ __volatile__(                                           \
1199         "       .set    push                                    \n"     \
1200         "       .set    noat                                    \n"     \
1201         "       move    $1, %0                                  \n"     \
1202         "       # mtlo  $1, $ac0                                \n"     \
1203         "       .word   0x00200013                              \n"     \
1204         "       .set    pop                                     \n"     \
1205         :                                                               \
1206         : "r" (x));                                                     \
1207 } while (0)
1208
1209 #define mtlo1(x)                                                        \
1210 do {                                                                    \
1211         __asm__ __volatile__(                                           \
1212         "       .set    push                                    \n"     \
1213         "       .set    noat                                    \n"     \
1214         "       move    $1, %0                                  \n"     \
1215         "       # mtlo  $1, $ac1                                \n"     \
1216         "       .word   0x00200813                              \n"     \
1217         "       .set    pop                                     \n"     \
1218         :                                                               \
1219         : "r" (x));                                                     \
1220 } while (0)
1221
1222 #define mtlo2(x)                                                        \
1223 do {                                                                    \
1224         __asm__ __volatile__(                                           \
1225         "       .set    push                                    \n"     \
1226         "       .set    noat                                    \n"     \
1227         "       move    $1, %0                                  \n"     \
1228         "       # mtlo  $1, $ac2                                \n"     \
1229         "       .word   0x00201013                              \n"     \
1230         "       .set    pop                                     \n"     \
1231         :                                                               \
1232         : "r" (x));                                                     \
1233 } while (0)
1234
1235 #define mtlo3(x)                                                        \
1236 do {                                                                    \
1237         __asm__ __volatile__(                                           \
1238         "       .set    push                                    \n"     \
1239         "       .set    noat                                    \n"     \
1240         "       move    $1, %0                                  \n"     \
1241         "       # mtlo  $1, $ac3                                \n"     \
1242         "       .word   0x00201813                              \n"     \
1243         "       .set    pop                                     \n"     \
1244         :                                                               \
1245         : "r" (x));                                                     \
1246 } while (0)
1247
1248 /*
1249  * TLB operations.
1250  *
1251  * It is responsibility of the caller to take care of any TLB hazards.
1252  */
1253 static inline void tlb_probe(void)
1254 {
1255         __asm__ __volatile__(
1256                 ".set noreorder\n\t"
1257                 "tlbp\n\t"
1258                 ".set reorder");
1259 }
1260
1261 static inline void tlb_read(void)
1262 {
1263 #if MIPS34K_MISSED_ITLB_WAR
1264         int res = 0;
1265
1266         __asm__ __volatile__(
1267         "       .set    push                                    \n"
1268         "       .set    noreorder                               \n"
1269         "       .set    noat                                    \n"
1270         "       .set    mips32r2                                \n"
1271         "       .word   0x41610001              # dvpe $1       \n"
1272         "       move    %0, $1                                  \n"
1273         "       ehb                                             \n"
1274         "       .set    pop                                     \n"
1275         : "=r" (res));
1276
1277         instruction_hazard();
1278 #endif
1279
1280         __asm__ __volatile__(
1281                 ".set noreorder\n\t"
1282                 "tlbr\n\t"
1283                 ".set reorder");
1284
1285 #if MIPS34K_MISSED_ITLB_WAR
1286         if ((res & _ULCAST_(1)))
1287                 __asm__ __volatile__(
1288                 "       .set    push                            \n"
1289                 "       .set    noreorder                       \n"
1290                 "       .set    noat                            \n"
1291                 "       .set    mips32r2                        \n"
1292                 "       .word   0x41600021      # evpe          \n"
1293                 "       ehb                                     \n"
1294                 "       .set    pop                             \n");
1295 #endif
1296 }
1297
1298 static inline void tlb_write_indexed(void)
1299 {
1300         __asm__ __volatile__(
1301                 ".set noreorder\n\t"
1302                 "tlbwi\n\t"
1303                 ".set reorder");
1304 }
1305
1306 static inline void tlb_write_random(void)
1307 {
1308         __asm__ __volatile__(
1309                 ".set noreorder\n\t"
1310                 "tlbwr\n\t"
1311                 ".set reorder");
1312 }
1313
1314 /*
1315  * Manipulate bits in a c0 register.
1316  */
1317 #define __BUILD_SET_C0(name)                                    \
1318 static inline unsigned int                                      \
1319 set_c0_##name(unsigned int set)                                 \
1320 {                                                               \
1321         unsigned int res;                                       \
1322                                                                 \
1323         res = read_c0_##name();                                 \
1324         res |= set;                                             \
1325         write_c0_##name(res);                                   \
1326                                                                 \
1327         return res;                                             \
1328 }                                                               \
1329                                                                 \
1330 static inline unsigned int                                      \
1331 clear_c0_##name(unsigned int clear)                             \
1332 {                                                               \
1333         unsigned int res;                                       \
1334                                                                 \
1335         res = read_c0_##name();                                 \
1336         res &= ~clear;                                          \
1337         write_c0_##name(res);                                   \
1338                                                                 \
1339         return res;                                             \
1340 }                                                               \
1341                                                                 \
1342 static inline unsigned int                                      \
1343 change_c0_##name(unsigned int change, unsigned int new)         \
1344 {                                                               \
1345         unsigned int res;                                       \
1346                                                                 \
1347         res = read_c0_##name();                                 \
1348         res &= ~change;                                         \
1349         res |= (new & change);                                  \
1350         write_c0_##name(res);                                   \
1351                                                                 \
1352         return res;                                             \
1353 }
1354
1355 __BUILD_SET_C0(status)
1356 __BUILD_SET_C0(cause)
1357 __BUILD_SET_C0(config)
1358 __BUILD_SET_C0(intcontrol)
1359 __BUILD_SET_C0(intctl)
1360 __BUILD_SET_C0(srsmap)
1361
1362 #endif /* !__ASSEMBLY__ */
1363
1364 #endif /* _ASM_MIPSREGS_H */