2 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
13 #ifndef __ASM_PPC_FSL_LBC_H
14 #define __ASM_PPC_FSL_LBC_H
18 /* BR - Base Registers
20 #define BR0 0x5000 /* Register offset to immr */
29 #define BR_BA 0xFFFF8000
30 #define BR_BA_SHIFT 15
31 #define BR_PS 0x00001800
32 #define BR_PS_SHIFT 11
33 #define BR_PS_8 0x00000800 /* Port Size 8 bit */
34 #define BR_PS_16 0x00001000 /* Port Size 16 bit */
35 #define BR_PS_32 0x00001800 /* Port Size 32 bit */
36 #define BR_DECC 0x00000600
37 #define BR_DECC_SHIFT 9
38 #define BR_DECC_OFF 0x00000000
39 #define BR_DECC_CHK 0x00000200
40 #define BR_DECC_CHK_GEN 0x00000400
41 #define BR_WP 0x00000100
43 #define BR_MSEL 0x000000E0
44 #define BR_MSEL_SHIFT 5
45 #define BR_MS_GPCM 0x00000000 /* GPCM */
46 #define BR_MS_FCM 0x00000020 /* FCM */
48 #define BR_MS_SDRAM 0x00000060 /* SDRAM */
49 #elif defined(CONFIG_MPC85xx)
50 #define BR_MS_SDRAM 0x00000000 /* SDRAM */
52 #define BR_MS_UPMA 0x00000080 /* UPMA */
53 #define BR_MS_UPMB 0x000000A0 /* UPMB */
54 #define BR_MS_UPMC 0x000000C0 /* UPMC */
55 #if !defined(CONFIG_MPC834X)
56 #define BR_ATOM 0x0000000C
57 #define BR_ATOM_SHIFT 2
59 #define BR_V 0x00000001
66 #if defined(CONFIG_MPC834X)
67 #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
69 #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
72 /* Convert an address into the right format for the BR registers */
73 #ifdef CONFIG_PHYS_64BIT
74 #define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \
75 ((x & 0x300000000ULL) >> 19)))
77 #define BR_PHYS_ADDR(x) (x & 0xffff8000)
80 /* OR - Option Registers
82 #define OR0 0x5004 /* Register offset to immr */
91 #define OR_GPCM_AM 0xFFFF8000
92 #define OR_GPCM_AM_SHIFT 15
93 #define OR_GPCM_BCTLD 0x00001000
94 #define OR_GPCM_BCTLD_SHIFT 12
95 #define OR_GPCM_CSNT 0x00000800
96 #define OR_GPCM_CSNT_SHIFT 11
97 #define OR_GPCM_ACS 0x00000600
98 #define OR_GPCM_ACS_SHIFT 9
99 #define OR_GPCM_ACS_DIV2 0x00000600
100 #define OR_GPCM_ACS_DIV4 0x00000400
101 #define OR_GPCM_XACS 0x00000100
102 #define OR_GPCM_XACS_SHIFT 8
103 #define OR_GPCM_SCY 0x000000F0
104 #define OR_GPCM_SCY_SHIFT 4
105 #define OR_GPCM_SCY_1 0x00000010
106 #define OR_GPCM_SCY_2 0x00000020
107 #define OR_GPCM_SCY_3 0x00000030
108 #define OR_GPCM_SCY_4 0x00000040
109 #define OR_GPCM_SCY_5 0x00000050
110 #define OR_GPCM_SCY_6 0x00000060
111 #define OR_GPCM_SCY_7 0x00000070
112 #define OR_GPCM_SCY_8 0x00000080
113 #define OR_GPCM_SCY_9 0x00000090
114 #define OR_GPCM_SCY_10 0x000000a0
115 #define OR_GPCM_SCY_11 0x000000b0
116 #define OR_GPCM_SCY_12 0x000000c0
117 #define OR_GPCM_SCY_13 0x000000d0
118 #define OR_GPCM_SCY_14 0x000000e0
119 #define OR_GPCM_SCY_15 0x000000f0
120 #define OR_GPCM_SETA 0x00000008
121 #define OR_GPCM_SETA_SHIFT 3
122 #define OR_GPCM_TRLX 0x00000004
123 #define OR_GPCM_TRLX_SHIFT 2
124 #define OR_GPCM_EHTR 0x00000002
125 #define OR_GPCM_EHTR_SHIFT 1
126 #define OR_GPCM_EAD 0x00000001
127 #define OR_GPCM_EAD_SHIFT 0
129 /* helpers to convert values into an OR address mask (GPCM mode) */
130 #define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
131 #define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20)
133 #define OR_FCM_AM 0xFFFF8000
134 #define OR_FCM_AM_SHIFT 15
135 #define OR_FCM_BCTLD 0x00001000
136 #define OR_FCM_BCTLD_SHIFT 12
137 #define OR_FCM_PGS 0x00000400
138 #define OR_FCM_PGS_SHIFT 10
139 #define OR_FCM_CSCT 0x00000200
140 #define OR_FCM_CSCT_SHIFT 9
141 #define OR_FCM_CST 0x00000100
142 #define OR_FCM_CST_SHIFT 8
143 #define OR_FCM_CHT 0x00000080
144 #define OR_FCM_CHT_SHIFT 7
145 #define OR_FCM_SCY 0x00000070
146 #define OR_FCM_SCY_SHIFT 4
147 #define OR_FCM_SCY_1 0x00000010
148 #define OR_FCM_SCY_2 0x00000020
149 #define OR_FCM_SCY_3 0x00000030
150 #define OR_FCM_SCY_4 0x00000040
151 #define OR_FCM_SCY_5 0x00000050
152 #define OR_FCM_SCY_6 0x00000060
153 #define OR_FCM_SCY_7 0x00000070
154 #define OR_FCM_RST 0x00000008
155 #define OR_FCM_RST_SHIFT 3
156 #define OR_FCM_TRLX 0x00000004
157 #define OR_FCM_TRLX_SHIFT 2
158 #define OR_FCM_EHTR 0x00000002
159 #define OR_FCM_EHTR_SHIFT 1
161 #define OR_UPM_AM 0xFFFF8000
162 #define OR_UPM_AM_SHIFT 15
163 #define OR_UPM_XAM 0x00006000
164 #define OR_UPM_XAM_SHIFT 13
165 #define OR_UPM_BCTLD 0x00001000
166 #define OR_UPM_BCTLD_SHIFT 12
167 #define OR_UPM_BI 0x00000100
168 #define OR_UPM_BI_SHIFT 8
169 #define OR_UPM_TRLX 0x00000004
170 #define OR_UPM_TRLX_SHIFT 2
171 #define OR_UPM_EHTR 0x00000002
172 #define OR_UPM_EHTR_SHIFT 1
173 #define OR_UPM_EAD 0x00000001
174 #define OR_UPM_EAD_SHIFT 0
176 #define OR_SDRAM_AM 0xFFFF8000
177 #define OR_SDRAM_AM_SHIFT 15
178 #define OR_SDRAM_XAM 0x00006000
179 #define OR_SDRAM_XAM_SHIFT 13
180 #define OR_SDRAM_COLS 0x00001C00
181 #define OR_SDRAM_COLS_SHIFT 10
182 #define OR_SDRAM_ROWS 0x000001C0
183 #define OR_SDRAM_ROWS_SHIFT 6
184 #define OR_SDRAM_PMSEL 0x00000020
185 #define OR_SDRAM_PMSEL_SHIFT 5
186 #define OR_SDRAM_EAD 0x00000001
187 #define OR_SDRAM_EAD_SHIFT 0
189 #define OR_AM_32KB 0xFFFF8000
190 #define OR_AM_64KB 0xFFFF0000
191 #define OR_AM_128KB 0xFFFE0000
192 #define OR_AM_256KB 0xFFFC0000
193 #define OR_AM_512KB 0xFFF80000
194 #define OR_AM_1MB 0xFFF00000
195 #define OR_AM_2MB 0xFFE00000
196 #define OR_AM_4MB 0xFFC00000
197 #define OR_AM_8MB 0xFF800000
198 #define OR_AM_16MB 0xFF000000
199 #define OR_AM_32MB 0xFE000000
200 #define OR_AM_64MB 0xFC000000
201 #define OR_AM_128MB 0xF8000000
202 #define OR_AM_256MB 0xF0000000
203 #define OR_AM_512MB 0xE0000000
204 #define OR_AM_1GB 0xC0000000
205 #define OR_AM_2GB 0x80000000
206 #define OR_AM_4GB 0x00000000
208 /* MxMR - UPM Machine A/B/C Mode Registers
210 #define MxMR_MAD_MSK 0x0000003f /* Machine Address Mask */
211 #define MxMR_TLFx_MSK 0x000003c0 /* Refresh Loop Field Mask */
212 #define MxMR_WLFx_MSK 0x00003c00 /* Write Loop Field Mask */
213 #define MxMR_WLFx_1X 0x00000400 /* executed 1 time */
214 #define MxMR_WLFx_2X 0x00000800 /* executed 2 times */
215 #define MxMR_WLFx_3X 0x00000c00 /* executed 3 times */
216 #define MxMR_WLFx_4X 0x00001000 /* executed 4 times */
217 #define MxMR_WLFx_5X 0x00001400 /* executed 5 times */
218 #define MxMR_WLFx_6X 0x00001800 /* executed 6 times */
219 #define MxMR_WLFx_7X 0x00001c00 /* executed 7 times */
220 #define MxMR_WLFx_8X 0x00002000 /* executed 8 times */
221 #define MxMR_WLFx_9X 0x00002400 /* executed 9 times */
222 #define MxMR_WLFx_10X 0x00002800 /* executed 10 times */
223 #define MxMR_WLFx_11X 0x00002c00 /* executed 11 times */
224 #define MxMR_WLFx_12X 0x00003000 /* executed 12 times */
225 #define MxMR_WLFx_13X 0x00003400 /* executed 13 times */
226 #define MxMR_WLFx_14X 0x00003800 /* executed 14 times */
227 #define MxMR_WLFx_15X 0x00003c00 /* executed 15 times */
228 #define MxMR_WLFx_16X 0x00000000 /* executed 16 times */
229 #define MxMR_RLFx_MSK 0x0003c000 /* Read Loop Field Mask */
230 #define MxMR_GPL_x4DIS 0x00040000 /* GPL_A4 Ouput Line Disable */
231 #define MxMR_G0CLx_MSK 0x00380000 /* General Line 0 Control Mask */
232 #define MxMR_DSx_1_CYCL 0x00000000 /* 1 cycle Disable Period */
233 #define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */
234 #define MxMR_DSx_3_CYCL 0x00800000 /* 3 cycle Disable Period */
235 #define MxMR_DSx_4_CYCL 0x00c00000 /* 4 cycle Disable Period */
236 #define MxMR_DSx_MSK 0x00c00000 /* Disable Timer Period Mask */
237 #define MxMR_AMx_MSK 0x07000000 /* Addess Multiplex Size Mask */
238 #define MxMR_OP_NORM 0x00000000 /* Normal Operation */
239 #define MxMR_OP_WARR 0x10000000 /* Write to Array */
240 #define MxMR_OP_RARR 0x20000000 /* Read from Array */
241 #define MxMR_OP_RUNP 0x30000000 /* Run Pattern */
242 #define MxMR_OP_MSK 0x30000000 /* Command Opcode Mask */
243 #define MxMR_RFEN 0x40000000 /* Refresh Enable */
244 #define MxMR_BSEL 0x80000000 /* Bus Select */
246 #define LBLAWAR_EN 0x80000000
247 #define LBLAWAR_4KB 0x0000000B
248 #define LBLAWAR_8KB 0x0000000C
249 #define LBLAWAR_16KB 0x0000000D
250 #define LBLAWAR_32KB 0x0000000E
251 #define LBLAWAR_64KB 0x0000000F
252 #define LBLAWAR_128KB 0x00000010
253 #define LBLAWAR_256KB 0x00000011
254 #define LBLAWAR_512KB 0x00000012
255 #define LBLAWAR_1MB 0x00000013
256 #define LBLAWAR_2MB 0x00000014
257 #define LBLAWAR_4MB 0x00000015
258 #define LBLAWAR_8MB 0x00000016
259 #define LBLAWAR_16MB 0x00000017
260 #define LBLAWAR_32MB 0x00000018
261 #define LBLAWAR_64MB 0x00000019
262 #define LBLAWAR_128MB 0x0000001A
263 #define LBLAWAR_256MB 0x0000001B
264 #define LBLAWAR_512MB 0x0000001C
265 #define LBLAWAR_1GB 0x0000001D
266 #define LBLAWAR_2GB 0x0000001E
268 /* LBCR - Local Bus Configuration Register
270 #define LBCR_LDIS 0x80000000
271 #define LBCR_LDIS_SHIFT 31
272 #define LBCR_BCTLC 0x00C00000
273 #define LBCR_BCTLC_SHIFT 22
274 #define LBCR_LPBSE 0x00020000
275 #define LBCR_LPBSE_SHIFT 17
276 #define LBCR_EPAR 0x00010000
277 #define LBCR_EPAR_SHIFT 16
278 #define LBCR_BMT 0x0000FF00
279 #define LBCR_BMT_SHIFT 8
281 /* LCRR - Clock Ratio Register
283 #define LCRR_DBYP 0x80000000
284 #define LCRR_DBYP_SHIFT 31
285 #define LCRR_BUFCMDC 0x30000000
286 #define LCRR_BUFCMDC_SHIFT 28
287 #define LCRR_BUFCMDC_1 0x10000000
288 #define LCRR_BUFCMDC_2 0x20000000
289 #define LCRR_BUFCMDC_3 0x30000000
290 #define LCRR_BUFCMDC_4 0x00000000
291 #define LCRR_ECL 0x03000000
292 #define LCRR_ECL_SHIFT 24
293 #define LCRR_ECL_4 0x00000000
294 #define LCRR_ECL_5 0x01000000
295 #define LCRR_ECL_6 0x02000000
296 #define LCRR_ECL_7 0x03000000
297 #define LCRR_EADC 0x00030000
298 #define LCRR_EADC_SHIFT 16
299 #define LCRR_EADC_1 0x00010000
300 #define LCRR_EADC_2 0x00020000
301 #define LCRR_EADC_3 0x00030000
302 #define LCRR_EADC_4 0x00000000
303 #define LCRR_CLKDIV 0x0000000F
304 #define LCRR_CLKDIV_SHIFT 0
305 #define LCRR_CLKDIV_2 0x00000002
306 #define LCRR_CLKDIV_4 0x00000004
307 #define LCRR_CLKDIV_8 0x00000008
309 /* LTEDR - Transfer Error Check Disable Register
311 #define LTEDR_BMD 0x80000000 /* Bus monitor disable */
312 #define LTEDR_PARD 0x20000000 /* Parity error checking disabled */
313 #define LTEDR_WPD 0x04000000 /* Write protect error checking diable */
314 #define LTEDR_WARA 0x00800000 /* Write-after-read-atomic error checking diable */
315 #define LTEDR_RAWA 0x00400000 /* Read-after-write-atomic error checking disable */
316 #define LTEDR_CSD 0x00080000 /* Chip select error checking disable */
318 /* FMR - Flash Mode Register
320 #define FMR_CWTO 0x0000F000
321 #define FMR_CWTO_SHIFT 12
322 #define FMR_BOOT 0x00000800
323 #define FMR_ECCM 0x00000100
324 #define FMR_AL 0x00000030
325 #define FMR_AL_SHIFT 4
326 #define FMR_OP 0x00000003
327 #define FMR_OP_SHIFT 0
329 /* FIR - Flash Instruction Register
331 #define FIR_OP0 0xF0000000
332 #define FIR_OP0_SHIFT 28
333 #define FIR_OP1 0x0F000000
334 #define FIR_OP1_SHIFT 24
335 #define FIR_OP2 0x00F00000
336 #define FIR_OP2_SHIFT 20
337 #define FIR_OP3 0x000F0000
338 #define FIR_OP3_SHIFT 16
339 #define FIR_OP4 0x0000F000
340 #define FIR_OP4_SHIFT 12
341 #define FIR_OP5 0x00000F00
342 #define FIR_OP5_SHIFT 8
343 #define FIR_OP6 0x000000F0
344 #define FIR_OP6_SHIFT 4
345 #define FIR_OP7 0x0000000F
346 #define FIR_OP7_SHIFT 0
347 #define FIR_OP_NOP 0x0 /* No operation and end of sequence */
348 #define FIR_OP_CA 0x1 /* Issue current column address */
349 #define FIR_OP_PA 0x2 /* Issue current block+page address */
350 #define FIR_OP_UA 0x3 /* Issue user defined address */
351 #define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
352 #define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
353 #define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
354 #define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
355 #define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
356 #define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
357 #define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
358 #define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
359 #define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
360 #define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
361 #define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
362 #define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */
364 /* FCR - Flash Command Register
366 #define FCR_CMD0 0xFF000000
367 #define FCR_CMD0_SHIFT 24
368 #define FCR_CMD1 0x00FF0000
369 #define FCR_CMD1_SHIFT 16
370 #define FCR_CMD2 0x0000FF00
371 #define FCR_CMD2_SHIFT 8
372 #define FCR_CMD3 0x000000FF
373 #define FCR_CMD3_SHIFT 0
374 /* FBAR - Flash Block Address Register
376 #define FBAR_BLK 0x00FFFFFF
378 /* FPAR - Flash Page Address Register
380 #define FPAR_SP_PI 0x00007C00
381 #define FPAR_SP_PI_SHIFT 10
382 #define FPAR_SP_MS 0x00000200
383 #define FPAR_SP_CI 0x000001FF
384 #define FPAR_SP_CI_SHIFT 0
385 #define FPAR_LP_PI 0x0003F000
386 #define FPAR_LP_PI_SHIFT 12
387 #define FPAR_LP_MS 0x00000800
388 #define FPAR_LP_CI 0x000007FF
389 #define FPAR_LP_CI_SHIFT 0
391 /* LTESR - Transfer Error Status Register
393 #define LTESR_BM 0x80000000
394 #define LTESR_FCT 0x40000000
395 #define LTESR_PAR 0x20000000
396 #define LTESR_WP 0x04000000
397 #define LTESR_ATMW 0x00800000
398 #define LTESR_ATMR 0x00400000
399 #define LTESR_CS 0x00080000
400 #define LTESR_CC 0x00000001
404 * Local Bus Controller Registers.
406 typedef struct lbus_bank {
407 u32 br; /* Base Register */
408 u32 or; /* Option Register */
411 typedef struct fsl_lbus {
414 u32 mar; /* UPM Address Register */
416 u32 mamr; /* UPMA Mode Register */
417 u32 mbmr; /* UPMB Mode Register */
418 u32 mcmr; /* UPMC Mode Register */
420 u32 mrtpr; /* Memory Refresh Timer Prescaler Register */
421 u32 mdr; /* UPM Data Register */
423 u32 lsor; /* Special Operation Initiation Register */
424 u32 lsdmr; /* SDRAM Mode Register */
426 u32 lurt; /* UPM Refresh Timer */
427 u32 lsrt; /* SDRAM Refresh Timer */
429 u32 ltesr; /* Transfer Error Status Register */
430 u32 ltedr; /* Transfer Error Disable Register */
431 u32 lteir; /* Transfer Error Interrupt Register */
432 u32 lteatr; /* Transfer Error Attributes Register */
433 u32 ltear; /* Transfer Error Address Register */
435 u32 lbcr; /* Configuration Register */
436 u32 lcrr; /* Clock Ratio Register */
438 u32 fmr; /* Flash Mode Register */
439 u32 fir; /* Flash Instruction Register */
440 u32 fcr; /* Flash Command Register */
441 u32 fbar; /* Flash Block Addr Register */
442 u32 fpar; /* Flash Page Addr Register */
443 u32 fbcr; /* Flash Byte Count Register */
446 #endif /* __ASSEMBLY__ */
448 #endif /* __ASM_PPC_FSL_LBC_H */