3 * MPC8260 Internal Memory Map
4 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
6 * The Internal Memory Map of the 8260. I don't know how generic
7 * this will be, as I don't have any knowledge of the subsequent
8 * parts at this time. I copied this from the 8xx_immap.h.
10 #ifndef __IMMAP_82XX__
11 #define __IMMAP_82XX__
13 /* System configuration registers.
15 typedef struct sys_conf {
43 /* Memory controller registers.
45 typedef struct mem_ctlr {
95 /* System Integration Timers.
97 typedef struct sys_int_timers {
113 #define PISCR_PIRQ_MASK ((ushort)0xff00)
114 #define PISCR_PS ((ushort)0x0080)
115 #define PISCR_PIE ((ushort)0x0004)
116 #define PISCR_PTF ((ushort)0x0002)
117 #define PISCR_PTE ((ushort)0x0001)
119 /* Interrupt Controller.
121 typedef struct interrupt_controller {
138 typedef struct clk_and_reset {
148 /* Input/Output Port control/status registers.
149 * Names consistent with processor manual, although they are different
150 * from the original 8xx names.......
152 typedef struct io_port {
179 /* Communication Processor Module Timers
181 typedef struct cpm_timers {
209 /* DMA control/status registers.
211 typedef struct sdma_csr {
250 u_char fcc_ftirr_phy[4];
270 typedef struct scc { /* Serial communication channels */
285 typedef struct smc { /* Serial management channels */
295 /* Serial Peripheral Interface.
297 typedef struct im_spi {
310 typedef struct cpmux {
325 typedef struct siram {
348 typedef struct comm_proc {
361 /* ...and the whole thing wrapped up....
363 typedef struct immap {
364 /* Some references are into the unique and known dpram spaces,
365 * others are from the generic base.
367 #define im_dprambase im_dpram1
368 u_char im_dpram1[16*1024];
370 u_char im_dpram2[4*1024];
372 u_char im_dpram3[4*1024];
375 sysconf8260_t im_siu_conf; /* SIU Configuration */
376 memctl8260_t im_memctl; /* Memory Controller */
377 sit8260_t im_sit; /* System Integration Timers */
378 intctl8260_t im_intctl; /* Interrupt Controller */
379 car8260_t im_clkrst; /* Clocks and reset */
380 iop8260_t im_ioport; /* IO Port control/status */
381 cpmtimer8260_t im_cpmtimer; /* CPM timers */
382 sdma8260_t im_sdma; /* SDMA control/status */
384 fcc_t im_fcc[3]; /* Three FCCs */
388 /* First set of baud rate generators.
398 i2c8260_t im_i2c; /* I2C control/status */
399 cpm8260_t im_cpm; /* Communication processor */
401 /* Second set of baud rate generators.
408 scc_t im_scc[4]; /* Four SCCs */
409 smc_t im_smc[2]; /* Couple of SMCs */
410 im_spi_t im_spi; /* A SPI */
411 cpmux_t im_cpmux; /* CPM clock route mux */
412 siramctl_t im_siramctl1; /* First SI RAM Control */
413 mcc_t im_mcc1; /* First MCC */
414 siramctl_t im_siramctl2; /* Second SI RAM Control */
415 mcc_t im_mcc2; /* Second MCC */
419 ushort im_si1txram[256];
421 ushort im_si1rxram[256];
423 ushort im_si2txram[256];
425 ushort im_si2rxram[256];
430 #endif /* __IMMAP_82XX__ */