2 * MPC85xx Internal Memory Map
4 * Copyright 2007-2009 Freescale Semiconductor, Inc.
6 * Copyright(c) 2002,2003 Motorola Inc.
7 * Xianghua Xiao (x.xiao@motorola.com)
11 #ifndef __IMMAP_85xx__
12 #define __IMMAP_85xx__
14 #include <asm/types.h>
15 #include <asm/fsl_dma.h>
16 #include <asm/fsl_i2c.h>
17 #include <asm/fsl_lbc.h>
19 typedef struct ccsr_local {
20 u32 ccsrbarh; /* 0x0 - Control Configuration Status Registers Base Address Register High */
21 u32 ccsrbarl; /* 0x4 - Control Configuration Status Registers Base Address Register Low */
22 u32 ccsrar; /* 0x8 - Configuration, Control, and Status Attribute Register */
23 #define CCSRAR_C 0x80000000 /* Commit */
25 u32 altcbarh; /* 0x10 - Alternate Configuration Base Address Register High */
26 u32 altcbarl; /* 0x14 - Alternate Configuration Base Address Register Low */
27 u32 altcar; /* 0x18 - Alternate Configuration Attribute Register */
29 u32 bstrh; /* 0x20 - Boot space translation register high */
30 u32 bstrl; /* 0x24 - Boot space translation register Low */
31 u32 bstrar; /* 0x28 - Boot space translation attributes register */
34 u32 lawbarh; /* 0xc00 + n * 0x10 - LAW0 base address register high */
35 u32 lawbarl; /* 0xc04 + n * 0x10 - LAW0 base address register low */
36 u32 lawar; /* 0xc08 + n * 0x10 - LAW0 attributes register */
43 * Local-Access Registers and ECM Registers(0x0000-0x2000)
45 typedef struct ccsr_local_ecm {
46 uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
48 uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */
50 uint altcar; /* 0x10 - Alternate Configuration Attribute Register */
52 uint bptr; /* 0x20 - Boot Page Translation Register */
54 uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */
56 uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */
58 uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */
60 uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */
62 uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */
64 uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */
66 uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */
68 uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */
70 uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */
72 uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */
74 uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */
76 uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */
78 uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */
80 uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */
82 uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
84 uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
86 uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */
88 uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */
90 uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */
92 uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */
94 uint lawbar10; /* 0xd48 - Local Access Window 10 Base Address Register */
96 uint lawar10; /* 0xd50 - Local Access Window 10 Attributes Register */
98 uint lawbar11; /* 0xd68 - Local Access Window 11 Base Address Register */
100 uint lawar11; /* 0xd70 - Local Access Window 11 Attributes Register */
102 uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */
104 uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */
106 uint eedr; /* 0x1e00 - ECM Error Detect Register */
108 uint eeer; /* 0x1e08 - ECM Error Enable Register */
109 uint eeatr; /* 0x1e0c - ECM Error Attributes Capture Register */
110 uint eeadr; /* 0x1e10 - ECM Error Address Capture Register */
115 * DDR memory controller registers(0x2000-0x3000)
117 typedef struct ccsr_ddr {
118 uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */
120 uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */
122 uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */
124 uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */
126 uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */
127 uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */
128 uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */
129 uint cs3_config; /* 0x208c - DDR Chip Select Configuration */
131 uint cs0_config_2; /* 0x20c0 - DDR Chip Select Configuration 2 */
132 uint cs1_config_2; /* 0x20c4 - DDR Chip Select Configuration 2 */
133 uint cs2_config_2; /* 0x20c8 - DDR Chip Select Configuration 2 */
134 uint cs3_config_2; /* 0x20cc - DDR Chip Select Configuration 2 */
136 uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */
137 uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
138 uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
139 uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
140 uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration */
141 uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */
142 uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration */
143 uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2*/
144 uint sdram_md_cntl; /* 0x2120 - DDR SDRAM Mode Control */
145 uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */
146 uint sdram_data_init; /* 0x2128 - DDR SDRAM Data initialization */
148 uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */
150 uint init_addr; /* 0x2148 - DDR training initialization address */
151 uint init_ext_addr; /* 0x214C - DDR training initialization extended address */
153 uint timing_cfg_4; /* 0x2160 - DDR SDRAM Timing Configuration Register 4 */
154 uint timing_cfg_5; /* 0x2164 - DDR SDRAM Timing Configuration Register 5 */
156 uint ddr_zq_cntl; /* 0x2170 - DDR ZQ calibration control*/
157 uint ddr_wrlvl_cntl; /* 0x2174 - DDR write leveling control*/
159 uint ddr_sr_cntr; /* 0x217C - DDR self refresh counter */
160 uint ddr_sdram_rcw_1; /* 0x2180 - DDR Register Control Words 1 */
161 uint ddr_sdram_rcw_2; /* 0x2184 - DDR Register Control Words 2 */
163 uint ddr_dsr1; /* 0x2B20 - DDR Debug Status Register 1 */
164 uint ddr_dsr2; /* 0x2B24 - DDR Debug Status Register 2 */
165 uint ddr_cdr1; /* 0x2B28 - DDR Control Driver Register 1 */
166 uint ddr_cdr2; /* 0x2B2C - DDR Control Driver Register 2 */
168 uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */
169 uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */
171 uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
172 uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
173 uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
175 uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */
176 uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */
177 uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */
179 uint err_detect; /* 0x2e40 - DDR Memory Error Detect */
180 uint err_disable; /* 0x2e44 - DDR Memory Error Disable */
181 uint err_int_en; /* 0x2e48 - DDR */
182 uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */
183 uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */
184 uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */
185 uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */
187 uint debug_1; /* 0x2f00 */
199 uint debug_13; /* +0xF30 */
204 uint debug_18; /* +0xF44 */
209 * I2C Registers(0x3000-0x4000)
211 typedef struct ccsr_i2c {
212 struct fsl_i2c i2c[1];
213 u8 res[4096 - 1 * sizeof(struct fsl_i2c)];
216 #if defined(CONFIG_MPC8540) \
217 || defined(CONFIG_MPC8541) \
218 || defined(CONFIG_MPC8548) \
219 || defined(CONFIG_MPC8555)
220 /* DUART Registers(0x4000-0x5000) */
221 typedef struct ccsr_duart {
223 u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
224 u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
225 u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
226 u_char ulcr1; /* 0x4503 - UART1 Line Control Register */
227 u_char umcr1; /* 0x4504 - UART1 Modem Control Register */
228 u_char ulsr1; /* 0x4505 - UART1 Line Status Register */
229 u_char umsr1; /* 0x4506 - UART1 Modem Status Register */
230 u_char uscr1; /* 0x4507 - UART1 Scratch Register */
232 u_char udsr1; /* 0x4510 - UART1 DMA Status Register */
234 u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
235 u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
236 u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
237 u_char ulcr2; /* 0x4603 - UART2 Line Control Register */
238 u_char umcr2; /* 0x4604 - UART2 Modem Control Register */
239 u_char ulsr2; /* 0x4605 - UART2 Line Status Register */
240 u_char umsr2; /* 0x4606 - UART2 Modem Status Register */
241 u_char uscr2; /* 0x4607 - UART2 Scratch Register */
243 u_char udsr2; /* 0x4610 - UART2 DMA Status Register */
246 #else /* MPC8560 uses UART on its CPM */
247 typedef struct ccsr_duart {
252 /* Local Bus Controller Registers(0x5000-0x6000) */
253 /* Omitting OCeaN(0x6000) and Reserved(0x7000) block */
255 typedef struct ccsr_lbc {
256 uint br0; /* 0x5000 - LBC Base Register 0 */
257 uint or0; /* 0x5004 - LBC Options Register 0 */
258 uint br1; /* 0x5008 - LBC Base Register 1 */
259 uint or1; /* 0x500c - LBC Options Register 1 */
260 uint br2; /* 0x5010 - LBC Base Register 2 */
261 uint or2; /* 0x5014 - LBC Options Register 2 */
262 uint br3; /* 0x5018 - LBC Base Register 3 */
263 uint or3; /* 0x501c - LBC Options Register 3 */
264 uint br4; /* 0x5020 - LBC Base Register 4 */
265 uint or4; /* 0x5024 - LBC Options Register 4 */
266 uint br5; /* 0x5028 - LBC Base Register 5 */
267 uint or5; /* 0x502c - LBC Options Register 5 */
268 uint br6; /* 0x5030 - LBC Base Register 6 */
269 uint or6; /* 0x5034 - LBC Options Register 6 */
270 uint br7; /* 0x5038 - LBC Base Register 7 */
271 uint or7; /* 0x503c - LBC Options Register 7 */
273 uint mar; /* 0x5068 - LBC UPM Address Register */
275 uint mamr; /* 0x5070 - LBC UPMA Mode Register */
276 uint mbmr; /* 0x5074 - LBC UPMB Mode Register */
277 uint mcmr; /* 0x5078 - LBC UPMC Mode Register */
279 uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */
280 uint mdr; /* 0x5088 - LBC UPM Data Register */
282 uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */
284 uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */
285 uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */
287 uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */
288 uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */
289 uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */
290 uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */
291 uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */
293 uint lbcr; /* 0x50d0 - LBC Configuration Register */
294 uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */
299 * eSPI Registers(0x7000-0x8000)
301 typedef struct ccsr_espi {
302 uint mode; /* 0x00 - eSPI mode register */
303 uint event; /* 0x04 - eSPI event register */
304 uint mask; /* 0x08 - eSPI mask register */
305 uint com; /* 0x0c - eSPI command register */
306 uint tx; /* 0x10 - eSPI transmit FIFO access register */
307 uint rx; /* 0x14 - eSPI receive FIFO access register */
308 char res1[8]; /* reserved */
309 uint csmode[4]; /* 0x20 - 0x2c: sSPI CS0/1/2/3 mode register */
310 char res2[4048]; /* fill up to 0x1000 */
314 * PCI Registers(0x8000-0x9000)
316 typedef struct ccsr_pcix {
317 uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */
318 uint cfg_data; /* 0x8004 - PCIX Configuration Data Register */
319 uint int_ack; /* 0x8008 - PCIX Interrupt Acknowledge Register */
321 uint potar0; /* 0x8c00 - PCIX Outbound Transaction Address Register 0 */
322 uint potear0; /* 0x8c04 - PCIX Outbound Translation Extended Address Register 0 */
323 uint powbar0; /* 0x8c08 - PCIX Outbound Window Base Address Register 0 */
324 uint powbear0; /* 0x8c0c - PCIX Outbound Window Base Extended Address Register 0 */
325 uint powar0; /* 0x8c10 - PCIX Outbound Window Attributes Register 0 */
327 uint potar1; /* 0x8c20 - PCIX Outbound Transaction Address Register 1 */
328 uint potear1; /* 0x8c24 - PCIX Outbound Translation Extended Address Register 1 */
329 uint powbar1; /* 0x8c28 - PCIX Outbound Window Base Address Register 1 */
330 uint powbear1; /* 0x8c2c - PCIX Outbound Window Base Extended Address Register 1 */
331 uint powar1; /* 0x8c30 - PCIX Outbound Window Attributes Register 1 */
333 uint potar2; /* 0x8c40 - PCIX Outbound Transaction Address Register 2 */
334 uint potear2; /* 0x8c44 - PCIX Outbound Translation Extended Address Register 2 */
335 uint powbar2; /* 0x8c48 - PCIX Outbound Window Base Address Register 2 */
336 uint powbear2; /* 0x8c4c - PCIX Outbound Window Base Extended Address Register 2 */
337 uint powar2; /* 0x8c50 - PCIX Outbound Window Attributes Register 2 */
339 uint potar3; /* 0x8c60 - PCIX Outbound Transaction Address Register 3 */
340 uint potear3; /* 0x8c64 - PCIX Outbound Translation Extended Address Register 3 */
341 uint powbar3; /* 0x8c68 - PCIX Outbound Window Base Address Register 3 */
342 uint powbear3; /* 0x8c6c - PCIX Outbound Window Base Extended Address Register 3 */
343 uint powar3; /* 0x8c70 - PCIX Outbound Window Attributes Register 3 */
345 uint potar4; /* 0x8c80 - PCIX Outbound Transaction Address Register 4 */
346 uint potear4; /* 0x8c84 - PCIX Outbound Translation Extended Address Register 4 */
347 uint powbar4; /* 0x8c88 - PCIX Outbound Window Base Address Register 4 */
348 uint powbear4; /* 0x8c8c - PCIX Outbound Window Base Extended Address Register 4 */
349 uint powar4; /* 0x8c90 - PCIX Outbound Window Attributes Register 4 */
351 uint pitar3; /* 0x8da0 - PCIX Inbound Translation Address Register 3 */
352 uint pitear3; /* 0x8da4 - PCIX Inbound Translation Extended Address Register 3 */
353 uint piwbar3; /* 0x8da8 - PCIX Inbound Window Base Address Register 3 */
354 uint piwbear3; /* 0x8dac - PCIX Inbound Window Base Extended Address Register 3 */
355 uint piwar3; /* 0x8db0 - PCIX Inbound Window Attributes Register 3 */
357 uint pitar2; /* 0x8dc0 - PCIX Inbound Translation Address Register 2 */
358 uint pitear2; /* 0x8dc4 - PCIX Inbound Translation Extended Address Register 2 */
359 uint piwbar2; /* 0x8dc8 - PCIX Inbound Window Base Address Register 2 */
360 uint piwbear2; /* 0x8dcc - PCIX Inbound Window Base Extended Address Register 2 */
361 uint piwar2; /* 0x8dd0 - PCIX Inbound Window Attributes Register 2 */
363 uint pitar1; /* 0x8de0 - PCIX Inbound Translation Address Register 1 */
364 uint pitear1; /* 0x8de4 - PCIX Inbound Translation Extended Address Register 1 */
365 uint piwbar1; /* 0x8de8 - PCIX Inbound Window Base Address Register 1 */
367 uint piwar1; /* 0x8df0 - PCIX Inbound Window Attributes Register 1 */
369 uint pedr; /* 0x8e00 - PCIX Error Detect Register */
370 uint pecdr; /* 0x8e04 - PCIX Error Capture Disable Register */
371 uint peer; /* 0x8e08 - PCIX Error Enable Register */
372 uint peattrcr; /* 0x8e0c - PCIX Error Attributes Capture Register */
373 uint peaddrcr; /* 0x8e10 - PCIX Error Address Capture Register */
374 uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */
375 uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */
376 uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */
377 uint gas_timr; /* 0x8e20 - PCIX Gasket Timer Register */
381 typedef struct ccsr_gpio {
390 #define PCIX_COMMAND 0x62
391 #define POWAR_EN 0x80000000
392 #define POWAR_IO_READ 0x00080000
393 #define POWAR_MEM_READ 0x00040000
394 #define POWAR_IO_WRITE 0x00008000
395 #define POWAR_MEM_WRITE 0x00004000
396 #define POWAR_MEM_512M 0x0000001c
397 #define POWAR_IO_1M 0x00000013
399 #define PIWAR_EN 0x80000000
400 #define PIWAR_PF 0x20000000
401 #define PIWAR_LOCAL 0x00f00000
402 #define PIWAR_READ_SNOOP 0x00050000
403 #define PIWAR_WRITE_SNOOP 0x00005000
404 #define PIWAR_MEM_2G 0x0000001e
408 * L2 Cache Registers(0x2_0000-0x2_1000)
410 typedef struct ccsr_l2cache {
411 uint l2ctl; /* 0x20000 - L2 configuration register 0 */
413 uint l2cewar0; /* 0x20010 - L2 cache external write address register 0 */
415 uint l2cewcr0; /* 0x20018 - L2 cache external write control register 0 */
417 uint l2cewar1; /* 0x20020 - L2 cache external write address register 1 */
419 uint l2cewcr1; /* 0x20028 - L2 cache external write control register 1 */
421 uint l2cewar2; /* 0x20030 - L2 cache external write address register 2 */
423 uint l2cewcr2; /* 0x20038 - L2 cache external write control register 2 */
425 uint l2cewar3; /* 0x20040 - L2 cache external write address register 3 */
427 uint l2cewcr3; /* 0x20048 - L2 cache external write control register 3 */
429 uint l2srbar0; /* 0x20100 - L2 memory-mapped SRAM base address register 0 */
431 uint l2srbar1; /* 0x20108 - L2 memory-mapped SRAM base address register 1 */
433 uint l2errinjhi; /* 0x20e00 - L2 error injection mask high register */
434 uint l2errinjlo; /* 0x20e04 - L2 error injection mask low register */
435 uint l2errinjctl; /* 0x20e08 - L2 error injection tag/ECC control register */
437 uint l2captdatahi; /* 0x20e20 - L2 error data high capture register */
438 uint l2captdatalo; /* 0x20e24 - L2 error data low capture register */
439 uint l2captecc; /* 0x20e28 - L2 error ECC capture register */
441 uint l2errdet; /* 0x20e40 - L2 error detect register */
442 uint l2errdis; /* 0x20e44 - L2 error disable register */
443 uint l2errinten; /* 0x20e48 - L2 error interrupt enable register */
444 uint l2errattr; /* 0x20e4c - L2 error attributes capture register */
445 uint l2erraddr; /* 0x20e50 - L2 error address capture register */
447 uint l2errctl; /* 0x20e58 - L2 error control register */
451 #define MPC85xx_L2CTL_L2E 0x80000000
452 #define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000
453 #define MPC85xx_L2ERRDIS_MBECC 0x00000008
454 #define MPC85xx_L2ERRDIS_SBECC 0x00000004
457 * DMA Registers(0x2_1000-0x2_2000)
459 typedef struct ccsr_dma {
461 struct fsl_dma dma[4];
462 uint dgsr; /* 0x21300 - DMA General Status Register */
467 * tsec1 tsec2: 24000-26000
469 typedef struct ccsr_tsec {
471 uint ievent; /* 0x24010 - Interrupt Event Register */
472 uint imask; /* 0x24014 - Interrupt Mask Register */
473 uint edis; /* 0x24018 - Error Disabled Register */
475 uint ecntrl; /* 0x24020 - Ethernet Control Register */
476 uint minflr; /* 0x24024 - Minimum Frame Length Register */
477 uint ptv; /* 0x24028 - Pause Time Value Register */
478 uint dmactrl; /* 0x2402c - DMA Control Register */
479 uint tbipa; /* 0x24030 - TBI PHY Address Register */
481 uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */
483 uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */
484 uint fifo_tx_starve_shutoff; /* 0x2409c - FIFO transmit starve shutoff register */
486 uint tctrl; /* 0x24100 - Transmit Control Register */
487 uint tstat; /* 0x24104 - Transmit Status Register */
489 uint tbdlen; /* 0x2410c - Transmit Buffer Descriptor Data Length Register */
491 uint ctbptrh; /* 0x24120 - Current Transmit Buffer Descriptor Pointer High Register */
492 uint ctbptr; /* 0x24124 - Current Transmit Buffer Descriptor Pointer Register */
494 uint tbptrh; /* 0x24180 - Transmit Buffer Descriptor Pointer High Register */
495 uint tbptr; /* 0x24184 - Transmit Buffer Descriptor Pointer Low Register */
497 uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */
498 uint tbase; /* 0x24204 - Transmit Descriptor Base Address Register */
500 uint ostbd; /* 0x242b0 - Out-of-Sequence Transmit Buffer Descriptor Register */
501 uint ostbdp; /* 0x242b4 - Out-of-Sequence Transmit Data Buffer Pointer Register */
502 uint os32tbdp; /* 0x242b8 - Out-of-Sequence 32 Bytes Transmit Data Buffer Pointer Low Register */
503 uint os32iptrh; /* 0x242bc - Out-of-Sequence 32 Bytes Transmit Insert Pointer High Register */
504 uint os32iptrl; /* 0x242c0 - Out-of-Sequence 32 Bytes Transmit Insert Pointer Low Register */
505 uint os32tbdr; /* 0x242c4 - Out-of-Sequence 32 Bytes Transmit Reserved Register */
506 uint os32iil; /* 0x242c8 - Out-of-Sequence 32 Bytes Transmit Insert Index/Length Register */
508 uint rctrl; /* 0x24300 - Receive Control Register */
509 uint rstat; /* 0x24304 - Receive Status Register */
511 uint rbdlen; /* 0x2430c - RxBD Data Length Register */
513 uint crbptrh; /* 0x24320 - Current Receive Buffer Descriptor Pointer High */
514 uint crbptr; /* 0x24324 - Current Receive Buffer Descriptor Pointer */
516 uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */
517 uint mrblr2r3; /* 0x24344 - Maximum Receive Buffer Length R2R3 Register */
519 uint rbptrh; /* 0x24380 - Receive Buffer Descriptor Pointer High 0 */
520 uint rbptr; /* 0x24384 - Receive Buffer Descriptor Pointer */
521 uint rbptrh1; /* 0x24388 - Receive Buffer Descriptor Pointer High 1 */
522 uint rbptrl1; /* 0x2438c - Receive Buffer Descriptor Pointer Low 1 */
523 uint rbptrh2; /* 0x24390 - Receive Buffer Descriptor Pointer High 2 */
524 uint rbptrl2; /* 0x24394 - Receive Buffer Descriptor Pointer Low 2 */
525 uint rbptrh3; /* 0x24398 - Receive Buffer Descriptor Pointer High 3 */
526 uint rbptrl3; /* 0x2439c - Receive Buffer Descriptor Pointer Low 3 */
528 uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */
529 uint rbase; /* 0x24404 - Receive Descriptor Base Address */
530 uint rbaseh1; /* 0x24408 - Receive Descriptor Base Address High 1 */
531 uint rbasel1; /* 0x2440c - Receive Descriptor Base Address Low 1 */
532 uint rbaseh2; /* 0x24410 - Receive Descriptor Base Address High 2 */
533 uint rbasel2; /* 0x24414 - Receive Descriptor Base Address Low 2 */
534 uint rbaseh3; /* 0x24418 - Receive Descriptor Base Address High 3 */
535 uint rbasel3; /* 0x2441c - Receive Descriptor Base Address Low 3 */
537 uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */
538 uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */
539 uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
540 uint hafdup; /* 0x2450c - Half Duplex Register */
541 uint maxfrm; /* 0x24510 - Maximum Frame Length Register */
543 uint miimcfg; /* 0x24520 - MII Management Configuration Register */
544 uint miimcom; /* 0x24524 - MII Management Command Register */
545 uint miimadd; /* 0x24528 - MII Management Address Register */
546 uint miimcon; /* 0x2452c - MII Management Control Register */
547 uint miimstat; /* 0x24530 - MII Management Status Register */
548 uint miimind; /* 0x24534 - MII Management Indicator Register */
550 uint ifstat; /* 0x2453c - Interface Status Register */
551 uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */
552 uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */
554 uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */
555 uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
556 uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
557 uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
558 uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
559 uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
560 uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
561 uint rbyt; /* 0x2469c - Receive Byte Counter */
562 uint rpkt; /* 0x246a0 - Receive Packet Counter */
563 uint rfcs; /* 0x246a4 - Receive FCS Error Counter */
564 uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */
565 uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */
566 uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */
567 uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */
568 uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */
569 uint raln; /* 0x246bc - Receive Alignment Error Counter */
570 uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */
571 uint rcde; /* 0x246c4 - Receive Code Error Counter */
572 uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */
573 uint rund; /* 0x246cc - Receive Undersize Packet Counter */
574 uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */
575 uint rfrg; /* 0x246d4 - Receive Fragments Counter */
576 uint rjbr; /* 0x246d8 - Receive Jabber Counter */
577 uint rdrp; /* 0x246dc - Receive Drop Counter */
578 uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */
579 uint tpkt; /* 0x246e4 - Transmit Packet Counter */
580 uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */
581 uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */
582 uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */
583 uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */
584 uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */
585 uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */
586 uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */
587 uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */
588 uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */
589 uint tncl; /* 0x2470c - Transmit Total Collision Counter */
591 uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */
592 uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */
593 uint tfcs; /* 0x2471c - Transmit FCS Error Counter */
594 uint txcf; /* 0x24720 - Transmit Control Frame Counter */
595 uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */
596 uint tund; /* 0x24728 - Transmit Undersize Frame Counter */
597 uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */
598 uint car1; /* 0x24730 - Carry Register One */
599 uint car2; /* 0x24734 - Carry Register Two */
600 uint cam1; /* 0x24738 - Carry Mask Register One */
601 uint cam2; /* 0x2473c - Carry Mask Register Two */
603 uint iaddr0; /* 0x24800 - Indivdual address register 0 */
604 uint iaddr1; /* 0x24804 - Indivdual address register 1 */
605 uint iaddr2; /* 0x24808 - Indivdual address register 2 */
606 uint iaddr3; /* 0x2480c - Indivdual address register 3 */
607 uint iaddr4; /* 0x24810 - Indivdual address register 4 */
608 uint iaddr5; /* 0x24814 - Indivdual address register 5 */
609 uint iaddr6; /* 0x24818 - Indivdual address register 6 */
610 uint iaddr7; /* 0x2481c - Indivdual address register 7 */
612 uint gaddr0; /* 0x24880 - Global address register 0 */
613 uint gaddr1; /* 0x24884 - Global address register 1 */
614 uint gaddr2; /* 0x24888 - Global address register 2 */
615 uint gaddr3; /* 0x2488c - Global address register 3 */
616 uint gaddr4; /* 0x24890 - Global address register 4 */
617 uint gaddr5; /* 0x24894 - Global address register 5 */
618 uint gaddr6; /* 0x24898 - Global address register 6 */
619 uint gaddr7; /* 0x2489c - Global address register 7 */
621 uint pmd0; /* 0x24900 - Pattern Match Data Register */
623 uint pmask0; /* 0x24908 - Pattern Mask Register */
625 uint pcntrl0; /* 0x24910 - Pattern Match Control Register */
627 uint pattrb0; /* 0x24918 - Pattern Match Attributes Register */
628 uint pattrbeli0; /* 0x2491c - Pattern Match Attributes Extract Length and Extract Index Register */
629 uint pmd1; /* 0x24920 - Pattern Match Data Register */
631 uint pmask1; /* 0x24928 - Pattern Mask Register */
633 uint pcntrl1; /* 0x24930 - Pattern Match Control Register */
635 uint pattrb1; /* 0x24938 - Pattern Match Attributes Register */
636 uint pattrbeli1; /* 0x2493c - Pattern Match Attributes Extract Length and Extract Index Register */
637 uint pmd2; /* 0x24940 - Pattern Match Data Register */
639 uint pmask2; /* 0x24948 - Pattern Mask Register */
641 uint pcntrl2; /* 0x24950 - Pattern Match Control Register */
643 uint pattrb2; /* 0x24958 - Pattern Match Attributes Register */
644 uint pattrbeli2; /* 0x2495c - Pattern Match Attributes Extract Length and Extract Index Register */
645 uint pmd3; /* 0x24960 - Pattern Match Data Register */
647 uint pmask3; /* 0x24968 - Pattern Mask Register */
649 uint pcntrl3; /* 0x24970 - Pattern Match Control Register */
651 uint pattrb3; /* 0x24978 - Pattern Match Attributes Register */
652 uint pattrbeli3; /* 0x2497c - Pattern Match Attributes Extract Length and Extract Index Register */
653 uint pmd4; /* 0x24980 - Pattern Match Data Register */
655 uint pmask4; /* 0x24988 - Pattern Mask Register */
657 uint pcntrl4; /* 0x24990 - Pattern Match Control Register */
659 uint pattrb4; /* 0x24998 - Pattern Match Attributes Register */
660 uint pattrbeli4; /* 0x2499c - Pattern Match Attributes Extract Length and Extract Index Register */
661 uint pmd5; /* 0x249a0 - Pattern Match Data Register */
663 uint pmask5; /* 0x249a8 - Pattern Mask Register */
665 uint pcntrl5; /* 0x249b0 - Pattern Match Control Register */
667 uint pattrb5; /* 0x249b8 - Pattern Match Attributes Register */
668 uint pattrbeli5; /* 0x249bc - Pattern Match Attributes Extract Length and Extract Index Register */
669 uint pmd6; /* 0x249c0 - Pattern Match Data Register */
671 uint pmask6; /* 0x249c8 - Pattern Mask Register */
673 uint pcntrl6; /* 0x249d0 - Pattern Match Control Register */
675 uint pattrb6; /* 0x249d8 - Pattern Match Attributes Register */
676 uint pattrbeli6; /* 0x249dc - Pattern Match Attributes Extract Length and Extract Index Register */
677 uint pmd7; /* 0x249e0 - Pattern Match Data Register */
679 uint pmask7; /* 0x249e8 - Pattern Mask Register */
681 uint pcntrl7; /* 0x249f0 - Pattern Match Control Register */
683 uint pattrb7; /* 0x249f8 - Pattern Match Attributes Register */
684 uint pattrbeli7; /* 0x249fc - Pattern Match Attributes Extract Length and Extract Index Register */
685 uint pmd8; /* 0x24a00 - Pattern Match Data Register */
687 uint pmask8; /* 0x24a08 - Pattern Mask Register */
689 uint pcntrl8; /* 0x24a10 - Pattern Match Control Register */
691 uint pattrb8; /* 0x24a18 - Pattern Match Attributes Register */
692 uint pattrbeli8; /* 0x24a1c - Pattern Match Attributes Extract Length and Extract Index Register */
693 uint pmd9; /* 0x24a20 - Pattern Match Data Register */
695 uint pmask9; /* 0x24a28 - Pattern Mask Register */
697 uint pcntrl9; /* 0x24a30 - Pattern Match Control Register */
699 uint pattrb9; /* 0x24a38 - Pattern Match Attributes Register */
700 uint pattrbeli9; /* 0x24a3c - Pattern Match Attributes Extract Length and Extract Index Register */
701 uint pmd10; /* 0x24a40 - Pattern Match Data Register */
703 uint pmask10; /* 0x24a48 - Pattern Mask Register */
705 uint pcntrl10; /* 0x24a50 - Pattern Match Control Register */
707 uint pattrb10; /* 0x24a58 - Pattern Match Attributes Register */
708 uint pattrbeli10; /* 0x24a5c - Pattern Match Attributes Extract Length and Extract Index Register */
709 uint pmd11; /* 0x24a60 - Pattern Match Data Register */
711 uint pmask11; /* 0x24a68 - Pattern Mask Register */
713 uint pcntrl11; /* 0x24a70 - Pattern Match Control Register */
715 uint pattrb11; /* 0x24a78 - Pattern Match Attributes Register */
716 uint pattrbeli11; /* 0x24a7c - Pattern Match Attributes Extract Length and Extract Index Register */
717 uint pmd12; /* 0x24a80 - Pattern Match Data Register */
719 uint pmask12; /* 0x24a88 - Pattern Mask Register */
721 uint pcntrl12; /* 0x24a90 - Pattern Match Control Register */
723 uint pattrb12; /* 0x24a98 - Pattern Match Attributes Register */
724 uint pattrbeli12; /* 0x24a9c - Pattern Match Attributes Extract Length and Extract Index Register */
725 uint pmd13; /* 0x24aa0 - Pattern Match Data Register */
727 uint pmask13; /* 0x24aa8 - Pattern Mask Register */
729 uint pcntrl13; /* 0x24ab0 - Pattern Match Control Register */
731 uint pattrb13; /* 0x24ab8 - Pattern Match Attributes Register */
732 uint pattrbeli13; /* 0x24abc - Pattern Match Attributes Extract Length and Extract Index Register */
733 uint pmd14; /* 0x24ac0 - Pattern Match Data Register */
735 uint pmask14; /* 0x24ac8 - Pattern Mask Register */
737 uint pcntrl14; /* 0x24ad0 - Pattern Match Control Register */
739 uint pattrb14; /* 0x24ad8 - Pattern Match Attributes Register */
740 uint pattrbeli14; /* 0x24adc - Pattern Match Attributes Extract Length and Extract Index Register */
741 uint pmd15; /* 0x24ae0 - Pattern Match Data Register */
743 uint pmask15; /* 0x24ae8 - Pattern Mask Register */
745 uint pcntrl15; /* 0x24af0 - Pattern Match Control Register */
747 uint pattrb15; /* 0x24af8 - Pattern Match Attributes Register */
748 uint pattrbeli15; /* 0x24afc - Pattern Match Attributes Extract Length and Extract Index Register */
750 uint attr; /* 0x24bf8 - Attributes Register */
751 uint attreli; /* 0x24bfc - Attributes Extract Length and Extract Index Register */
756 * PIC Registers(0x4_0000-0x8_0000)
758 typedef struct ccsr_pic {
759 char res1[64]; /* 0x40000 */
760 uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
762 uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
764 uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */
766 uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */
768 uint ctpr; /* 0x40080 - Current Task Priority Register */
770 uint whoami; /* 0x40090 - Who Am I Register */
772 uint iack; /* 0x400a0 - Interrupt Acknowledge Register */
774 uint eoi; /* 0x400b0 - End Of Interrupt Register */
776 uint frr; /* 0x41000 - Feature Reporting Register */
778 uint gcr; /* 0x41020 - Global Configuration Register */
779 #define MPC85xx_PICGCR_RST 0x80000000
780 #define MPC85xx_PICGCR_M 0x20000000
782 uint vir; /* 0x41080 - Vendor Identification Register */
784 uint pir; /* 0x41090 - Processor Initialization Register */
786 uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */
788 uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */
790 uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */
792 uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */
794 uint svr; /* 0x410e0 - Spurious Vector Register */
796 uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */
798 uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */
800 uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */
802 uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */
804 uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */
806 uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */
808 uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */
810 uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */
812 uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */
814 uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */
816 uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */
818 uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */
820 uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */
822 uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */
824 uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */
826 uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */
828 uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */
830 uint tcr; /* 0x41300 - Timer Control Register */
832 uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */
834 uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */
836 uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */
838 uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */
840 uint msgr0; /* 0x41400 - Message Register 0 */
842 uint msgr1; /* 0x41410 - Message Register 1 */
844 uint msgr2; /* 0x41420 - Message Register 2 */
846 uint msgr3; /* 0x41430 - Message Register 3 */
848 uint mer; /* 0x41500 - Message Enable Register */
850 uint msr; /* 0x41510 - Message Status Register */
852 uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */
854 uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */
856 uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */
858 uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */
860 uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */
862 uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */
864 uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */
866 uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */
868 uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */
870 uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */
872 uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */
874 uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */
876 uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */
878 uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */
880 uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */
882 uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */
884 uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */
886 uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */
888 uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */
890 uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */
892 uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */
894 uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */
896 uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */
898 uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */
900 uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
902 uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */
904 uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
906 uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */
908 uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
910 uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */
912 uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
914 uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */
916 uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
918 uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */
920 uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
922 uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */
924 uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
926 uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */
928 uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
930 uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */
932 uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
934 uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */
936 uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
938 uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */
940 uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
942 uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */
944 uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
946 uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */
948 uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
950 uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */
952 uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
954 uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */
956 uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
958 uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */
960 uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
962 uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */
964 uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
966 uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */
968 uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
970 uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */
972 uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
974 uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */
976 uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
978 uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */
980 uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
982 uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */
984 uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
986 uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */
988 uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
990 uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */
992 uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
994 uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */
996 uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
998 uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */
1000 uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
1002 uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */
1004 uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
1006 uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */
1008 uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
1010 uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */
1012 uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
1014 uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */
1016 uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
1018 uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */
1020 uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
1022 uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */
1024 uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
1026 uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */
1028 uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
1030 uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */
1032 uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
1034 uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */
1036 uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
1038 uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */
1040 uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */
1042 uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */
1044 uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */
1046 uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */
1048 uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */
1050 uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */
1052 uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */
1054 uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */
1056 uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */
1058 uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */
1059 char res150[130892];
1063 * CPM Block(0x8_0000-0xc_0000)
1066 typedef struct ccsr_cpm {
1071 * 0x8000-0x8ffff:DPARM
1072 * 0x9000-0x90bff: General SIU
1074 typedef struct ccsr_cpm_siu {
1086 /* 0x90c00-0x90cff: Interrupt Controller */
1087 typedef struct ccsr_cpm_intctl {
1102 } ccsr_cpm_intctl_t;
1104 /* 0x90d00-0x90d7f: input/output port */
1105 typedef struct ccsr_cpm_iop {
1132 /* 0x90d80-0x91017: CPM timers */
1133 typedef struct ccsr_cpm_timer {
1161 /* 0x91018-0x912ff: SDMA */
1162 typedef struct ccsr_cpm_sdma {
1169 /* 0x91300-0x9131f: FCC1 */
1170 typedef struct ccsr_cpm_fcc1 {
1183 u_char ftirr_phy[4];
1186 /* 0x91320-0x9133f: FCC2 */
1187 typedef struct ccsr_cpm_fcc2 {
1200 u_char ftirr_phy[4];
1203 /* 0x91340-0x9137f: FCC3 */
1204 typedef struct ccsr_cpm_fcc3 {
1220 /* 0x91380-0x9139f: FCC1 extended */
1221 typedef struct ccsr_cpm_fcc1_ext {
1229 } ccsr_cpm_fcc1_ext_t;
1231 /* 0x913a0-0x913cf: FCC2 extended */
1232 typedef struct ccsr_cpm_fcc2_ext {
1239 } ccsr_cpm_fcc2_ext_t;
1241 /* 0x913d0-0x913ff: FCC3 extended */
1242 typedef struct ccsr_cpm_fcc3_ext {
1245 } ccsr_cpm_fcc3_ext_t;
1247 /* 0x91400-0x915ef: TC layers */
1248 typedef struct ccsr_cpm_tmp1 {
1252 /* 0x915f0-0x9185f: BRGs:5,6,7,8 */
1253 typedef struct ccsr_cpm_brg2 {
1261 /* 0x91860-0x919bf: I2C */
1262 typedef struct ccsr_cpm_i2c {
1277 /* 0x919c0-0x919ef: CPM core */
1278 typedef struct ccsr_cpm_cp {
1291 /* 0x919f0-0x919ff: BRGs:1,2,3,4 */
1292 typedef struct ccsr_cpm_brg1 {
1299 /* 0x91a00-0x91a9f: SCC1-SCC4 */
1300 typedef struct ccsr_cpm_scc {
1315 /* 0x91a80-0x91a9f */
1316 typedef struct ccsr_cpm_tmp2 {
1320 /* 0x91aa0-0x91aff: SPI */
1321 typedef struct ccsr_cpm_spi {
1332 /* 0x91b00-0x91b1f: CPM MUX */
1333 typedef struct ccsr_cpm_mux {
1345 /* 0x91b20-0xbffff: SI,MCC,etc */
1346 typedef struct ccsr_cpm_tmp3 {
1350 typedef struct ccsr_cpm_iram {
1351 unsigned long iram[8192];
1355 typedef struct ccsr_cpm {
1356 /* Some references are into the unique and known dpram spaces,
1357 * others are from the generic base.
1359 #define im_dprambase im_dpram1
1360 u_char im_dpram1[16*1024];
1362 u_char im_dpram2[16*1024];
1364 ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
1365 ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */
1366 ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
1367 ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
1368 ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
1369 ccsr_cpm_fcc1_t im_cpm_fcc1;
1370 ccsr_cpm_fcc2_t im_cpm_fcc2;
1371 ccsr_cpm_fcc3_t im_cpm_fcc3;
1372 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext;
1373 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext;
1374 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext;
1375 ccsr_cpm_tmp1_t im_cpm_tmp1;
1376 ccsr_cpm_brg2_t im_cpm_brg2;
1377 ccsr_cpm_i2c_t im_cpm_i2c;
1378 ccsr_cpm_cp_t im_cpm_cp;
1379 ccsr_cpm_brg1_t im_cpm_brg1;
1380 ccsr_cpm_scc_t im_cpm_scc[4];
1381 ccsr_cpm_tmp2_t im_cpm_tmp2;
1382 ccsr_cpm_spi_t im_cpm_spi;
1383 ccsr_cpm_mux_t im_cpm_mux;
1384 ccsr_cpm_tmp3_t im_cpm_tmp3;
1385 ccsr_cpm_iram_t im_cpm_iram;
1390 * RapidIO Registers(0xc_0000-0xe_0000)
1392 typedef struct ccsr_rio {
1393 uint didcar; /* 0xc0000 - Device Identity Capability Register */
1394 uint dicar; /* 0xc0004 - Device Information Capability Register */
1395 uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */
1396 uint aicar; /* 0xc000c - Assembly Information Capability Register */
1397 uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */
1398 uint spicar; /* 0xc0014 - Switch Port Information Capability Register */
1399 uint socar; /* 0xc0018 - Source Operations Capability Register */
1400 uint docar; /* 0xc001c - Destination Operations Capability Register */
1402 uint msr; /* 0xc0040 - Mailbox Command And Status Register */
1403 uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */
1405 uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
1407 uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */
1408 uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */
1410 uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */
1411 uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */
1413 uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
1415 uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */
1416 uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */
1418 uint pgccsr; /* 0xc013c - Port General Command and Status Register */
1419 uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */
1420 uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */
1421 uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */
1423 uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */
1424 uint pccsr; /* 0xc015c - Port Control Command and Status Register */
1426 uint cr; /* 0xd0000 - Port Control Command and Status Register */
1428 uint pcr; /* 0xd0010 - Port Configuration Register */
1429 uint peir; /* 0xd0014 - Port Error Injection Register */
1431 uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
1433 uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
1435 uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
1437 uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
1439 uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
1441 uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
1443 uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
1445 uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
1447 uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
1449 uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
1451 uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
1453 uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
1455 uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
1457 uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
1459 uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
1461 uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
1463 uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
1465 uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
1467 uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
1469 uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
1471 uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
1473 uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
1475 uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
1477 uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
1479 uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
1481 uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
1483 uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
1485 uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
1487 uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
1489 uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
1491 uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
1493 uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
1495 uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
1497 uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
1499 uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
1501 uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
1503 uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
1505 uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
1507 uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
1509 uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
1511 uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */
1512 uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */
1513 uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
1514 uint pecr; /* 0xd0e0c - Port Error Control Register */
1515 uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
1516 uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */
1517 uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */
1519 uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */
1521 uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */
1522 uint prtr; /* 0xd0e2c - Port Retry Threshold Register */
1524 uint omr; /* 0xd1000 - Outbound Mode Register */
1525 uint osr; /* 0xd1004 - Outbound Status Register */
1526 uint eodqtpar; /* 0xd1008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
1527 uint odqtpar; /* 0xd100c - Outbound Descriptor Queue Tail Pointer Address Register */
1528 uint eosar; /* 0xd1010 - Extended Outbound Unit Source Address Register */
1529 uint osar; /* 0xd1014 - Outbound Unit Source Address Register */
1530 uint odpr; /* 0xd1018 - Outbound Destination Port Register */
1531 uint odatr; /* 0xd101c - Outbound Destination Attributes Register */
1532 uint odcr; /* 0xd1020 - Outbound Doubleword Count Register */
1533 uint eodqhpar; /* 0xd1024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
1534 uint odqhpar; /* 0xd1028 - Outbound Descriptor Queue Head Pointer Address Register */
1536 uint imr; /* 0xd1060 - Outbound Mode Register */
1537 uint isr; /* 0xd1064 - Inbound Status Register */
1538 uint eidqtpar; /* 0xd1068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
1539 uint idqtpar; /* 0xd106c - Inbound Descriptor Queue Tail Pointer Address Register */
1540 uint eifqhpar; /* 0xd1070 - Extended Inbound Frame Queue Head Pointer Address Register */
1541 uint ifqhpar; /* 0xd1074 - Inbound Frame Queue Head Pointer Address Register */
1543 uint dmr; /* 0xd1460 - Doorbell Mode Register */
1544 uint dsr; /* 0xd1464 - Doorbell Status Register */
1545 uint edqtpar; /* 0xd1468 - Extended Doorbell Queue Tail Pointer Address Register */
1546 uint dqtpar; /* 0xd146c - Doorbell Queue Tail Pointer Address Register */
1547 uint edqhpar; /* 0xd1470 - Extended Doorbell Queue Head Pointer Address Register */
1548 uint dqhpar; /* 0xd1474 - Doorbell Queue Head Pointer Address Register */
1550 uint pwmr; /* 0xd14e0 - Port-Write Mode Register */
1551 uint pwsr; /* 0xd14e4 - Port-Write Status Register */
1552 uint epwqbar; /* 0xd14e8 - Extended Port-Write Queue Base Address Register */
1553 uint pwqbar; /* 0xd14ec - Port-Write Queue Base Address Register */
1557 /* Quick Engine Block Pin Muxing Registers (0xe_0100 - 0xe_01bf) */
1558 typedef struct par_io {
1559 uint cpodr; /* 0x100 */
1560 uint cpdat; /* 0x104 */
1561 uint cpdir1; /* 0x108 */
1562 uint cpdir2; /* 0x10c */
1563 uint cppar1; /* 0x110 */
1564 uint cppar2; /* 0x114 */
1569 * Global Utilities Register Block(0xe_0000-0xf_ffff)
1571 #ifdef CONFIG_FSL_CORENET
1572 typedef struct ccsr_gur {
1573 u32 porsr1; /* 0xe0000 - POR status register */
1574 u8 res1[28]; /* 0xe0004 - 0xe001c Reserved: PORSRn */
1575 u32 gpporcr1; /* 0xe0020 - General-purpose POR configuration register */
1577 u32 gpiocr; /* 0xe0030 - GPIO control register */
1579 u32 gpoutdr; /* 0xe0040 - General-purpose output data register */
1581 u32 gpindr; /* 0xe0050 - General-purpose input data register */
1583 u32 pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
1585 u32 devdisr; /* 0xe0070 - Device disable control */
1586 #define FSL_CORENET_DEVDISR_PCIE1 0x80000000
1587 #define FSL_CORENET_DEVDISR_PCIE2 0x40000000
1588 #define FSL_CORENET_DEVDISR_PCIE3 0x20000000
1589 #define FSL_CORENET_DEVDISR_RMU 0x08000000
1590 #define FSL_CORENET_DEVDISR_SRIO1 0x04000000
1591 #define FSL_CORENET_DEVDISR_SRIO2 0x02000000
1592 #define FSL_CORENET_DEVDISR_DMA1 0x00400000
1593 #define FSL_CORENET_DEVDISR_DMA2 0x00200000
1594 #define FSL_CORENET_DEVDISR_DDR1 0x00100000
1595 #define FSL_CORENET_DEVDISR_DDR2 0x00080000
1596 #define FSL_CORENET_DEVDISR_DBG 0x00010000
1597 #define FSL_CORENET_DEVDISR_NAL 0x00008000
1598 #define FSL_CORENET_DEVDISR_ELBC 0x00001000
1599 #define FSL_CORENET_DEVDISR_USB1 0x00000800
1600 #define FSL_CORENET_DEVDISR_USB2 0x00000400
1601 #define FSL_CORENET_DEVDISR_ESDHC 0x00000100
1602 #define FSL_CORENET_DEVDISR_GPIO 0x00000080
1603 #define FSL_CORENET_DEVDISR_ESPI 0x00000040
1604 #define FSL_CORENET_DEVDISR_I2C1 0x00000020
1605 #define FSL_CORENET_DEVDISR_I2C2 0x00000010
1606 #define FSL_CORENET_DEVDISR_DUART1 0x00000002
1607 #define FSL_CORENET_DEVDISR_DUART2 0x00000001
1609 u32 powmgtcsr; /* 0xe0080 - Power management status and control register */
1611 u32 coredisru; /* 0xe0090 - uppper portion for support of 64 cores */
1612 u32 coredisrl; /* 0xe0094 - lower portion for support of 64 cores */
1614 u32 pvr; /* 0xe00a0 - Processor version register */
1615 u32 svr; /* 0xe00a4 - System version register */
1617 u32 rstcr; /* 0xe00b0 - Reset control register */
1618 u32 rstrqpblsr; /* 0xe00b4 - Reset request preboot loader status register */
1620 u32 rstrqmr1; /* 0xe00c0 - Reset request mask register */
1621 u8 res12[4]; /* Reserved: RSTRQMR2 */
1622 u32 rstrqsr1; /* 0xe00c8 - Reset request status register */
1623 u8 res13[4]; /* Reserved: RSTRQSR2 */
1624 u8 res14[4]; /* Reserved: RSTRQWDTMRU */
1625 u32 rstrqwdtmrl; /* 0xe00d4 - Reset request WDT mask register */
1626 u8 res15[4]; /* Reserved: RSTRQWDTSRU */
1627 u32 rstrqwdtsrl; /* 0xe00dc - Reset request WDT status register */
1628 u8 res16[4]; /* Reserved: BRRU max total of 2 for up to 64 cores */
1629 u32 brrl; /* 0xe00e4 Boot release register */
1631 u32 rcwsr[16]; /* 0xe0100 - 0xe013c: Reset control word status register */
1632 #define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
1633 #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00008000
1634 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 15
1635 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
1636 #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
1637 #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
1638 u8 res18[192]; /* Reserved: RCWSRn (max total of 64)*/
1639 u32 scratchrw[4]; /* 0xe0200 - 0xe020c: Scratch Read/Write register */
1640 u8 res19[240]; /* Reserved: SCRATCHRWn (max total of 64)*/
1641 u32 scratchw1r[4]; /* 0xe0300 - 0xe030c: Scratch Read register (Write once) */
1642 u8 res20[240]; /* Reserved: SCRATCHW1Rn (max total of 64)*/
1643 u32 scrtsr[8]; /* 0xe0400 - 0xe041c: Core reset status register */
1644 u8 res21[224]; /* Reserved: CRSTSRn (max total of 64 for up to 64 cores)*/
1645 u32 pex1liodnr; /* 0xe0500 PCI Express 1 Logical I/O Device Number register*/
1646 u32 pex2liodnr; /* 0xe0504 PCI Express 2 Logical I/O Device Number register*/
1647 u32 pex3liodnr; /* 0xe0508 PCI Express 3 Logical I/O Device Number register*/
1648 u32 pex4liodnr; /* 0xe050c PCI Express 4 Logical I/O Device Number register*/
1649 u32 rio1liodnr; /* 0xe0510 RIO 1 Logical I/O Device Number register*/
1650 u32 rio2liodnr; /* 0xe0514 RIO 2 Logical I/O Device Number register*/
1651 u32 rio3liodnr; /* 0xe0518 RIO 3 Logical I/O Device Number register*/
1652 u32 rio4liodnr; /* 0xe051c RIO 4 Logical I/O Device Number register*/
1653 u32 usb1liodnr; /* 0xe0520 USB 1 Logical I/O Device Number register*/
1654 u32 usb2liodnr; /* 0xe0524 USB 2 Logical I/O Device Number register*/
1655 u32 usb3liodnr; /* 0xe0528 USB 3 Logical I/O Device Number register*/
1656 u32 usb4liodnr; /* 0xe052c USB 4 Logical I/O Device Number register*/
1657 u32 sdmmc1liodnr; /* 0xe0530 SD/MMC 1 Logical I/O Device Number register*/
1658 u32 sdmmc2liodnr; /* 0xe0534 SD/MMC 2 Logical I/O Device Number register*/
1659 u32 sdmmc3liodnr; /* 0xe0538 SD/MMC 3 Logical I/O Device Number register*/
1660 u32 sdmmc4liodnr; /* 0xe053c SD/MMC 4 Logical I/O Device Number register*/
1661 u32 rmuliodnr; /* 0xe0540 RIO Message Unit Logical I/O Device Number register*/
1662 u32 rduliodnr; /* 0xe0544 RIO Doorbell Unit Logical I/O Device Number register*/
1663 u32 rpwuliodnr; /* 0xe0548 RIO Port Write Unit Logical I/O Device Number register*/
1664 u8 res22[52]; /* Reserved: for future LIODN register expansion */
1665 u32 dma1liodnr; /* 0xe0580 DMA 1 Logical I/O Device Number register*/
1666 u32 dma2liodnr; /* 0xe0584 DMA 2 Logical I/O Device Number register*/
1667 u32 dma3liodnr; /* 0xe0588 DMA 3 Logical I/O Device Number register*/
1668 u32 dma4liodnr; /* 0xe058c DMA 4 Logical I/O Device Number register*/
1669 u8 res23[48]; /* Reserved: for future LIODN register expansion */
1670 u8 res24[64]; /* Reserved */
1671 u32 pblsr; /* 0xe0600 Preboot loader status register*/
1672 u32 pamubypenr; /* 0xe0604 PAMU bypass enable register*/
1673 u32 dmacr1; /* 0xe0608 DMA control register*/
1674 u8 res25[4]; /* Reserved: DMACR2 (max total of 2)*/
1675 u32 gensr1; /* 0xe0610 General status register*/
1676 u8 res26[12]; /* Reserved: GENSRn (max total of 4)*/
1677 u32 gencr1; /* 0xe0620 General control register*/
1678 u8 res27[12]; /* Reserved: GENCRn (max total of 4)*/
1679 u8 res28[4]; /* Reserved: CGENSRU (upper portion for support of 64 cores) */
1680 u32 cgensrl; /* 0xe0634 Core general status register*/
1681 u8 res29[8]; /* Reserved */
1682 u8 res30[4]; /* Reserved: CGENCRU (upper portion for support of 64 cores) */
1683 u32 cgencrl; /* 0xe0634 Core general control register*/
1684 u8 res31[184]; /* Reserved 0xe0648 - 0xe06fc */
1685 u32 sriopstecr; /* 0xe0700 SRIO prescaler timer enable control register*/
1686 u8 res32[2300]; /* Reserved 0xe0704 - 0xe0ffc */
1689 typedef struct ccsr_clk {
1690 u32 clkc0csr; /* 0xe1000 - Core 0 Clock control/status register */
1692 u32 clkc1csr; /* 0xe1020 - Core 1 Clock control/status register */
1694 u32 clkc2csr; /* 0xe1040 - Core 2 Clock control/status register */
1696 u32 clkc3csr; /* 0xe1060 - Core 3 Clock control/status register */
1698 u32 clkc4csr; /* 0xe1080 - Core 4 Clock control/status register */
1700 u32 clkc5csr; /* 0xe10a0 - Core 5 Clock control/status register */
1702 u32 clkc6csr; /* 0xe10c0 - Core 6 Clock control/status register */
1704 u32 clkc7csr; /* 0xe10e0 - Core 7 Clock control/status register */
1706 u32 pllc1gsr; /* 0xe1800 - Cluster PLL 1 General Status Register */
1708 u32 pllc2gsr; /* 0xe1820 - Cluster PLL 2 General Status Register */
1710 u32 pllc3gsr; /* 0xe1840 - Cluster PLL 3 General Status Register */
1712 u32 pllc4gsr; /* 0xe1860 - Cluster PLL 4 General Status Register */
1714 u32 pllpgsr; /* 0xe1c00 - Platform PLL General Status Register */
1716 u32 plldgsr; /* 0xe1c20 - DDR PLL General Status Register */
1720 typedef struct ccsr_rcpm {
1721 u8 res1[4]; /* 0xe2000 - Reserved */
1722 u32 cdozsrl; /* 0xe2004 - Core Doze Status Register */
1723 u8 res2[4]; /* 0xe2008 - Reserved */
1724 u32 cdozcrl; /* 0xe200c - Core Doze Control Register */
1725 u8 res3[4]; /* 0xe2010 - Reserved */
1726 u32 cnapsrl; /* 0xe2014 - Core Nap Status Register */
1727 u8 res4[4]; /* 0xe2018 - Reserved */
1728 u32 cnapcrl; /* 0xe201c - Core Nap Control Register */
1729 u8 res5[4]; /* 0xe2020 - Reserved */
1730 u32 cdozpsrl; /* 0xe2024 - Core Doze Previous Status Register */
1731 u8 res6[4]; /* 0xe2028 - Reserved */
1732 u32 cdozpcrl; /* 0xe202c - Core Doze Previous Control Register */
1733 u8 res7[4]; /* 0xe2030 - Reserved */
1734 u32 cwaitsrl; /* 0xe2034 - Core Wait Status Register */
1735 u8 res8[8]; /* Reserved */
1736 u32 powmgtcsr; /* 0xe2040 - Power Mangement Control & Status Register */
1737 u8 res9[12]; /* Reserved */
1738 u32 ippdexpcr0; /* 0xe2050 - IP Powerdown Exception Control Register 0 */
1739 u8 res10[12]; /* Reserved */
1740 u8 res11[4]; /* Reserved */
1741 u32 cpmimrl; /* 0xe2064 - Core Power Management Interrupt Masking Register */
1742 u8 res12[4]; /* Reserved */
1743 u32 cpmcimrl; /* 0xe206c - Core Power Management Critical Interrupt Masking Register */
1744 u8 res13[4]; /* Reserved */
1745 u32 cpmmcimrl; /* 0xe2074 - Core Power Management Machine Check Interrupt Masking Register */
1746 u8 res14[4]; /* Reserved */
1747 u32 cpmnmimrl; /* 0xe207c - Core Power Management NMI Masking Register */
1748 u8 res15[4]; /* Reserved */
1749 u32 ctbenrl; /* 0xe2084 - Core Time Base Enable Register */
1750 u8 res16[4]; /* Reserved */
1751 u32 ctbclkselrl; /* 0xe208c - Core Time Base Clock Select Register */
1752 u8 res17[4]; /* Reserved */
1753 u32 ctbhltcrl; /* 0xe2094 - Core Time Base Halt Control Register */
1758 typedef struct ccsr_gur {
1759 uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
1760 #ifdef CONFIG_MPC8536
1761 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
1762 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
1764 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
1765 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
1767 #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
1768 #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25
1769 #define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e
1770 #define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1
1771 uint porbmsr; /* 0xe0004 - POR boot mode status register */
1772 #define MPC85xx_PORBMSR_HA 0x00070000
1773 #define MPC85xx_PORBMSR_HA_SHIFT 16
1774 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
1775 uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
1776 #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
1777 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
1778 #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
1779 #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
1780 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
1781 #define MPC85xx_PORDEVSR_PCI1 0x00800000
1782 #define MPC85xx_PORDEVSR_IO_SEL 0x00780000
1783 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
1784 #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
1785 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
1786 #define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
1787 #define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
1788 #define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
1789 #define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
1790 #define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
1791 #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
1792 uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
1793 uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */
1794 /* The 8544 RM says this is bit 26, but it's really bit 24 */
1795 #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
1797 uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
1799 uint gpiocr; /* 0xe0030 - GPIO control register */
1801 #if defined(CONFIG_MPC8569)
1803 /* 0xe0040 - Platform port pin assignment register 1 */
1805 /* 0xe0044 - Platform port pin assignment register 2 */
1807 /* 0xe0048 - Platform port pin direction register 1 */
1809 /* 0xe004c - Platform port pin direction register 2 */
1811 uint gpoutdr; /* 0xe0040 - General-purpose output data register */
1814 uint gpindr; /* 0xe0050 - General-purpose input data register */
1816 uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
1817 #define MPC85xx_PMUXCR_SD_DATA 0x80000000
1818 #define MPC85xx_PMUXCR_SDHC_CD 0x40000000
1819 #define MPC85xx_PMUXCR_SDHC_WP 0x20000000
1821 uint devdisr; /* 0xe0070 - Device disable control */
1822 #define MPC85xx_DEVDISR_PCI1 0x80000000
1823 #define MPC85xx_DEVDISR_PCI2 0x40000000
1824 #define MPC85xx_DEVDISR_PCIE 0x20000000
1825 #define MPC85xx_DEVDISR_LBC 0x08000000
1826 #define MPC85xx_DEVDISR_PCIE2 0x04000000
1827 #define MPC85xx_DEVDISR_PCIE3 0x02000000
1828 #define MPC85xx_DEVDISR_SEC 0x01000000
1829 #define MPC85xx_DEVDISR_SRIO 0x00080000
1830 #define MPC85xx_DEVDISR_RMSG 0x00040000
1831 #define MPC85xx_DEVDISR_DDR 0x00010000
1832 #define MPC85xx_DEVDISR_CPU 0x00008000
1833 #define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU
1834 #define MPC85xx_DEVDISR_TB 0x00004000
1835 #define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB
1836 #define MPC85xx_DEVDISR_CPU1 0x00002000
1837 #define MPC85xx_DEVDISR_TB1 0x00001000
1838 #define MPC85xx_DEVDISR_DMA 0x00000400
1839 #define MPC85xx_DEVDISR_TSEC1 0x00000080
1840 #define MPC85xx_DEVDISR_TSEC2 0x00000040
1841 #define MPC85xx_DEVDISR_TSEC3 0x00000020
1842 #define MPC85xx_DEVDISR_TSEC4 0x00000010
1843 #define MPC85xx_DEVDISR_I2C 0x00000004
1844 #define MPC85xx_DEVDISR_DUART 0x00000002
1846 uint powmgtcsr; /* 0xe0080 - Power management status and control register */
1848 uint mcpsumr; /* 0xe0090 - Machine check summary register */
1850 uint pvr; /* 0xe00a0 - Processor version register */
1851 uint svr; /* 0xe00a4 - System version register */
1853 uint rstcr; /* 0xe00b0 - Reset control register */
1854 #if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
1856 par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */
1861 uint clkocr; /* 0xe0e00 - Clock out select register */
1863 uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
1865 uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */
1867 uint lbiuiplldcr0; /* 0xe0f1c -- LBIU PLL Debug Reg 0 */
1868 uint lbiuiplldcr1; /* 0xe0f20 -- LBIU PLL Debug Reg 1 */
1869 uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */
1870 uint tsec12ioovcr; /* 0xe0f28 - eTSEC 1/2 IO override control */
1871 uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */
1872 char res15[61648]; /* 0xe0f30 to 0xefffff */
1876 #ifdef CONFIG_FSL_CORENET
1877 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
1878 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000
1879 #define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000
1880 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
1881 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
1882 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x100000
1883 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
1884 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
1885 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
1886 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
1887 #define CONFIG_SYS_MPC85xx_QMAN_OFFSET 0x318000
1888 #define CONFIG_SYS_MPC85xx_BMAN_OFFSET 0x31a000
1890 #define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
1891 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000
1892 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
1893 #define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x6000
1894 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
1895 #define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
1896 #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
1897 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
1898 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
1899 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
1900 #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
1901 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
1902 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
1903 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
1904 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
1905 #define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000
1908 #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
1909 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
1911 #define CONFIG_SYS_MPC85xx_QMAN_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_QMAN_OFFSET)
1912 #define CONFIG_SYS_MPC85xx_BMAN_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_BMAN_OFFSET)
1913 #define CONFIG_SYS_MPC85xx_GUTS_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
1914 #define CONFIG_SYS_FSL_CORENET_CCM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
1915 #define CONFIG_SYS_FSL_CORENET_CLK_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
1916 #define CONFIG_SYS_FSL_CORENET_RCPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
1917 #define CONFIG_SYS_MPC85xx_ECM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
1918 #define CONFIG_SYS_MPC85xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET)
1919 #define CONFIG_SYS_MPC85xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
1920 #define CONFIG_SYS_MPC85xx_LBC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
1921 #define CONFIG_SYS_MPC85xx_ESPI_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
1922 #define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
1923 #define CONFIG_SYS_MPC85xx_PCIX2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
1924 #define CONFIG_SYS_MPC85xx_GPIO_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
1925 #define CONFIG_SYS_MPC85xx_SATA1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
1926 #define CONFIG_SYS_MPC85xx_SATA2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
1927 #define CONFIG_SYS_MPC85xx_L2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
1928 #define CONFIG_SYS_MPC85xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
1929 #define CONFIG_SYS_MPC85xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
1930 #define CONFIG_SYS_MPC85xx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
1931 #define CONFIG_SYS_MPC85xx_CPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
1932 #define CONFIG_SYS_MPC85xx_SERDES1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
1933 #define CONFIG_SYS_MPC85xx_SERDES2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
1934 #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000
1935 #define CONFIG_SYS_MPC85xx_USB_ADDR \
1936 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
1938 #endif /*__IMMAP_85xx__*/