2 * PowerPC memory management structures
8 #include <linux/config.h>
11 /* Hardware Page Table Entry */
13 #ifdef CONFIG_PPC64BRIDGE
14 unsigned long long vsid:52;
19 unsigned long long rpn:52;
20 #else /* CONFIG_PPC64BRIDGE */
21 unsigned long v:1; /* Entry is valid */
22 unsigned long vsid:24; /* Virtual segment identifier */
23 unsigned long h:1; /* Hash algorithm indicator */
24 unsigned long api:6; /* Abbreviated page index */
25 unsigned long rpn:20; /* Real (physical) page number */
26 #endif /* CONFIG_PPC64BRIDGE */
27 unsigned long :3; /* Unused */
28 unsigned long r:1; /* Referenced */
29 unsigned long c:1; /* Changed */
30 unsigned long w:1; /* Write-thru cache mode */
31 unsigned long i:1; /* Cache inhibited */
32 unsigned long m:1; /* Memory coherence */
33 unsigned long g:1; /* Guarded */
34 unsigned long :1; /* Unused */
35 unsigned long pp:2; /* Page protection */
38 /* Values for PP (assumes Ks=0, Kp=1) */
39 #define PP_RWXX 0 /* Supervisor read/write, User none */
40 #define PP_RWRX 1 /* Supervisor read/write, User read */
41 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
42 #define PP_RXRX 3 /* Supervisor read, User read */
44 /* Segment Register */
45 typedef struct _SEGREG {
46 unsigned long t:1; /* Normal or I/O type */
47 unsigned long ks:1; /* Supervisor 'key' (normally 0) */
48 unsigned long kp:1; /* User 'key' (normally 1) */
49 unsigned long n:1; /* No-execute */
50 unsigned long :4; /* Unused */
51 unsigned long vsid:24; /* Virtual Segment Identifier */
54 /* Block Address Translation (BAT) Registers */
55 typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */
56 unsigned long bepi:15; /* Effective page index (virtual address) */
57 unsigned long :8; /* unused */
59 unsigned long i:1; /* Cache inhibit */
60 unsigned long m:1; /* Memory coherence */
61 unsigned long ks:1; /* Supervisor key (normally 0) */
62 unsigned long kp:1; /* User key (normally 1) */
63 unsigned long pp:2; /* Page access protections */
66 typedef struct _BATU { /* Upper part of BAT (all except 601) */
67 #ifdef CONFIG_PPC64BRIDGE
68 unsigned long long bepi:47;
69 #else /* CONFIG_PPC64BRIDGE */
70 unsigned long bepi:15; /* Effective page index (virtual address) */
71 #endif /* CONFIG_PPC64BRIDGE */
72 unsigned long :4; /* Unused */
73 unsigned long bl:11; /* Block size mask */
74 unsigned long vs:1; /* Supervisor valid */
75 unsigned long vp:1; /* User valid */
78 typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */
79 unsigned long brpn:15; /* Real page index (physical address) */
80 unsigned long :10; /* Unused */
81 unsigned long v:1; /* Valid bit */
82 unsigned long bl:6; /* Block size mask */
85 typedef struct _BATL { /* Lower part of BAT (all except 601) */
86 #ifdef CONFIG_PPC64BRIDGE
87 unsigned long long brpn:47;
88 #else /* CONFIG_PPC64BRIDGE */
89 unsigned long brpn:15; /* Real page index (physical address) */
90 #endif /* CONFIG_PPC64BRIDGE */
91 unsigned long :10; /* Unused */
92 unsigned long w:1; /* Write-thru cache */
93 unsigned long i:1; /* Cache inhibit */
94 unsigned long m:1; /* Memory coherence */
95 unsigned long g:1; /* Guarded (MBZ in IBAT) */
96 unsigned long :1; /* Unused */
97 unsigned long pp:2; /* Page access protections */
100 typedef struct _BAT {
101 BATU batu; /* Upper register */
102 BATL batl; /* Lower register */
105 typedef struct _P601_BAT {
106 P601_BATU batu; /* Upper register */
107 P601_BATL batl; /* Lower register */
111 * Simulated two-level MMU. This structure is used by the kernel
112 * to keep track of MMU mappings and is used to update/maintain
113 * the hardware HASH table which is really a cache of mappings.
115 * The simulated structures mimic the hardware available on other
116 * platforms, notably the 80x86 and 680x0.
119 typedef struct _pte {
120 unsigned long page_num:20;
121 unsigned long flags:12; /* Page flags (some unused bits) */
124 #define PD_SHIFT (10+12) /* Page directory */
125 #define PD_MASK 0x02FF
126 #define PT_SHIFT (12) /* Page Table */
127 #define PT_MASK 0x02FF
128 #define PG_SHIFT (12) /* Page Entry */
133 typedef struct _MMU_context {
134 SEGREG segs[16]; /* Segment registers */
135 pte **pmap; /* Two-level page-map structure */
138 extern void _tlbie(unsigned long va); /* invalidate a TLB entry */
139 extern void _tlbia(void); /* invalidate all TLB entries */
141 #ifdef CONFIG_ADDR_MAP
142 extern void init_addr_map(void);
146 IBAT0 = 0, IBAT1, IBAT2, IBAT3,
147 DBAT0, DBAT1, DBAT2, DBAT3,
148 #ifdef CONFIG_HIGH_BATS
149 IBAT4, IBAT5, IBAT6, IBAT7,
150 DBAT4, DBAT5, DBAT6, DBAT7
154 extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower);
155 extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
156 extern void print_bats(void);
158 #endif /* __ASSEMBLY__ */
160 #define BATU_VS 0x00000002
161 #define BATU_VP 0x00000001
162 #define BATU_INVALID 0x00000000
164 #define BATL_WRITETHROUGH 0x00000040
165 #define BATL_CACHEINHIBIT 0x00000020
166 #define BATL_MEMCOHERENCE 0x00000010
167 #define BATL_GUARDEDSTORAGE 0x00000008
168 #define BATL_NO_ACCESS 0x00000000
170 #define BATL_PP_MSK 0x00000003
171 #define BATL_PP_00 0x00000000 /* No access */
172 #define BATL_PP_01 0x00000001 /* Read-only */
173 #define BATL_PP_10 0x00000002 /* Read-write */
174 #define BATL_PP_11 0x00000003
176 #define BATL_PP_NO_ACCESS BATL_PP_00
177 #define BATL_PP_RO BATL_PP_01
178 #define BATL_PP_RW BATL_PP_10
180 /* BAT Block size values */
181 #define BATU_BL_128K 0x00000000
182 #define BATU_BL_256K 0x00000004
183 #define BATU_BL_512K 0x0000000c
184 #define BATU_BL_1M 0x0000001c
185 #define BATU_BL_2M 0x0000003c
186 #define BATU_BL_4M 0x0000007c
187 #define BATU_BL_8M 0x000000fc
188 #define BATU_BL_16M 0x000001fc
189 #define BATU_BL_32M 0x000003fc
190 #define BATU_BL_64M 0x000007fc
191 #define BATU_BL_128M 0x00000ffc
192 #define BATU_BL_256M 0x00001ffc
194 /* Block lengths for processors that support extended block length */
196 #define BATU_BL_512M 0x00003ffc
197 #define BATU_BL_1G 0x00007ffc
198 #define BATU_BL_2G 0x0000fffc
199 #define BATU_BL_4G 0x0001fffc
200 #define BATU_BL_MAX BATU_BL_4G
202 #define BATU_BL_MAX BATU_BL_256M
205 /* BAT Access Protection */
206 #define BPP_XX 0x00 /* No access */
207 #define BPP_RX 0x01 /* Read only */
208 #define BPP_RW 0x02 /* Read/write */
210 /* Macros to get values from BATs, once data is in the BAT register format */
211 #define BATU_VALID(x) (x & 0x3)
212 #define BATU_VADDR(x) (x & 0xfffe0000)
213 #define BATL_PADDR(x) ((phys_addr_t)((x & 0xfffe0000) \
214 | ((x & 0x0e00ULL) << 24) \
215 | ((x & 0x04ULL) << 30)))
216 #define BATU_SIZE(x) (1UL << (fls((x & BATU_BL_MAX) >> 2) + 17))
218 /* Used to set up SDR1 register */
219 #define HASH_TABLE_SIZE_64K 0x00010000
220 #define HASH_TABLE_SIZE_128K 0x00020000
221 #define HASH_TABLE_SIZE_256K 0x00040000
222 #define HASH_TABLE_SIZE_512K 0x00080000
223 #define HASH_TABLE_SIZE_1M 0x00100000
224 #define HASH_TABLE_SIZE_2M 0x00200000
225 #define HASH_TABLE_SIZE_4M 0x00400000
226 #define HASH_TABLE_MASK_64K 0x000
227 #define HASH_TABLE_MASK_128K 0x001
228 #define HASH_TABLE_MASK_256K 0x003
229 #define HASH_TABLE_MASK_512K 0x007
230 #define HASH_TABLE_MASK_1M 0x00F
231 #define HASH_TABLE_MASK_2M 0x01F
232 #define HASH_TABLE_MASK_4M 0x03F
234 /* Control/status registers for the MPC8xx.
235 * A write operation to these registers causes serialized access.
236 * During software tablewalk, the registers used perform mask/shift-add
237 * operations when written/read. A TLB entry is created when the Mx_RPN
238 * is written, and the contents of several registers are used to
241 #define MI_CTR 784 /* Instruction TLB control register */
242 #define MI_GPM 0x80000000 /* Set domain manager mode */
243 #define MI_PPM 0x40000000 /* Set subpage protection */
244 #define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
245 #define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
246 #define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
247 #define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
248 #define MI_RESETVAL 0x00000000 /* Value of register at reset */
250 /* These are the Ks and Kp from the PowerPC books. For proper operation,
254 #define MI_Ks 0x80000000 /* Should not be set */
255 #define MI_Kp 0x40000000 /* Should always be set */
257 /* The effective page number register. When read, contains the information
258 * about the last instruction TLB miss. When MI_RPN is written, bits in
259 * this register are used to create the TLB entry.
262 #define MI_EPNMASK 0xfffff000 /* Effective page number for entry */
263 #define MI_EVALID 0x00000200 /* Entry is valid */
264 #define MI_ASIDMASK 0x0000000f /* ASID match value */
265 /* Reset value is undefined */
267 /* A "level 1" or "segment" or whatever you want to call it register.
268 * For the instruction TLB, it contains bits that get loaded into the
269 * TLB entry when the MI_RPN is written.
272 #define MI_APG 0x000001e0 /* Access protection group (0) */
273 #define MI_GUARDED 0x00000010 /* Guarded storage */
274 #define MI_PSMASK 0x0000000c /* Mask of page size bits */
275 #define MI_PS8MEG 0x0000000c /* 8M page size */
276 #define MI_PS512K 0x00000004 /* 512K page size */
277 #define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */
278 #define MI_SVALID 0x00000001 /* Segment entry is valid */
279 /* Reset value is undefined */
281 /* Real page number. Defined by the pte. Writing this register
282 * causes a TLB entry to be created for the instruction TLB, using
283 * additional information from the MI_EPN, and MI_TWC registers.
287 /* Define an RPN value for mapping kernel memory to large virtual
288 * pages for boot initialization. This has real page number of 0,
289 * large page size, shared page, cache enabled, and valid.
290 * Also mark all subpages valid and write access.
292 #define MI_BOOTINIT 0x000001fd
294 #define MD_CTR 792 /* Data TLB control register */
295 #define MD_GPM 0x80000000 /* Set domain manager mode */
296 #define MD_PPM 0x40000000 /* Set subpage protection */
297 #define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
298 #define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */
299 #define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */
300 #define MD_TWAM 0x04000000 /* Use 4K page hardware assist */
301 #define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
302 #define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */
303 #define MD_RESETVAL 0x04000000 /* Value of register at reset */
305 #define M_CASID 793 /* Address space ID (context) to match */
306 #define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */
309 /* These are the Ks and Kp from the PowerPC books. For proper operation,
313 #define MD_Ks 0x80000000 /* Should not be set */
314 #define MD_Kp 0x40000000 /* Should always be set */
316 /* The effective page number register. When read, contains the information
317 * about the last instruction TLB miss. When MD_RPN is written, bits in
318 * this register are used to create the TLB entry.
321 #define MD_EPNMASK 0xfffff000 /* Effective page number for entry */
322 #define MD_EVALID 0x00000200 /* Entry is valid */
323 #define MD_ASIDMASK 0x0000000f /* ASID match value */
324 /* Reset value is undefined */
326 /* The pointer to the base address of the first level page table.
327 * During a software tablewalk, reading this register provides the address
328 * of the entry associated with MD_EPN.
331 #define M_L1TB 0xfffff000 /* Level 1 table base address */
332 #define M_L1INDX 0x00000ffc /* Level 1 index, when read */
333 /* Reset value is undefined */
335 /* A "level 1" or "segment" or whatever you want to call it register.
336 * For the data TLB, it contains bits that get loaded into the TLB entry
337 * when the MD_RPN is written. It is also provides the hardware assist
338 * for finding the PTE address during software tablewalk.
341 #define MD_L2TB 0xfffff000 /* Level 2 table base address */
342 #define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */
343 #define MD_APG 0x000001e0 /* Access protection group (0) */
344 #define MD_GUARDED 0x00000010 /* Guarded storage */
345 #define MD_PSMASK 0x0000000c /* Mask of page size bits */
346 #define MD_PS8MEG 0x0000000c /* 8M page size */
347 #define MD_PS512K 0x00000004 /* 512K page size */
348 #define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */
349 #define MD_WT 0x00000002 /* Use writethrough page attribute */
350 #define MD_SVALID 0x00000001 /* Segment entry is valid */
351 /* Reset value is undefined */
354 /* Real page number. Defined by the pte. Writing this register
355 * causes a TLB entry to be created for the data TLB, using
356 * additional information from the MD_EPN, and MD_TWC registers.
360 /* This is a temporary storage register that could be used to save
361 * a processor working register during a tablewalk.
366 * At present, all PowerPC 400-class processors share a similar TLB
367 * architecture. The instruction and data sides share a unified,
368 * 64-entry, fully-associative TLB which is maintained totally under
369 * software control. In addition, the instruction side has a
370 * hardware-managed, 4-entry, fully- associative TLB which serves as a
371 * first level to the shared TLB. These two TLBs are known as the UTLB
372 * and ITLB, respectively.
375 #define PPC4XX_TLB_SIZE 64
378 * TLB entries are defined by a "high" tag portion and a "low" data
379 * portion. On all architectures, the data portion is 32-bits.
381 * TLB entries are managed entirely under software control by reading,
382 * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
390 #define MAS0_TLBSEL_MSK 0x30000000
391 #define MAS0_TLBSEL(x) ((x << 28) & MAS0_TLBSEL_MSK)
392 #define MAS0_ESEL_MSK 0x0FFF0000
393 #define MAS0_ESEL(x) ((x << 16) & MAS0_ESEL_MSK)
394 #define MAS0_NV(x) ((x) & 0x00000FFF)
396 #define MAS1_VALID 0x80000000
397 #define MAS1_IPROT 0x40000000
398 #define MAS1_TID(x) ((x << 16) & 0x3FFF0000)
399 #define MAS1_TS 0x00001000
400 #define MAS1_TSIZE(x) ((x << 8) & 0x00000F00)
402 #define MAS2_EPN 0xFFFFF000
403 #define MAS2_X0 0x00000040
404 #define MAS2_X1 0x00000020
405 #define MAS2_W 0x00000010
406 #define MAS2_I 0x00000008
407 #define MAS2_M 0x00000004
408 #define MAS2_G 0x00000002
409 #define MAS2_E 0x00000001
411 #define MAS3_RPN 0xFFFFF000
412 #define MAS3_U0 0x00000200
413 #define MAS3_U1 0x00000100
414 #define MAS3_U2 0x00000080
415 #define MAS3_U3 0x00000040
416 #define MAS3_UX 0x00000020
417 #define MAS3_SX 0x00000010
418 #define MAS3_UW 0x00000008
419 #define MAS3_SW 0x00000004
420 #define MAS3_UR 0x00000002
421 #define MAS3_SR 0x00000001
423 #define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
424 #define MAS4_TIDDSEL 0x000F0000
425 #define MAS4_TSIZED(x) MAS1_TSIZE(x)
426 #define MAS4_X0D 0x00000040
427 #define MAS4_X1D 0x00000020
428 #define MAS4_WD 0x00000010
429 #define MAS4_ID 0x00000008
430 #define MAS4_MD 0x00000004
431 #define MAS4_GD 0x00000002
432 #define MAS4_ED 0x00000001
434 #define MAS6_SPID0 0x3FFF0000
435 #define MAS6_SPID1 0x00007FFE
436 #define MAS6_SAS 0x00000001
437 #define MAS6_SPID MAS6_SPID0
439 #define MAS7_RPN 0xFFFFFFFF
441 #define FSL_BOOKE_MAS0(tlbsel,esel,nv) \
442 (MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel) | MAS0_NV(nv))
443 #define FSL_BOOKE_MAS1(v,iprot,tid,ts,tsize) \
444 ((((v) << 31) & MAS1_VALID) |\
445 (((iprot) << 30) & MAS1_IPROT) |\
447 (((ts) << 12) & MAS1_TS) |\
449 #define FSL_BOOKE_MAS2(epn, wimge) \
450 (((epn) & MAS3_RPN) | (wimge))
451 #define FSL_BOOKE_MAS3(rpn, user, perms) \
452 (((rpn) & MAS3_RPN) | (user) | (perms))
454 #define BOOKE_PAGESZ_1K 0
455 #define BOOKE_PAGESZ_4K 1
456 #define BOOKE_PAGESZ_16K 2
457 #define BOOKE_PAGESZ_64K 3
458 #define BOOKE_PAGESZ_256K 4
459 #define BOOKE_PAGESZ_1M 5
460 #define BOOKE_PAGESZ_4M 6
461 #define BOOKE_PAGESZ_16M 7
462 #define BOOKE_PAGESZ_64M 8
463 #define BOOKE_PAGESZ_256M 9
464 #define BOOKE_PAGESZ_1G 10
465 #define BOOKE_PAGESZ_4G 11
466 #define BOOKE_PAGESZ_16GB 12
467 #define BOOKE_PAGESZ_64GB 13
468 #define BOOKE_PAGESZ_256GB 14
469 #define BOOKE_PAGESZ_1TB 15
473 extern void set_tlb(u8 tlb, u32 epn, u64 rpn,
475 u8 ts, u8 esel, u8 tsize, u8 iprot);
476 extern void disable_tlb(u8 esel);
477 extern void invalidate_tlb(u8 tlb);
478 extern void init_tlbs(void);
479 extern int find_tlb_idx(void *addr, u8 tlbsel);
481 extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
483 #define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \
484 { .tlb = _tlb, .epn = _epn, .rpn = _rpn, .perms = _perms, \
485 .wimge = _wimge, .ts = _ts, .esel = _esel, .tsize = _sz, .iprot = _iprot }
487 struct fsl_e_tlb_entry {
499 extern struct fsl_e_tlb_entry tlb_table[];
500 extern int num_tlb_entries;
504 #if defined(CONFIG_MPC86xx)
505 #define LAWBAR_BASE_ADDR 0x00FFFFFF
506 #define LAWAR_TRGT_IF 0x01F00000
508 #define LAWBAR_BASE_ADDR 0x000FFFFF
509 #define LAWAR_TRGT_IF 0x00F00000
511 #define LAWAR_EN 0x80000000
512 #define LAWAR_SIZE 0x0000003F
514 #define LAWAR_TRGT_IF_PCI 0x00000000
515 #define LAWAR_TRGT_IF_PCI1 0x00000000
516 #define LAWAR_TRGT_IF_PCIX 0x00000000
517 #define LAWAR_TRGT_IF_PCI2 0x00100000
518 #define LAWAR_TRGT_IF_PCIE1 0x00200000
519 #define LAWAR_TRGT_IF_PCIE2 0x00100000
520 #define LAWAR_TRGT_IF_PCIE3 0x00300000
521 #define LAWAR_TRGT_IF_LBC 0x00400000
522 #define LAWAR_TRGT_IF_CCSR 0x00800000
523 #define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000
524 #define LAWAR_TRGT_IF_RIO 0x00c00000
525 #define LAWAR_TRGT_IF_DDR 0x00f00000
526 #define LAWAR_TRGT_IF_DDR1 0x00f00000
527 #define LAWAR_TRGT_IF_DDR2 0x01600000
529 #define LAWAR_SIZE_BASE 0xa
530 #define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1)
531 #define LAWAR_SIZE_8K (LAWAR_SIZE_BASE+2)
532 #define LAWAR_SIZE_16K (LAWAR_SIZE_BASE+3)
533 #define LAWAR_SIZE_32K (LAWAR_SIZE_BASE+4)
534 #define LAWAR_SIZE_64K (LAWAR_SIZE_BASE+5)
535 #define LAWAR_SIZE_128K (LAWAR_SIZE_BASE+6)
536 #define LAWAR_SIZE_256K (LAWAR_SIZE_BASE+7)
537 #define LAWAR_SIZE_512K (LAWAR_SIZE_BASE+8)
538 #define LAWAR_SIZE_1M (LAWAR_SIZE_BASE+9)
539 #define LAWAR_SIZE_2M (LAWAR_SIZE_BASE+10)
540 #define LAWAR_SIZE_4M (LAWAR_SIZE_BASE+11)
541 #define LAWAR_SIZE_8M (LAWAR_SIZE_BASE+12)
542 #define LAWAR_SIZE_16M (LAWAR_SIZE_BASE+13)
543 #define LAWAR_SIZE_32M (LAWAR_SIZE_BASE+14)
544 #define LAWAR_SIZE_64M (LAWAR_SIZE_BASE+15)
545 #define LAWAR_SIZE_128M (LAWAR_SIZE_BASE+16)
546 #define LAWAR_SIZE_256M (LAWAR_SIZE_BASE+17)
547 #define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18)
548 #define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19)
549 #define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20)
550 #define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21)
551 #define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22)
552 #define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23)
553 #define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24)
557 #define TLB_VALID 0x00000200
559 /* Supported page sizes */
561 #define SZ_1K 0x00000000
562 #define SZ_4K 0x00000010
563 #define SZ_16K 0x00000020
564 #define SZ_64K 0x00000030
565 #define SZ_256K 0x00000040
566 #define SZ_1M 0x00000050
567 #define SZ_16M 0x00000070
568 #define SZ_256M 0x00000090
570 /* Storage attributes */
571 #define SA_W 0x00000800 /* Write-through */
572 #define SA_I 0x00000400 /* Caching inhibited */
573 #define SA_M 0x00000200 /* Memory coherence */
574 #define SA_G 0x00000100 /* Guarded */
575 #define SA_E 0x00000080 /* Endian */
578 #define AC_X 0x00000024 /* Execute */
579 #define AC_W 0x00000012 /* Write */
580 #define AC_R 0x00000009 /* Read */
582 /* Some handy macros */
584 #define EPN(e) ((e) & 0xfffffc00)
585 #define TLB0(epn,sz) ((EPN((epn)) | (sz) | TLB_VALID ))
586 #define TLB1(rpn,erpn) (((rpn) & 0xfffffc00) | (erpn))
587 #define TLB2(a) ((a) & 0x00000fbf)
589 #define tlbtab_start\
599 #define tlbentry(epn,sz,rpn,erpn,attr)\
600 .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
602 /*----------------------------------------------------------------------------+
603 | TLB specific defines.
604 +----------------------------------------------------------------------------*/
605 #define TLB_256MB_ALIGN_MASK 0xFF0000000ULL
606 #define TLB_16MB_ALIGN_MASK 0xFFF000000ULL
607 #define TLB_1MB_ALIGN_MASK 0xFFFF00000ULL
608 #define TLB_256KB_ALIGN_MASK 0xFFFFC0000ULL
609 #define TLB_64KB_ALIGN_MASK 0xFFFFF0000ULL
610 #define TLB_16KB_ALIGN_MASK 0xFFFFFC000ULL
611 #define TLB_4KB_ALIGN_MASK 0xFFFFFF000ULL
612 #define TLB_1KB_ALIGN_MASK 0xFFFFFFC00ULL
613 #define TLB_256MB_SIZE 0x10000000
614 #define TLB_16MB_SIZE 0x01000000
615 #define TLB_1MB_SIZE 0x00100000
616 #define TLB_256KB_SIZE 0x00040000
617 #define TLB_64KB_SIZE 0x00010000
618 #define TLB_16KB_SIZE 0x00004000
619 #define TLB_4KB_SIZE 0x00001000
620 #define TLB_1KB_SIZE 0x00000400
622 #define TLB_WORD0_EPN_MASK 0xFFFFFC00
623 #define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
624 #define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
625 #define TLB_WORD0_V_MASK 0x00000200
626 #define TLB_WORD0_V_ENABLE 0x00000200
627 #define TLB_WORD0_V_DISABLE 0x00000000
628 #define TLB_WORD0_TS_MASK 0x00000100
629 #define TLB_WORD0_TS_1 0x00000100
630 #define TLB_WORD0_TS_0 0x00000000
631 #define TLB_WORD0_SIZE_MASK 0x000000F0
632 #define TLB_WORD0_SIZE_1KB 0x00000000
633 #define TLB_WORD0_SIZE_4KB 0x00000010
634 #define TLB_WORD0_SIZE_16KB 0x00000020
635 #define TLB_WORD0_SIZE_64KB 0x00000030
636 #define TLB_WORD0_SIZE_256KB 0x00000040
637 #define TLB_WORD0_SIZE_1MB 0x00000050
638 #define TLB_WORD0_SIZE_16MB 0x00000070
639 #define TLB_WORD0_SIZE_256MB 0x00000090
640 #define TLB_WORD0_TPAR_MASK 0x0000000F
641 #define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
642 #define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
644 #define TLB_WORD1_RPN_MASK 0xFFFFFC00
645 #define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
646 #define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
647 #define TLB_WORD1_PAR1_MASK 0x00000300
648 #define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
649 #define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
650 #define TLB_WORD1_PAR1_0 0x00000000
651 #define TLB_WORD1_PAR1_1 0x00000100
652 #define TLB_WORD1_PAR1_2 0x00000200
653 #define TLB_WORD1_PAR1_3 0x00000300
654 #define TLB_WORD1_ERPN_MASK 0x0000000F
655 #define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
656 #define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
658 #define TLB_WORD2_PAR2_MASK 0xC0000000
659 #define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30)
660 #define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03)
661 #define TLB_WORD2_PAR2_0 0x00000000
662 #define TLB_WORD2_PAR2_1 0x40000000
663 #define TLB_WORD2_PAR2_2 0x80000000
664 #define TLB_WORD2_PAR2_3 0xC0000000
665 #define TLB_WORD2_U0_MASK 0x00008000
666 #define TLB_WORD2_U0_ENABLE 0x00008000
667 #define TLB_WORD2_U0_DISABLE 0x00000000
668 #define TLB_WORD2_U1_MASK 0x00004000
669 #define TLB_WORD2_U1_ENABLE 0x00004000
670 #define TLB_WORD2_U1_DISABLE 0x00000000
671 #define TLB_WORD2_U2_MASK 0x00002000
672 #define TLB_WORD2_U2_ENABLE 0x00002000
673 #define TLB_WORD2_U2_DISABLE 0x00000000
674 #define TLB_WORD2_U3_MASK 0x00001000
675 #define TLB_WORD2_U3_ENABLE 0x00001000
676 #define TLB_WORD2_U3_DISABLE 0x00000000
677 #define TLB_WORD2_W_MASK 0x00000800
678 #define TLB_WORD2_W_ENABLE 0x00000800
679 #define TLB_WORD2_W_DISABLE 0x00000000
680 #define TLB_WORD2_I_MASK 0x00000400
681 #define TLB_WORD2_I_ENABLE 0x00000400
682 #define TLB_WORD2_I_DISABLE 0x00000000
683 #define TLB_WORD2_M_MASK 0x00000200
684 #define TLB_WORD2_M_ENABLE 0x00000200
685 #define TLB_WORD2_M_DISABLE 0x00000000
686 #define TLB_WORD2_G_MASK 0x00000100
687 #define TLB_WORD2_G_ENABLE 0x00000100
688 #define TLB_WORD2_G_DISABLE 0x00000000
689 #define TLB_WORD2_E_MASK 0x00000080
690 #define TLB_WORD2_E_ENABLE 0x00000080
691 #define TLB_WORD2_E_DISABLE 0x00000000
692 #define TLB_WORD2_UX_MASK 0x00000020
693 #define TLB_WORD2_UX_ENABLE 0x00000020
694 #define TLB_WORD2_UX_DISABLE 0x00000000
695 #define TLB_WORD2_UW_MASK 0x00000010
696 #define TLB_WORD2_UW_ENABLE 0x00000010
697 #define TLB_WORD2_UW_DISABLE 0x00000000
698 #define TLB_WORD2_UR_MASK 0x00000008
699 #define TLB_WORD2_UR_ENABLE 0x00000008
700 #define TLB_WORD2_UR_DISABLE 0x00000000
701 #define TLB_WORD2_SX_MASK 0x00000004
702 #define TLB_WORD2_SX_ENABLE 0x00000004
703 #define TLB_WORD2_SX_DISABLE 0x00000000
704 #define TLB_WORD2_SW_MASK 0x00000002
705 #define TLB_WORD2_SW_ENABLE 0x00000002
706 #define TLB_WORD2_SW_DISABLE 0x00000000
707 #define TLB_WORD2_SR_MASK 0x00000001
708 #define TLB_WORD2_SR_ENABLE 0x00000001
709 #define TLB_WORD2_SR_DISABLE 0x00000000
711 /*----------------------------------------------------------------------------+
712 | Following instructions are not available in Book E mode of the GNU assembler.
713 +----------------------------------------------------------------------------*/
714 #define DCCCI(ra,rb) .long 0x7c000000|\
715 (ra<<16)|(rb<<11)|(454<<1)
717 #define ICCCI(ra,rb) .long 0x7c000000|\
718 (ra<<16)|(rb<<11)|(966<<1)
720 #define DCREAD(rt,ra,rb) .long 0x7c000000|\
721 (rt<<21)|(ra<<16)|(rb<<11)|(486<<1)
723 #define ICREAD(ra,rb) .long 0x7c000000|\
724 (ra<<16)|(rb<<11)|(998<<1)
726 #define TLBSX(rt,ra,rb) .long 0x7c000000|\
727 (rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
729 #define TLBWE(rs,ra,ws) .long 0x7c000000|\
730 (rs<<21)|(ra<<16)|(ws<<11)|(978<<1)
732 #define TLBRE(rt,ra,ws) .long 0x7c000000|\
733 (rt<<21)|(ra<<16)|(ws<<11)|(946<<1)
735 #define TLBSXDOT(rt,ra,rb) .long 0x7c000001|\
736 (rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
738 #define MSYNC .long 0x7c000000|\
741 #define MBAR_INST .long 0x7c000000|\
746 void mttlb1(unsigned long index, unsigned long value);
747 void mttlb2(unsigned long index, unsigned long value);
748 void mttlb3(unsigned long index, unsigned long value);
749 unsigned long mftlb1(unsigned long index);
750 unsigned long mftlb2(unsigned long index);
751 unsigned long mftlb3(unsigned long index);
753 void program_tlb(u64 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
754 void remove_tlb(u32 vaddr, u32 size);
755 void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value);
756 #endif /* __ASSEMBLY__ */
758 #endif /* CONFIG_440 */
759 #endif /* _PPC_MMU_H_ */