3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #ifndef _PPC4xx_EBC_H_
25 #define _PPC4xx_EBC_H_
28 * Currently there are two register layout versions for the
29 * IBM EBC core used on 4xx PPC's:
31 #if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \
32 defined(CONFIG_405EP) || \
33 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
34 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
35 #define CONFIG_EBC_PPC4xx_IBM_VER1
38 /* Bank Configuration Register */
39 #define EBC_BXCR_BAS_MASK PPC_REG_VAL(11, 0xFFF)
40 #define EBC_BXCR_BAS_ENCODE(n) (((static_cast(u32, n)) & EBC_BXCR_BAS_MASK))
41 #define EBC_BXCR_BS_MASK PPC_REG_VAL(14, 0x7)
42 #define EBC_BXCR_BS_1MB PPC_REG_VAL(14, 0x0)
43 #define EBC_BXCR_BS_2MB PPC_REG_VAL(14, 0x1)
44 #define EBC_BXCR_BS_4MB PPC_REG_VAL(14, 0x2)
45 #define EBC_BXCR_BS_8MB PPC_REG_VAL(14, 0x3)
46 #define EBC_BXCR_BS_16MB PPC_REG_VAL(14, 0x4)
47 #define EBC_BXCR_BS_32MB PPC_REG_VAL(14, 0x5)
48 #define EBC_BXCR_BS_64MB PPC_REG_VAL(14, 0x6)
49 #define EBC_BXCR_BS_128MB PPC_REG_VAL(14, 0x7)
50 #define EBC_BXCR_BU_MASK PPC_REG_VAL(16, 0x3)
51 #define EBC_BXCR_BU_NONE PPC_REG_VAL(16, 0x0)
52 #define EBC_BXCR_BU_R PPC_REG_VAL(16, 0x1)
53 #define EBC_BXCR_BU_W PPC_REG_VAL(16, 0x2)
54 #define EBC_BXCR_BU_RW PPC_REG_VAL(16, 0x3)
55 #define EBC_BXCR_BW_MASK PPC_REG_VAL(18, 0x3)
56 #define EBC_BXCR_BW_8BIT PPC_REG_VAL(18, 0x0)
57 #define EBC_BXCR_BW_16BIT PPC_REG_VAL(18, 0x1)
58 #if defined(CONFIG_EBC_PPC4xx_IBM_VER1)
59 #define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x2)
61 #define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x3)
64 /* Bank Access Parameter Register */
65 #define EBC_BXAP_BME_ENABLED PPC_REG_VAL(0, 0x1)
66 #define EBC_BXAP_BME_DISABLED PPC_REG_VAL(0, 0x0)
67 #define EBC_BXAP_TWT_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0xFF)
68 #define EBC_BXAP_FWT_ENCODE(n) PPC_REG_VAL(5, (static_cast(u32, n)) & 0x1F)
69 #define EBC_BXAP_BWT_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0x7)
70 #define EBC_BXAP_BCE_DISABLE PPC_REG_VAL(9, 0x0)
71 #define EBC_BXAP_BCE_ENABLE PPC_REG_VAL(9, 0x1)
72 #define EBC_BXAP_BCT_MASK PPC_REG_VAL(11, 0x3)
73 #define EBC_BXAP_BCT_2TRANS PPC_REG_VAL(11, 0x0)
74 #define EBC_BXAP_BCT_4TRANS PPC_REG_VAL(11, 0x1)
75 #define EBC_BXAP_BCT_8TRANS PPC_REG_VAL(11, 0x2)
76 #define EBC_BXAP_BCT_16TRANS PPC_REG_VAL(11, 0x3)
77 #define EBC_BXAP_CSN_ENCODE(n) PPC_REG_VAL(13, (static_cast(u32, n)) & 0x3)
78 #define EBC_BXAP_OEN_ENCODE(n) PPC_REG_VAL(15, (static_cast(u32, n)) & 0x3)
79 #define EBC_BXAP_WBN_ENCODE(n) PPC_REG_VAL(17, (static_cast(u32, n)) & 0x3)
80 #define EBC_BXAP_WBF_ENCODE(n) PPC_REG_VAL(19, (static_cast(u32, n)) & 0x3)
81 #define EBC_BXAP_TH_ENCODE(n) PPC_REG_VAL(22, (static_cast(u32, n)) & 0x7)
82 #define EBC_BXAP_RE_ENABLED PPC_REG_VAL(23, 0x1)
83 #define EBC_BXAP_RE_DISABLED PPC_REG_VAL(23, 0x0)
84 #define EBC_BXAP_SOR_DELAYED PPC_REG_VAL(24, 0x0)
85 #define EBC_BXAP_SOR_NONDELAYED PPC_REG_VAL(24, 0x1)
86 #define EBC_BXAP_BEM_WRITEONLY PPC_REG_VAL(25, 0x0)
87 #define EBC_BXAP_BEM_RW PPC_REG_VAL(25, 0x1)
88 #define EBC_BXAP_PEN_DISABLED PPC_REG_VAL(26, 0x0)
89 #define EBC_BXAP_PEN_ENABLED PPC_REG_VAL(26, 0x1)
91 /* Common fields in EBC0_CFG register */
92 #define EBC_CFG_PTD_MASK PPC_REG_VAL(1, 0x1)
93 #define EBC_CFG_PTD_ENABLE PPC_REG_VAL(1, 0x0)
94 #define EBC_CFG_PTD_DISABLE PPC_REG_VAL(1, 0x1)
95 #define EBC_CFG_RTC_MASK PPC_REG_VAL(4, 0x7)
96 #define EBC_CFG_RTC_16PERCLK PPC_REG_VAL(4, 0x0)
97 #define EBC_CFG_RTC_32PERCLK PPC_REG_VAL(4, 0x1)
98 #define EBC_CFG_RTC_64PERCLK PPC_REG_VAL(4, 0x2)
99 #define EBC_CFG_RTC_128PERCLK PPC_REG_VAL(4, 0x3)
100 #define EBC_CFG_RTC_256PERCLK PPC_REG_VAL(4, 0x4)
101 #define EBC_CFG_RTC_512PERCLK PPC_REG_VAL(4, 0x5)
102 #define EBC_CFG_RTC_1024PERCLK PPC_REG_VAL(4, 0x6)
103 #define EBC_CFG_RTC_2048PERCLK PPC_REG_VAL(4, 0x7)
104 #define EBC_CFG_PME_MASK PPC_REG_VAL(14, 0x1)
105 #define EBC_CFG_PME_DISABLE PPC_REG_VAL(14, 0x0)
106 #define EBC_CFG_PME_ENABLE PPC_REG_VAL(14, 0x1)
107 #define EBC_CFG_PMT_MASK PPC_REG_VAL(19, 0x1F)
108 #define EBC_CFG_PMT_ENCODE(n) PPC_REG_VAL(19, (static_cast(u32, n)) & 0x1F)
110 /* Now the two versions of the other bits */
111 #if defined(CONFIG_EBC_PPC4xx_IBM_VER1)
112 #define EBC_CFG_EBTC_MASK PPC_REG_VAL(0, 0x1)
113 #define EBC_CFG_EBTC_HI PPC_REG_VAL(0, 0x0)
114 #define EBC_CFG_EBTC_DRIVEN PPC_REG_VAL(0, 0x1)
115 #define EBC_CFG_EMPH_MASK PPC_REG_VAL(6, 0x3)
116 #define EBC_CFG_EMPH_ENCODE(n) PPC_REG_VAL(6, (static_cast(u32, n)) & 0x3)
117 #define EBC_CFG_EMPL_MASK PPC_REG_VAL(8, 0x3)
118 #define EBC_CFG_EMPL_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0x3)
119 #define EBC_CFG_CSTC_MASK PPC_REG_VAL(9, 0x1)
120 #define EBC_CFG_CSTC_HI PPC_REG_VAL(9, 0x0)
121 #define EBC_CFG_CSTC_DRIVEN PPC_REG_VAL(9, 0x1)
122 #define EBC_CFG_BPR_MASK PPC_REG_VAL(11, 0x3)
123 #define EBC_CFG_BPR_1DW PPC_REG_VAL(11, 0x0)
124 #define EBC_CFG_BPR_2DW PPC_REG_VAL(11, 0x1)
125 #define EBC_CFG_BPR_4DW PPC_REG_VAL(11, 0x2)
126 #define EBC_CFG_EMS_MASK PPC_REG_VAL(13, 0x3)
127 #define EBC_CFG_EMS_8BIT PPC_REG_VAL(13, 0x0)
128 #define EBC_CFG_EMS_16BIT PPC_REG_VAL(13, 0x1)
129 #define EBC_CFG_EMS_32BIT PPC_REG_VAL(13, 0x2)
131 #define EBC_CFG_LE_MASK PPC_REG_VAL(0, 0x1)
132 #define EBC_CFG_LE_UNLOCK PPC_REG_VAL(0, 0x0)
133 #define EBC_CFG_LE_LOCK PPC_REG_VAL(0, 0x1)
134 #define EBC_CFG_ATC_MASK PPC_REG_VAL(5, 0x1)
135 #define EBC_CFG_ATC_HI PPC_REG_VAL(5, 0x0)
136 #define EBC_CFG_ATC_PREVIOUS PPC_REG_VAL(5, 0x1)
137 #define EBC_CFG_DTC_MASK PPC_REG_VAL(6, 0x1)
138 #define EBC_CFG_DTC_HI PPC_REG_VAL(6, 0x0)
139 #define EBC_CFG_DTC_PREVIOUS PPC_REG_VAL(6, 0x1)
140 #define EBC_CFG_CTC_MASK PPC_REG_VAL(7, 0x1)
141 #define EBC_CFG_CTC_HI PPC_REG_VAL(7, 0x0)
142 #define EBC_CFG_CTC_PREVIOUS PPC_REG_VAL(7, 0x1)
143 #define EBC_CFG_OEO_MASK PPC_REG_VAL(8, 0x1)
144 #define EBC_CFG_OEO_HI PPC_REG_VAL(8, 0x0)
145 #define EBC_CFG_OEO_PREVIOUS PPC_REG_VAL(8, 0x1)
146 #define EBC_CFG_EMC_MASK PPC_REG_VAL(9, 0x1)
147 #define EBC_CFG_EMC_NONDEFAULT PPC_REG_VAL(9, 0x0)
148 #define EBC_CFG_EMC_DEFAULT PPC_REG_VAL(9, 0x1)
149 #define EBC_CFG_PR_MASK PPC_REG_VAL(21, 0x3)
150 #define EBC_CFG_PR_16 PPC_REG_VAL(21, 0x0)
151 #define EBC_CFG_PR_32 PPC_REG_VAL(21, 0x1)
152 #define EBC_CFG_PR_64 PPC_REG_VAL(21, 0x2)
153 #define EBC_CFG_PR_128 PPC_REG_VAL(21, 0x3)
156 #endif /* _PPC4xx_EBC_H_ */