2 * MPC8xx Communication Processor Module.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * (C) Copyright 2000-2006
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * This file contains structures and information for the communication
9 * processor channels. Some CPM control and status is available
10 * throught the MPC8xx internal memory map. See immap.h for details.
11 * This file only contains what I need for the moment, not the total
12 * CPM capabilities. I (or someone else) will add definitions as they
19 #include <asm/8xx_immap.h>
21 /* CPM Command register.
23 #define CPM_CR_RST ((ushort)0x8000)
24 #define CPM_CR_OPCODE ((ushort)0x0f00)
25 #define CPM_CR_CHAN ((ushort)0x00f0)
26 #define CPM_CR_FLG ((ushort)0x0001)
28 /* Some commands (there are more...later)
30 #define CPM_CR_INIT_TRX ((ushort)0x0000)
31 #define CPM_CR_INIT_RX ((ushort)0x0001)
32 #define CPM_CR_INIT_TX ((ushort)0x0002)
33 #define CPM_CR_HUNT_MODE ((ushort)0x0003)
34 #define CPM_CR_STOP_TX ((ushort)0x0004)
35 #define CPM_CR_RESTART_TX ((ushort)0x0006)
36 #define CPM_CR_SET_GADDR ((ushort)0x0008)
40 #define CPM_CR_CH_SCC1 ((ushort)0x0000)
41 #define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
42 #define CPM_CR_CH_SCC2 ((ushort)0x0004)
43 #define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */
44 #define CPM_CR_CH_SCC3 ((ushort)0x0008)
45 #define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
46 #define CPM_CR_CH_SCC4 ((ushort)0x000c)
47 #define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
49 #define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
52 * DPRAM defines and allocation functions
55 /* The dual ported RAM is multi-functional. Some areas can be (and are
56 * being) used for microcode. There is an area that can only be used
57 * as data ram for buffer descriptors, which is all we use right now.
58 * Currently the first 512 and last 256 bytes are used for microcode.
60 #ifdef CONFIG_SYS_ALLOC_DPRAM
62 #define CPM_DATAONLY_BASE ((uint)0x0800)
63 #define CPM_DATAONLY_SIZE ((uint)0x0700)
64 #define CPM_DP_NOSPACE ((uint)0x7fffffff)
68 #define CPM_SERIAL_BASE 0x0800
69 #define CPM_I2C_BASE 0x0820
70 #define CPM_SPI_BASE 0x0840
71 #define CPM_FEC_BASE 0x0860
72 #define CPM_SERIAL2_BASE 0x08E0
73 #define CPM_SCC_BASE 0x0900
74 #define CPM_POST_BASE 0x0980
75 #define CPM_WLKBD_BASE 0x0a00
79 #ifndef CONFIG_SYS_CPM_POST_WORD_ADDR
80 #define CPM_POST_WORD_ADDR 0x07FC
82 #define CPM_POST_WORD_ADDR CONFIG_SYS_CPM_POST_WORD_ADDR
85 #ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR
86 #define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong))
88 #define CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_BOOTCOUNT_ADDR
91 #define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
93 /* Export the base address of the communication processor registers
96 extern cpm8xx_t *cpmp; /* Pointer to comm processor */
98 /* Buffer descriptors used by many of the CPM protocols.
100 typedef struct cpm_buf_desc {
101 ushort cbd_sc; /* Status and Control */
102 ushort cbd_datlen; /* Data length in buffer */
103 uint cbd_bufaddr; /* Buffer address in host memory */
106 #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
107 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
108 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
109 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
110 #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
111 #define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
112 #define BD_SC_CM ((ushort)0x0200) /* Continous mode */
113 #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
114 #define BD_SC_P ((ushort)0x0100) /* xmt preamble */
115 #define BD_SC_BR ((ushort)0x0020) /* Break received */
116 #define BD_SC_FR ((ushort)0x0010) /* Framing error */
117 #define BD_SC_PR ((ushort)0x0008) /* Parity error */
118 #define BD_SC_OV ((ushort)0x0002) /* Overrun */
119 #define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
121 /* Parameter RAM offsets.
123 #define PROFF_SCC1 ((uint)0x0000)
124 #define PROFF_IIC ((uint)0x0080)
125 #define PROFF_REVNUM ((uint)0x00b0)
126 #define PROFF_SCC2 ((uint)0x0100)
127 #define PROFF_SPI ((uint)0x0180)
128 #define PROFF_SCC3 ((uint)0x0200)
129 #define PROFF_SMC1 ((uint)0x0280)
130 #define PROFF_SCC4 ((uint)0x0300)
131 #define PROFF_SMC2 ((uint)0x0380)
133 /* Define enough so I can at least use the serial port as a UART.
135 typedef struct smc_uart {
136 ushort smc_rbase; /* Rx Buffer descriptor base address */
137 ushort smc_tbase; /* Tx Buffer descriptor base address */
138 u_char smc_rfcr; /* Rx function code */
139 u_char smc_tfcr; /* Tx function code */
140 ushort smc_mrblr; /* Max receive buffer length */
141 uint smc_rstate; /* Internal */
142 uint smc_idp; /* Internal */
143 ushort smc_rbptr; /* Internal */
144 ushort smc_ibc; /* Internal */
145 uint smc_rxtmp; /* Internal */
146 uint smc_tstate; /* Internal */
147 uint smc_tdp; /* Internal */
148 ushort smc_tbptr; /* Internal */
149 ushort smc_tbc; /* Internal */
150 uint smc_txtmp; /* Internal */
151 ushort smc_maxidl; /* Maximum idle characters */
152 ushort smc_tmpidl; /* Temporary idle counter */
153 ushort smc_brklen; /* Last received break length */
154 ushort smc_brkec; /* rcv'd break condition counter */
155 ushort smc_brkcr; /* xmt break count register */
156 ushort smc_rmask; /* Temporary bit mask */
158 ushort smc_rpbase; /* Relocation pointer */
161 /* Function code bits.
163 #define SMC_EB ((u_char)0x10) /* Set big endian byte order */
165 /* SMC uart mode register.
167 #define SMCMR_REN ((ushort)0x0001)
168 #define SMCMR_TEN ((ushort)0x0002)
169 #define SMCMR_DM ((ushort)0x000c)
170 #define SMCMR_SM_GCI ((ushort)0x0000)
171 #define SMCMR_SM_UART ((ushort)0x0020)
172 #define SMCMR_SM_TRANS ((ushort)0x0030)
173 #define SMCMR_SM_MASK ((ushort)0x0030)
174 #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
175 #define SMCMR_REVD SMCMR_PM_EVEN
176 #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
177 #define SMCMR_BS SMCMR_PEN
178 #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
179 #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
180 #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
182 /* SMC2 as Centronics parallel printer. It is half duplex, in that
183 * it can only receive or transmit. The parameter ram values for
184 * each direction are either unique or properly overlap, so we can
185 * include them in one structure.
187 typedef struct smc_centronics {
205 ushort scent_character1;
206 ushort scent_character2;
207 ushort scent_character3;
208 ushort scent_character4;
209 ushort scent_character5;
210 ushort scent_character6;
211 ushort scent_character7;
212 ushort scent_character8;
217 /* Centronics Status Mask Register.
219 #define SMC_CENT_F ((u_char)0x08)
220 #define SMC_CENT_PE ((u_char)0x04)
221 #define SMC_CENT_S ((u_char)0x02)
223 /* SMC Event and Mask register.
225 #define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
226 #define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
227 #define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
228 #define SMCM_BSY ((unsigned char)0x04)
229 #define SMCM_TX ((unsigned char)0x02)
230 #define SMCM_RX ((unsigned char)0x01)
232 /* Baud rate generators.
234 #define CPM_BRG_RST ((uint)0x00020000)
235 #define CPM_BRG_EN ((uint)0x00010000)
236 #define CPM_BRG_EXTC_INT ((uint)0x00000000)
237 #define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
238 #define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
239 #define CPM_BRG_ATB ((uint)0x00002000)
240 #define CPM_BRG_CD_MASK ((uint)0x00001ffe)
241 #define CPM_BRG_DIV16 ((uint)0x00000001)
243 /* SI Clock Route Register
245 #define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000)
246 #define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000)
247 #define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800)
248 #define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100)
249 #define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000)
250 #define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000)
251 #define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000)
252 #define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000)
256 #define SCC_GSMRH_IRP ((uint)0x00040000)
257 #define SCC_GSMRH_GDE ((uint)0x00010000)
258 #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
259 #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
260 #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
261 #define SCC_GSMRH_REVD ((uint)0x00002000)
262 #define SCC_GSMRH_TRX ((uint)0x00001000)
263 #define SCC_GSMRH_TTX ((uint)0x00000800)
264 #define SCC_GSMRH_CDP ((uint)0x00000400)
265 #define SCC_GSMRH_CTSP ((uint)0x00000200)
266 #define SCC_GSMRH_CDS ((uint)0x00000100)
267 #define SCC_GSMRH_CTSS ((uint)0x00000080)
268 #define SCC_GSMRH_TFL ((uint)0x00000040)
269 #define SCC_GSMRH_RFW ((uint)0x00000020)
270 #define SCC_GSMRH_TXSY ((uint)0x00000010)
271 #define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
272 #define SCC_GSMRH_SYNL8 ((uint)0x00000008)
273 #define SCC_GSMRH_SYNL4 ((uint)0x00000004)
274 #define SCC_GSMRH_RTSM ((uint)0x00000002)
275 #define SCC_GSMRH_RSYN ((uint)0x00000001)
277 #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
278 #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
279 #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
280 #define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
281 #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
282 #define SCC_GSMRL_TCI ((uint)0x10000000)
283 #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
284 #define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
285 #define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
286 #define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
287 #define SCC_GSMRL_RINV ((uint)0x02000000)
288 #define SCC_GSMRL_TINV ((uint)0x01000000)
289 #define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
290 #define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
291 #define SCC_GSMRL_TPL_48 ((uint)0x00800000)
292 #define SCC_GSMRL_TPL_32 ((uint)0x00600000)
293 #define SCC_GSMRL_TPL_16 ((uint)0x00400000)
294 #define SCC_GSMRL_TPL_8 ((uint)0x00200000)
295 #define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
296 #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
297 #define SCC_GSMRL_TPP_01 ((uint)0x00100000)
298 #define SCC_GSMRL_TPP_10 ((uint)0x00080000)
299 #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
300 #define SCC_GSMRL_TEND ((uint)0x00040000)
301 #define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
302 #define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
303 #define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
304 #define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
305 #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
306 #define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
307 #define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
308 #define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
309 #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
310 #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
311 #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
312 #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
313 #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
314 #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
315 #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
316 #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
317 #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
318 #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
319 #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
320 #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
321 #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
322 #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
323 #define SCC_GSMRL_ENR ((uint)0x00000020)
324 #define SCC_GSMRL_ENT ((uint)0x00000010)
325 #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
326 #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
327 #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
328 #define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
329 #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
330 #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
331 #define SCC_GSMRL_MODE_UART ((uint)0x00000004)
332 #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
333 #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
334 #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
336 #define SCC_TODR_TOD ((ushort)0x8000)
338 /* SCC Event and Mask register.
340 #define SCCM_TXE ((unsigned char)0x10)
341 #define SCCM_BSY ((unsigned char)0x04)
342 #define SCCM_TX ((unsigned char)0x02)
343 #define SCCM_RX ((unsigned char)0x01)
345 typedef struct scc_param {
346 ushort scc_rbase; /* Rx Buffer descriptor base address */
347 ushort scc_tbase; /* Tx Buffer descriptor base address */
348 u_char scc_rfcr; /* Rx function code */
349 u_char scc_tfcr; /* Tx function code */
350 ushort scc_mrblr; /* Max receive buffer length */
351 uint scc_rstate; /* Internal */
352 uint scc_idp; /* Internal */
353 ushort scc_rbptr; /* Internal */
354 ushort scc_ibc; /* Internal */
355 uint scc_rxtmp; /* Internal */
356 uint scc_tstate; /* Internal */
357 uint scc_tdp; /* Internal */
358 ushort scc_tbptr; /* Internal */
359 ushort scc_tbc; /* Internal */
360 uint scc_txtmp; /* Internal */
361 uint scc_rcrc; /* Internal */
362 uint scc_tcrc; /* Internal */
365 /* Function code bits.
367 #define SCC_EB ((u_char)0x10) /* Set big endian byte order */
369 /* CPM Ethernet through SCCx.
371 typedef struct scc_enet {
373 uint sen_cpres; /* Preset CRC */
374 uint sen_cmask; /* Constant mask for CRC */
375 uint sen_crcec; /* CRC Error counter */
376 uint sen_alec; /* alignment error counter */
377 uint sen_disfc; /* discard frame counter */
378 ushort sen_pads; /* Tx short frame pad character */
379 ushort sen_retlim; /* Retry limit threshold */
380 ushort sen_retcnt; /* Retry limit counter */
381 ushort sen_maxflr; /* maximum frame length register */
382 ushort sen_minflr; /* minimum frame length register */
383 ushort sen_maxd1; /* maximum DMA1 length */
384 ushort sen_maxd2; /* maximum DMA2 length */
385 ushort sen_maxd; /* Rx max DMA */
386 ushort sen_dmacnt; /* Rx DMA counter */
387 ushort sen_maxb; /* Max BD byte count */
388 ushort sen_gaddr1; /* Group address filter */
392 uint sen_tbuf0data0; /* Save area 0 - current frame */
393 uint sen_tbuf0data1; /* Save area 1 - current frame */
394 uint sen_tbuf0rba; /* Internal */
395 uint sen_tbuf0crc; /* Internal */
396 ushort sen_tbuf0bcnt; /* Internal */
397 ushort sen_paddrh; /* physical address (MSB) */
399 ushort sen_paddrl; /* physical address (LSB) */
400 ushort sen_pper; /* persistence */
401 ushort sen_rfbdptr; /* Rx first BD pointer */
402 ushort sen_tfbdptr; /* Tx first BD pointer */
403 ushort sen_tlbdptr; /* Tx last BD pointer */
404 uint sen_tbuf1data0; /* Save area 0 - current frame */
405 uint sen_tbuf1data1; /* Save area 1 - current frame */
406 uint sen_tbuf1rba; /* Internal */
407 uint sen_tbuf1crc; /* Internal */
408 ushort sen_tbuf1bcnt; /* Internal */
409 ushort sen_txlen; /* Tx Frame length counter */
410 ushort sen_iaddr1; /* Individual address filter */
414 ushort sen_boffcnt; /* Backoff counter */
416 /* NOTE: Some versions of the manual have the following items
417 * incorrectly documented. Below is the proper order.
419 ushort sen_taddrh; /* temp address (MSB) */
421 ushort sen_taddrl; /* temp address (LSB) */
424 /**********************************************************************
426 * Board specific configuration settings.
428 * Please note that we use the presence of a #define SCC_ENET and/or
429 * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers.
430 **********************************************************************/
433 /*** ADS *************************************************************/
435 #if defined(CONFIG_MPC860) && defined(CONFIG_ADS)
436 /* This ENET stuff is for the MPC860ADS with ethernet on SCC1.
439 #define PROFF_ENET PROFF_SCC1
440 #define CPM_CR_ENET CPM_CR_CH_SCC1
443 #define PA_ENET_RXD ((ushort)0x0001)
444 #define PA_ENET_TXD ((ushort)0x0002)
445 #define PA_ENET_TCLK ((ushort)0x0100)
446 #define PA_ENET_RCLK ((ushort)0x0200)
448 #define PB_ENET_TENA ((uint)0x00001000)
450 #define PC_ENET_CLSN ((ushort)0x0010)
451 #define PC_ENET_RENA ((ushort)0x0020)
453 #define SICR_ENET_MASK ((uint)0x000000ff)
454 #define SICR_ENET_CLKRT ((uint)0x0000002c)
456 /* 68160 PHY control */
458 #define PC_ENET_ETHLOOP ((ushort)0x0800)
459 #define PC_ENET_TPFLDL ((ushort)0x0400)
460 #define PC_ENET_TPSQEL ((ushort)0x0200)
462 #endif /* MPC860ADS */
464 /*** BSEIP **********************************************************/
467 /* This ENET stuff is for the MPC823 with ethernet on SCC2.
468 * This is unique to the BSE ip-Engine board.
470 #define PROFF_ENET PROFF_SCC2
471 #define CPM_CR_ENET CPM_CR_CH_SCC2
473 #define PA_ENET_RXD ((ushort)0x0004)
474 #define PA_ENET_TXD ((ushort)0x0008)
475 #define PA_ENET_TCLK ((ushort)0x0100)
476 #define PA_ENET_RCLK ((ushort)0x0200)
477 #define PB_ENET_TENA ((uint)0x00002000)
478 #define PC_ENET_CLSN ((ushort)0x0040)
479 #define PC_ENET_RENA ((ushort)0x0080)
481 /* BSE uses port B and C bits for PHY control also.
483 #define PB_BSE_POWERUP ((uint)0x00000004)
484 #define PB_BSE_FDXDIS ((uint)0x00008000)
485 #define PC_BSE_LOOPBACK ((ushort)0x0800)
487 #define SICR_ENET_MASK ((uint)0x0000ff00)
488 #define SICR_ENET_CLKRT ((uint)0x00002c00)
489 #endif /* CONFIG_BSEIP */
491 /*** BSEIP **********************************************************/
493 #ifdef CONFIG_FLAGADM
494 /* Enet configuration for the FLAGADM */
497 #define PROFF_ENET PROFF_SCC2
498 #define CPM_CR_ENET CPM_CR_CH_SCC2
500 #define PA_ENET_RXD ((ushort)0x0004)
501 #define PA_ENET_TXD ((ushort)0x0008)
502 #define PA_ENET_TCLK ((ushort)0x0100)
503 #define PA_ENET_RCLK ((ushort)0x0400)
504 #define PB_ENET_TENA ((uint)0x00002000)
505 #define PC_ENET_CLSN ((ushort)0x0040)
506 #define PC_ENET_RENA ((ushort)0x0080)
508 #define SICR_ENET_MASK ((uint)0x0000ff00)
509 #define SICR_ENET_CLKRT ((uint)0x00003400)
510 #endif /* CONFIG_FLAGADM */
512 /*** ELPT860 *********************************************************/
514 #ifdef CONFIG_ELPT860
515 /* Bits in parallel I/O port registers that have to be set/cleared
516 * to configure the pins for SCC1 use.
518 # define PROFF_ENET PROFF_SCC1
519 # define CPM_CR_ENET CPM_CR_CH_SCC1
522 # define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
523 # define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
524 # define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
525 # define PA_ENET_TCLK ((ushort)0x0200) /* PA 6 */
527 # define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
528 # define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
529 # define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
531 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to
532 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
534 # define SICR_ENET_MASK ((uint)0x000000FF)
535 # define SICR_ENET_CLKRT ((uint)0x00000025)
536 #endif /* CONFIG_ELPT860 */
538 /*** ESTEEM 192E **************************************************/
539 #ifdef CONFIG_ESTEEM192E
541 * This ENET stuff is for the MPC850 with ethernet on SCC2. This
542 * is very similar to the RPX-Lite configuration.
543 * Note TENA , LOOPBACK , FDPLEX_DIS on Port B.
546 #define PROFF_ENET PROFF_SCC2
547 #define CPM_CR_ENET CPM_CR_CH_SCC2
550 #define PA_ENET_RXD ((ushort)0x0004)
551 #define PA_ENET_TXD ((ushort)0x0008)
552 #define PA_ENET_TCLK ((ushort)0x0200)
553 #define PA_ENET_RCLK ((ushort)0x0800)
554 #define PB_ENET_TENA ((uint)0x00002000)
555 #define PC_ENET_CLSN ((ushort)0x0040)
556 #define PC_ENET_RENA ((ushort)0x0080)
558 #define SICR_ENET_MASK ((uint)0x0000ff00)
559 #define SICR_ENET_CLKRT ((uint)0x00003d00)
561 #define PB_ENET_LOOPBACK ((uint)0x00004000)
562 #define PB_ENET_FDPLEX_DIS ((uint)0x00008000)
566 /*** FADS823 ********************************************************/
568 #if defined(CONFIG_MPC823FADS) && defined(CONFIG_FADS)
569 /* This ENET stuff is for the MPC823FADS with ethernet on SCC2.
571 #ifdef CONFIG_SCC2_ENET
572 #define PROFF_ENET PROFF_SCC2
573 #define CPM_CR_ENET CPM_CR_CH_SCC2
575 #define CPMVEC_ENET CPMVEC_SCC2
578 #ifdef CONFIG_SCC1_ENET
579 #define PROFF_ENET PROFF_SCC1
580 #define CPM_CR_ENET CPM_CR_CH_SCC1
582 #define CPMVEC_ENET CPMVEC_SCC1
585 #define PA_ENET_RXD ((ushort)0x0004)
586 #define PA_ENET_TXD ((ushort)0x0008)
587 #define PA_ENET_TCLK ((ushort)0x0400)
588 #define PA_ENET_RCLK ((ushort)0x0200)
590 #define PB_ENET_TENA ((uint)0x00002000)
592 #define PC_ENET_CLSN ((ushort)0x0040)
593 #define PC_ENET_RENA ((ushort)0x0080)
595 #define SICR_ENET_MASK ((uint)0x0000ff00)
596 #define SICR_ENET_CLKRT ((uint)0x00002e00)
598 #endif /* CONFIG_FADS823FADS */
600 /*** FADS850SAR ********************************************************/
602 #if defined(CONFIG_MPC850SAR) && defined(CONFIG_FADS)
603 /* This ENET stuff is for the MPC850SAR with ethernet on SCC2. Some of
604 * this may be unique to the FADS850SAR configuration.
605 * Note TENA is on Port B.
607 #define PROFF_ENET PROFF_SCC2
608 #define CPM_CR_ENET CPM_CR_CH_SCC2
610 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
611 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
612 #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
613 #define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
614 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
615 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
616 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
618 #define SICR_ENET_MASK ((uint)0x0000ff00)
619 #define SICR_ENET_CLKRT ((uint)0x00002f00) /* RCLK-CLK2, TCLK-CLK4 */
620 #endif /* CONFIG_FADS850SAR */
622 /*** FADS860T********************************************************/
624 #if defined(CONFIG_FADS) && defined(CONFIG_MPC86x)
626 * This ENET stuff is for the MPC86xFADS/MPC8xxADS with ethernet on SCC1.
628 #ifdef CONFIG_SCC1_ENET
632 #define PROFF_ENET PROFF_SCC1
633 #define CPM_CR_ENET CPM_CR_CH_SCC1
635 #define PA_ENET_RXD ((ushort)0x0001)
636 #define PA_ENET_TXD ((ushort)0x0002)
637 #define PA_ENET_TCLK ((ushort)0x0100)
638 #define PA_ENET_RCLK ((ushort)0x0200)
640 #define PB_ENET_TENA ((uint)0x00001000)
642 #define PC_ENET_CLSN ((ushort)0x0010)
643 #define PC_ENET_RENA ((ushort)0x0020)
645 #define SICR_ENET_MASK ((uint)0x000000ff)
646 #define SICR_ENET_CLKRT ((uint)0x0000002c)
648 #endif /* CONFIG_SCC1_ETHERNET */
651 * This ENET stuff is for the MPC860TFADS/MPC86xADS/MPC885ADS
652 * with ethernet on FEC.
655 #ifdef CONFIG_FEC_ENET
656 #define FEC_ENET /* Use FEC for Ethernet */
657 #endif /* CONFIG_FEC_ENET */
659 #endif /* CONFIG_FADS && CONFIG_MPC86x */
661 /*** FPS850L, FPS860L ************************************************/
663 #if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L)
664 /* Bits in parallel I/O port registers that have to be set/cleared
665 * to configure the pins for SCC2 use.
667 #define PROFF_ENET PROFF_SCC2
668 #define CPM_CR_ENET CPM_CR_CH_SCC2
670 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
671 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
672 #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
673 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
675 #define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */
676 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
677 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
679 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
680 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
682 #define SICR_ENET_MASK ((uint)0x0000ff00)
683 #define SICR_ENET_CLKRT ((uint)0x00002600)
684 #endif /* CONFIG_FPS850L, CONFIG_FPS860L */
686 /*** GEN860T **********************************************************/
687 #if defined(CONFIG_GEN860T)
691 #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
692 #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
693 #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
694 #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
695 #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
696 #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
697 #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
698 #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
699 #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
700 #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
701 #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
702 #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
703 #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
704 #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3-15 */
705 #endif /* CONFIG_GEN860T */
707 /*** GENIETV ********************************************************/
709 #if defined(CONFIG_GENIETV)
710 /* Ethernet is only on SCC2 */
712 #define CONFIG_SCC2_ENET
713 #define PROFF_ENET PROFF_SCC2
714 #define CPM_CR_ENET CPM_CR_CH_SCC2
716 #define CPMVEC_ENET CPMVEC_SCC2
718 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
719 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
720 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
721 #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
723 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
725 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
726 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
728 #define SICR_ENET_MASK ((uint)0x0000ff00)
729 #define SICR_ENET_CLKRT ((uint)0x00002e00)
731 #endif /* CONFIG_GENIETV */
733 /*** HERMES-PRO ******************************************************/
735 /* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */
739 #define FEC_ENET /* use FEC for EThernet */
743 #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
744 #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
745 #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
746 #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
747 #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
748 #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
749 #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
750 #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
751 #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
752 #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
753 #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
754 #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
755 #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
757 #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
759 #endif /* CONFIG_HERMES */
761 /*** ICU862 **********************************************************/
763 #if defined(CONFIG_ICU862)
765 #ifdef CONFIG_FEC_ENET
766 #define FEC_ENET /* use FEC for EThernet */
767 #endif /* CONFIG_FEC_ETHERNET */
769 #endif /* CONFIG_ICU862 */
771 /*** IP860 **********************************************************/
773 #if defined(CONFIG_IP860)
774 /* Bits in parallel I/O port registers that have to be set/cleared
775 * to configure the pins for SCC1 use.
777 #define PROFF_ENET PROFF_SCC1
778 #define CPM_CR_ENET CPM_CR_CH_SCC1
780 #define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
781 #define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
782 #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
783 #define PA_ENET_TCLK ((ushort)0x0100) /* PA 7 */
785 #define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
786 #define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
787 #define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
789 #define PB_ENET_RESET (uint)0x00000008 /* PB 28 */
790 #define PB_ENET_JABD (uint)0x00000004 /* PB 29 */
792 /* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
793 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
795 #define SICR_ENET_MASK ((uint)0x000000ff)
796 #define SICR_ENET_CLKRT ((uint)0x0000002C)
797 #endif /* CONFIG_IP860 */
799 /*** IVMS8 **********************************************************/
801 /* The IVMS8 uses the FEC on a MPC860T for Ethernet */
803 #if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
805 #define FEC_ENET /* use FEC for EThernet */
808 #define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */
810 #define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */
812 #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
813 #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
814 #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
815 #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
816 #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
817 #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
818 #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
819 #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
820 #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
821 #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
822 #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
823 #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
824 #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
826 #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
828 #endif /* CONFIG_IVMS8, CONFIG_IVML24 */
830 /*** KUP4K, KUP4X ****************************************************/
831 /* The KUP4 boards uses the FEC on a MPC8xx for Ethernet */
833 #if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
835 #define FEC_ENET /* use FEC for EThernet */
838 #define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */
840 #define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */
842 #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
843 #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
844 #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
845 #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
846 #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
847 #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
848 #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
849 #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
850 #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
851 #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
852 #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
853 #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
854 #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
856 #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
858 #endif /* CONFIG_KUP4K */
860 /*** LWMON **********************************************************/
862 #if defined(CONFIG_LWMON)
863 /* Bits in parallel I/O port registers that have to be set/cleared
864 * to configure the pins for SCC2 use.
866 #define PROFF_ENET PROFF_SCC2
867 #define CPM_CR_ENET CPM_CR_CH_SCC2
869 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
870 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
871 #define PA_ENET_RCLK ((ushort)0x0800) /* PA 4 */
872 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
874 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
876 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
877 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
879 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to
880 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
882 #define SICR_ENET_MASK ((uint)0x0000ff00)
883 #define SICR_ENET_CLKRT ((uint)0x00003E00)
884 #endif /* CONFIG_LWMON */
886 /*** KM8XX *********************************************************/
888 /* The KM8XX Service Module uses SCC3 for Ethernet */
891 #define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */
892 #define CPM_CR_ENET CPM_CR_CH_SCC3
894 #define PA_ENET_RXD ((ushort)0x0010) /* PA 11 */
895 #define PA_ENET_TXD ((ushort)0x0020) /* PA 10 */
896 #define PA_ENET_RCLK ((ushort)0x1000) /* PA 3 CLK 5 */
897 #define PA_ENET_TCLK ((ushort)0x2000) /* PA 2 CLK 6 */
899 #define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */
901 #define PC_ENET_RENA ((ushort)0x0200) /* PC 6 */
902 #define PC_ENET_CLSN ((ushort)0x0100) /* PC 7 */
904 /* Control bits in the SICR to route TCLK (CLK6) and RCLK (CLK5) to
905 * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
907 #define SICR_ENET_MASK ((uint)0x00FF0000)
908 #define SICR_ENET_CLKRT ((uint)0x00250000)
909 #endif /* CONFIG_KM8XX */
912 /*** MHPC ********************************************************/
914 #if defined(CONFIG_MHPC)
915 /* This ENET stuff is for the MHPC with ethernet on SCC2.
916 * Note TENA is on Port B.
918 #define PROFF_ENET PROFF_SCC2
919 #define CPM_CR_ENET CPM_CR_CH_SCC2
921 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
922 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
923 #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
924 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
925 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
926 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
927 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
929 #define SICR_ENET_MASK ((uint)0x0000ff00)
930 #define SICR_ENET_CLKRT ((uint)0x00002e00) /* RCLK-CLK2, TCLK-CLK3 */
931 #endif /* CONFIG_MHPC */
933 /*** NETVIA *******************************************************/
935 /* SinoVee Microsystems SC8xx series FEL8xx-AT,SC823,SC850,SC855T,SC860T */
936 #if ( defined CONFIG_SVM_SC8xx )
937 # ifndef CONFIG_FEC_ENET
939 #define PROFF_ENET PROFF_SCC2
940 #define CPM_CR_ENET CPM_CR_CH_SCC2
943 /* Bits in parallel I/O port registers that have to be set/cleared
944 * * * * to configure the pins for SCC2 use.
946 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
947 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
948 #define PA_ENET_RCLK ((ushort)0x0400) /* PA 5 */
949 #define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
951 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
953 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
954 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
955 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
956 * * * * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
958 #define SICR_ENET_MASK ((uint)0x0000ff00)
959 #define SICR_ENET_CLKRT ((uint)0x00003700)
961 # else /* Use FEC for Fast Ethernet */
966 #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
967 #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
968 #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
969 #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
970 #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
971 #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
972 #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
973 #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
974 #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
975 #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
976 #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
977 #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
978 #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
980 #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
982 # endif /* CONFIG_FEC_ENET */
983 #endif /* CONFIG_SVM_SC8xx */
986 #if defined(CONFIG_NETVIA)
987 /* Bits in parallel I/O port registers that have to be set/cleared
988 * to configure the pins for SCC2 use.
990 #define PROFF_ENET PROFF_SCC2
991 #define CPM_CR_ENET CPM_CR_CH_SCC2
993 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
994 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
995 #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
996 #define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
998 #if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
999 # define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */
1000 #elif CONFIG_NETVIA_VERSION >= 2
1001 # define PC_ENET_PDN ((ushort)0x0008) /* PC 12 */
1004 #define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */
1006 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1007 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1009 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1010 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1012 #define SICR_ENET_MASK ((uint)0x0000ff00)
1013 #define SICR_ENET_CLKRT ((uint)0x00002f00)
1015 #endif /* CONFIG_NETVIA */
1017 /*** QS850/QS823 ***************************************************/
1019 #if defined(CONFIG_QS850) || defined(CONFIG_QS823)
1020 #undef FEC_ENET /* Don't use FEC for EThernet */
1022 #define PROFF_ENET PROFF_SCC2
1023 #define CPM_CR_ENET CPM_CR_CH_SCC2
1026 #define PA_ENET_RXD ((ushort)0x0004) /* RXD on PA13 (Pin D9) */
1027 #define PA_ENET_TXD ((ushort)0x0008) /* TXD on PA12 (Pin D7) */
1028 #define PC_ENET_RENA ((ushort)0x0080) /* RENA on PC8 (Pin D12) */
1029 #define PC_ENET_CLSN ((ushort)0x0040) /* CLSN on PC9 (Pin C12) */
1030 #define PA_ENET_TCLK ((ushort)0x0200) /* TCLK on PA6 (Pin D8) */
1031 #define PA_ENET_RCLK ((ushort)0x0800) /* RCLK on PA4 (Pin D10) */
1032 #define PB_ENET_TENA ((uint)0x00002000) /* TENA on PB18 (Pin D11) */
1033 #define PC_ENET_LBK ((ushort)0x0010) /* Loopback control on PC11 (Pin B14) */
1034 #define PC_ENET_LI ((ushort)0x0020) /* Link Integrity control PC10 (A15) */
1035 #define PC_ENET_SQE ((ushort)0x0100) /* SQE Disable control PC7 (B15) */
1037 /* SCC2 TXCLK from CLK2
1038 * SCC2 RXCLK from CLK4
1039 * SCC2 Connected to NMSI */
1040 #define SICR_ENET_MASK ((uint)0x00007F00)
1041 #define SICR_ENET_CLKRT ((uint)0x00003D00)
1043 #endif /* CONFIG_QS850/QS823 */
1045 /*** QS860T ***************************************************/
1047 #ifdef CONFIG_QS860T
1048 #ifdef CONFIG_FEC_ENET
1049 #define FEC_ENET /* use FEC for EThernet */
1050 #endif /* CONFIG_FEC_ETHERNET */
1052 /* This ENET stuff is for GTH 10 Mbit ( SCC ) */
1053 #define PROFF_ENET PROFF_SCC1
1054 #define CPM_CR_ENET CPM_CR_CH_SCC1
1057 #define PA_ENET_RXD ((ushort)0x0001) /* PA15 */
1058 #define PA_ENET_TXD ((ushort)0x0002) /* PA14 */
1059 #define PA_ENET_TCLK ((ushort)0x0800) /* PA4 */
1060 #define PA_ENET_RCLK ((ushort)0x0200) /* PA6 */
1061 #define PB_ENET_TENA ((uint)0x00001000) /* PB19 */
1062 #define PC_ENET_CLSN ((ushort)0x0010) /* PC11 */
1063 #define PC_ENET_RENA ((ushort)0x0020) /* PC10 */
1065 #define SICR_ENET_MASK ((uint)0x000000ff)
1066 /* RCLK PA4 -->CLK4, TCLK PA6 -->CLK2 */
1067 #define SICR_ENET_CLKRT ((uint)0x0000003D)
1069 #endif /* CONFIG_QS860T */
1071 /*** RPXCLASSIC *****************************************************/
1073 #ifdef CONFIG_RPXCLASSIC
1075 #ifdef CONFIG_FEC_ENET
1077 # define FEC_ENET /* use FEC for EThernet */
1080 #else /* ! CONFIG_FEC_ENET */
1082 /* Bits in parallel I/O port registers that have to be set/cleared
1083 * to configure the pins for SCC1 use.
1085 #define PROFF_ENET PROFF_SCC1
1086 #define CPM_CR_ENET CPM_CR_CH_SCC1
1088 #define PA_ENET_RXD ((ushort)0x0001)
1089 #define PA_ENET_TXD ((ushort)0x0002)
1090 #define PA_ENET_TCLK ((ushort)0x0200)
1091 #define PA_ENET_RCLK ((ushort)0x0800)
1092 #define PB_ENET_TENA ((uint)0x00001000)
1093 #define PC_ENET_CLSN ((ushort)0x0010)
1094 #define PC_ENET_RENA ((ushort)0x0020)
1096 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
1097 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
1099 #define SICR_ENET_MASK ((uint)0x000000ff)
1100 #define SICR_ENET_CLKRT ((uint)0x0000003d)
1102 #endif /* CONFIG_FEC_ENET */
1104 #endif /* CONFIG_RPXCLASSIC */
1106 /*** RPXLITE ********************************************************/
1108 #ifdef CONFIG_RPXLITE
1109 /* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of
1110 * this may be unique to the RPX-Lite configuration.
1111 * Note TENA is on Port B.
1113 #define PROFF_ENET PROFF_SCC2
1114 #define CPM_CR_ENET CPM_CR_CH_SCC2
1116 #define PA_ENET_RXD ((ushort)0x0004)
1117 #define PA_ENET_TXD ((ushort)0x0008)
1118 #define PA_ENET_TCLK ((ushort)0x0200)
1119 #define PA_ENET_RCLK ((ushort)0x0800)
1120 #if defined(CONFIG_RMU)
1121 #define PC_ENET_TENA ((uint)0x00000002) /* PC14 */
1123 #define PB_ENET_TENA ((uint)0x00002000)
1125 #define PC_ENET_CLSN ((ushort)0x0040)
1126 #define PC_ENET_RENA ((ushort)0x0080)
1128 #define SICR_ENET_MASK ((uint)0x0000ff00)
1129 #define SICR_ENET_CLKRT ((uint)0x00003d00)
1130 #endif /* CONFIG_RPXLITE */
1132 /*** SM850 *********************************************************/
1134 /* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */
1137 #define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */
1138 #define CPM_CR_ENET CPM_CR_CH_SCC3
1140 #define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */
1141 #define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */
1142 #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
1143 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1145 #define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
1146 #define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */
1148 #define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */
1149 #define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */
1151 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1152 * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
1154 #define SICR_ENET_MASK ((uint)0x00FF0000)
1155 #define SICR_ENET_CLKRT ((uint)0x00260000)
1156 #endif /* CONFIG_SM850 */
1158 /*** SPD823TS ******************************************************/
1160 #ifdef CONFIG_SPD823TS
1161 /* Bits in parallel I/O port registers that have to be set/cleared
1162 * to configure the pins for SCC2 use.
1164 #define PROFF_ENET PROFF_SCC2 /* Ethernet on SCC2 */
1165 #define CPM_CR_ENET CPM_CR_CH_SCC2
1167 #define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */
1168 #define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */
1169 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1170 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1171 #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
1172 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1174 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
1176 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1177 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1178 #define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */
1180 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
1181 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1183 #define SICR_ENET_MASK ((uint)0x0000ff00)
1184 #define SICR_ENET_CLKRT ((uint)0x00002E00)
1185 #endif /* CONFIG_SPD823TS */
1187 /*** SXNI855T ******************************************************/
1189 #if defined(CONFIG_SXNI855T)
1191 #ifdef CONFIG_FEC_ENET
1192 #define FEC_ENET /* use FEC for Ethernet */
1193 #endif /* CONFIG_FEC_ETHERNET */
1195 #endif /* CONFIG_SXNI855T */
1197 /*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/
1199 #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
1200 defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \
1201 defined(CONFIG_RRVISION)|| defined(CONFIG_TQM823L) || \
1202 defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \
1203 defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) || \
1204 defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)
1206 /* Bits in parallel I/O port registers that have to be set/cleared
1207 * to configure the pins for SCC2 use.
1209 #define PROFF_ENET PROFF_SCC2
1210 #define CPM_CR_ENET CPM_CR_CH_SCC2
1211 #if (!defined(CONFIG_TK885D)) /* TK885D does not use SCC Ethernet */
1214 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1215 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1216 #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
1217 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1219 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
1221 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1222 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1223 #if defined(CONFIG_R360MPI)
1224 #define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
1225 #endif /* CONFIG_R360MPI */
1227 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1228 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1230 #define SICR_ENET_MASK ((uint)0x0000ff00)
1231 #define SICR_ENET_CLKRT ((uint)0x00002600)
1233 # ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */
1235 # endif /* CONFIG_FEC_ENET */
1237 #endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */
1239 /*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/
1241 #if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \
1242 defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \
1243 defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \
1244 defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M)
1246 # ifdef CONFIG_SCC1_ENET /* use SCC for 10Mbps Ethernet */
1248 /* Bits in parallel I/O port registers that have to be set/cleared
1249 * to configure the pins for SCC1 use.
1251 #define PROFF_ENET PROFF_SCC1
1252 #define CPM_CR_ENET CPM_CR_CH_SCC1
1254 #define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
1255 #define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
1256 #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
1257 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1259 #define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
1260 #define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
1261 #define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
1263 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1264 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
1266 #define SICR_ENET_MASK ((uint)0x000000ff)
1267 #define SICR_ENET_CLKRT ((uint)0x00000026)
1269 # endif /* CONFIG_SCC1_ENET */
1271 # ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */
1275 #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
1276 #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
1277 #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
1278 #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
1279 #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
1280 #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
1281 #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
1282 #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
1283 #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
1284 #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
1285 #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
1286 #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
1287 #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
1289 #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
1291 # endif /* CONFIG_FEC_ENET */
1292 #endif /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */
1294 /*** V37 **********************************************************/
1297 /* This ENET stuff is for the MPC823 with ethernet on SCC2. Some of
1298 * this may be unique to the Marel V37 configuration.
1299 * Note TENA is on Port B.
1301 #define PROFF_ENET PROFF_SCC2
1302 #define CPM_CR_ENET CPM_CR_CH_SCC2
1304 #define PA_ENET_RXD ((ushort)0x0004)
1305 #define PA_ENET_TXD ((ushort)0x0008)
1306 #define PA_ENET_TCLK ((ushort)0x0400)
1307 #define PA_ENET_RCLK ((ushort)0x0200)
1308 #define PB_ENET_TENA ((uint)0x00002000)
1309 #define PC_ENET_CLSN ((ushort)0x0040)
1310 #define PC_ENET_RENA ((ushort)0x0080)
1312 #define SICR_ENET_MASK ((uint)0x0000ff00)
1313 #define SICR_ENET_CLKRT ((uint)0x00002e00)
1314 #endif /* CONFIG_V37 */
1317 /*********************************************************************/
1319 /* SCC Event register as used by Ethernet.
1321 #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
1322 #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
1323 #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
1324 #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
1325 #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
1326 #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
1328 /* SCC Mode Register (PSMR) as used by Ethernet.
1330 #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
1331 #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
1332 #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
1333 #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
1334 #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
1335 #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
1336 #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
1337 #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
1338 #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
1339 #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
1340 #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
1341 #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
1342 #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
1344 /* Buffer descriptor control/status used by Ethernet receive.
1346 #define BD_ENET_RX_EMPTY ((ushort)0x8000)
1347 #define BD_ENET_RX_WRAP ((ushort)0x2000)
1348 #define BD_ENET_RX_INTR ((ushort)0x1000)
1349 #define BD_ENET_RX_LAST ((ushort)0x0800)
1350 #define BD_ENET_RX_FIRST ((ushort)0x0400)
1351 #define BD_ENET_RX_MISS ((ushort)0x0100)
1352 #define BD_ENET_RX_LG ((ushort)0x0020)
1353 #define BD_ENET_RX_NO ((ushort)0x0010)
1354 #define BD_ENET_RX_SH ((ushort)0x0008)
1355 #define BD_ENET_RX_CR ((ushort)0x0004)
1356 #define BD_ENET_RX_OV ((ushort)0x0002)
1357 #define BD_ENET_RX_CL ((ushort)0x0001)
1358 #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
1360 /* Buffer descriptor control/status used by Ethernet transmit.
1362 #define BD_ENET_TX_READY ((ushort)0x8000)
1363 #define BD_ENET_TX_PAD ((ushort)0x4000)
1364 #define BD_ENET_TX_WRAP ((ushort)0x2000)
1365 #define BD_ENET_TX_INTR ((ushort)0x1000)
1366 #define BD_ENET_TX_LAST ((ushort)0x0800)
1367 #define BD_ENET_TX_TC ((ushort)0x0400)
1368 #define BD_ENET_TX_DEF ((ushort)0x0200)
1369 #define BD_ENET_TX_HB ((ushort)0x0100)
1370 #define BD_ENET_TX_LC ((ushort)0x0080)
1371 #define BD_ENET_TX_RL ((ushort)0x0040)
1372 #define BD_ENET_TX_RCMASK ((ushort)0x003c)
1373 #define BD_ENET_TX_UN ((ushort)0x0002)
1374 #define BD_ENET_TX_CSL ((ushort)0x0001)
1375 #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
1379 typedef struct scc_uart {
1381 uint scc_res1; /* Reserved */
1382 uint scc_res2; /* Reserved */
1383 ushort scc_maxidl; /* Maximum idle chars */
1384 ushort scc_idlc; /* temp idle counter */
1385 ushort scc_brkcr; /* Break count register */
1386 ushort scc_parec; /* receive parity error counter */
1387 ushort scc_frmec; /* receive framing error counter */
1388 ushort scc_nosec; /* receive noise counter */
1389 ushort scc_brkec; /* receive break condition counter */
1390 ushort scc_brkln; /* last received break length */
1391 ushort scc_uaddr1; /* UART address character 1 */
1392 ushort scc_uaddr2; /* UART address character 2 */
1393 ushort scc_rtemp; /* Temp storage */
1394 ushort scc_toseq; /* Transmit out of sequence char */
1395 ushort scc_char1; /* control character 1 */
1396 ushort scc_char2; /* control character 2 */
1397 ushort scc_char3; /* control character 3 */
1398 ushort scc_char4; /* control character 4 */
1399 ushort scc_char5; /* control character 5 */
1400 ushort scc_char6; /* control character 6 */
1401 ushort scc_char7; /* control character 7 */
1402 ushort scc_char8; /* control character 8 */
1403 ushort scc_rccm; /* receive control character mask */
1404 ushort scc_rccr; /* receive control character register */
1405 ushort scc_rlbc; /* receive last break character */
1408 /* SCC Event and Mask registers when it is used as a UART.
1410 #define UART_SCCM_GLR ((ushort)0x1000)
1411 #define UART_SCCM_GLT ((ushort)0x0800)
1412 #define UART_SCCM_AB ((ushort)0x0200)
1413 #define UART_SCCM_IDL ((ushort)0x0100)
1414 #define UART_SCCM_GRA ((ushort)0x0080)
1415 #define UART_SCCM_BRKE ((ushort)0x0040)
1416 #define UART_SCCM_BRKS ((ushort)0x0020)
1417 #define UART_SCCM_CCR ((ushort)0x0008)
1418 #define UART_SCCM_BSY ((ushort)0x0004)
1419 #define UART_SCCM_TX ((ushort)0x0002)
1420 #define UART_SCCM_RX ((ushort)0x0001)
1422 /* The SCC PSMR when used as a UART.
1424 #define SCU_PSMR_FLC ((ushort)0x8000)
1425 #define SCU_PSMR_SL ((ushort)0x4000)
1426 #define SCU_PSMR_CL ((ushort)0x3000)
1427 #define SCU_PSMR_UM ((ushort)0x0c00)
1428 #define SCU_PSMR_FRZ ((ushort)0x0200)
1429 #define SCU_PSMR_RZS ((ushort)0x0100)
1430 #define SCU_PSMR_SYN ((ushort)0x0080)
1431 #define SCU_PSMR_DRT ((ushort)0x0040)
1432 #define SCU_PSMR_PEN ((ushort)0x0010)
1433 #define SCU_PSMR_RPM ((ushort)0x000c)
1434 #define SCU_PSMR_REVP ((ushort)0x0008)
1435 #define SCU_PSMR_TPM ((ushort)0x0003)
1436 #define SCU_PSMR_TEVP ((ushort)0x0003)
1438 /* CPM Transparent mode SCC.
1440 typedef struct scc_trans {
1442 uint st_cpres; /* Preset CRC */
1443 uint st_cmask; /* Constant mask for CRC */
1446 #define BD_SCC_TX_LAST ((ushort)0x0800)
1448 /* IIC parameter RAM.
1450 typedef struct iic {
1451 ushort iic_rbase; /* Rx Buffer descriptor base address */
1452 ushort iic_tbase; /* Tx Buffer descriptor base address */
1453 u_char iic_rfcr; /* Rx function code */
1454 u_char iic_tfcr; /* Tx function code */
1455 ushort iic_mrblr; /* Max receive buffer length */
1456 uint iic_rstate; /* Internal */
1457 uint iic_rdp; /* Internal */
1458 ushort iic_rbptr; /* Internal */
1459 ushort iic_rbc; /* Internal */
1460 uint iic_rxtmp; /* Internal */
1461 uint iic_tstate; /* Internal */
1462 uint iic_tdp; /* Internal */
1463 ushort iic_tbptr; /* Internal */
1464 ushort iic_tbc; /* Internal */
1465 uint iic_txtmp; /* Internal */
1466 uint iic_res; /* reserved */
1467 ushort iic_rpbase; /* Relocation pointer */
1468 ushort iic_res2; /* reserved */
1471 /* SPI parameter RAM.
1473 typedef struct spi {
1474 ushort spi_rbase; /* Rx Buffer descriptor base address */
1475 ushort spi_tbase; /* Tx Buffer descriptor base address */
1476 u_char spi_rfcr; /* Rx function code */
1477 u_char spi_tfcr; /* Tx function code */
1478 ushort spi_mrblr; /* Max receive buffer length */
1479 uint spi_rstate; /* Internal */
1480 uint spi_rdp; /* Internal */
1481 ushort spi_rbptr; /* Internal */
1482 ushort spi_rbc; /* Internal */
1483 uint spi_rxtmp; /* Internal */
1484 uint spi_tstate; /* Internal */
1485 uint spi_tdp; /* Internal */
1486 ushort spi_tbptr; /* Internal */
1487 ushort spi_tbc; /* Internal */
1488 uint spi_txtmp; /* Internal */
1490 ushort spi_rpbase; /* Relocation pointer */
1494 /* SPI Mode register.
1496 #define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
1497 #define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
1498 #define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
1499 #define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
1500 #define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
1501 #define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
1502 #define SPMODE_EN ((ushort)0x0100) /* Enable */
1503 #define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
1504 #define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
1506 #define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
1507 #define SPMODE_PM(x) ((x) &0xF)
1509 /* HDLC parameter RAM.
1512 typedef struct hdlc_pram_s {
1516 ushort rbase; /* Rx Buffer descriptor base address */
1517 ushort tbase; /* Tx Buffer descriptor base address */
1518 uchar rfcr; /* Rx function code */
1519 uchar tfcr; /* Tx function code */
1520 ushort mrblr; /* Rx buffer length */
1521 ulong rstate; /* Rx internal state */
1522 ulong rptr; /* Rx internal data pointer */
1523 ushort rbptr; /* rb BD Pointer */
1524 ushort rcount; /* Rx internal byte count */
1525 ulong rtemp; /* Rx temp */
1526 ulong tstate; /* Tx internal state */
1527 ulong tptr; /* Tx internal data pointer */
1528 ushort tbptr; /* Tx BD pointer */
1529 ushort tcount; /* Tx byte count */
1530 ulong ttemp; /* Tx temp */
1531 ulong rcrc; /* temp receive CRC */
1532 ulong tcrc; /* temp transmit CRC */
1534 * HDLC specific parameter RAM
1536 uchar res[4]; /* reserved */
1537 ulong c_mask; /* CRC constant */
1538 ulong c_pres; /* CRC preset */
1539 ushort disfc; /* discarded frame counter */
1540 ushort crcec; /* CRC error counter */
1541 ushort abtsc; /* abort sequence counter */
1542 ushort nmarc; /* nonmatching address rx cnt */
1543 ushort retrc; /* frame retransmission cnt */
1544 ushort mflr; /* maximum frame length reg */
1545 ushort max_cnt; /* maximum length counter */
1546 ushort rfthr; /* received frames threshold */
1547 ushort rfcnt; /* received frames count */
1548 ushort hmask; /* user defined frm addr mask */
1549 ushort haddr1; /* user defined frm address 1 */
1550 ushort haddr2; /* user defined frm address 2 */
1551 ushort haddr3; /* user defined frm address 3 */
1552 ushort haddr4; /* user defined frm address 4 */
1553 ushort tmp; /* temp */
1554 ushort tmp_mb; /* temp */
1557 /* CPM interrupts. There are nearly 32 interrupts generated by CPM
1558 * channels or devices. All of these are presented to the PPC core
1559 * as a single interrupt. The CPM interrupt handler dispatches its
1560 * own handlers, in a similar fashion to the PPC core handler. We
1561 * use the table as defined in the manuals (i.e. no special high
1562 * priority and SCC1 == SCCa, etc...).
1564 #define CPMVEC_NR 32
1565 #define CPMVEC_OFFSET 0x00010000
1566 #define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET)
1567 #define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET)
1568 #define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET)
1569 #define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET)
1570 #define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET)
1571 #define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET)
1572 #define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET)
1573 #define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET)
1574 #define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET)
1575 #define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET)
1576 #define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET)
1577 #define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET)
1578 #define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET)
1579 #define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET)
1580 #define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET)
1581 #define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET)
1582 #define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET)
1583 #define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET)
1584 #define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET)
1585 #define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET)
1586 #define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET)
1587 #define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET)
1588 #define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET)
1589 #define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET)
1590 #define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET)
1591 #define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET)
1592 #define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET)
1593 #define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET)
1594 #define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET)
1596 extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
1598 /* CPM interrupt configuration vector.
1600 #define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
1601 #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
1602 #define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
1603 #define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
1604 #define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */
1605 #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
1606 #define CICR_IEN ((uint)0x00000080) /* Int. enable */
1607 #define CICR_SPS ((uint)0x00000001) /* SCC Spread */
1608 #endif /* __CPM_8XX__ */