3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * Configuration settings for the AmigaOneG3SE board.
30 /* ------------------------------------------------------------------------- */
33 * board/config.h - configuration options, board specific
40 * High Level Configuration Options
44 #define CONFIG_AMIGAONEG3SE 1
46 #define CONFIG_BOARD_EARLY_INIT_F 1
47 #define CONFIG_MISC_INIT_R 1
49 #define CONFIG_VERY_BIG_RAM 1
51 #define CONFIG_CONS_INDEX 1
52 #define CONFIG_BAUDRATE 9600
53 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
55 #undef CONFIG_CLOCKS_IN_MHZ /* clocks passed to Linux in Hz */
57 #define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk=4096"
59 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
60 CONFIG_BOOTP_BOOTFILESIZE)
62 #define CONFIG_MAC_PARTITION
63 #define CONFIG_DOS_PARTITION
64 #define CONFIG_AMIGA_PARTITION
68 * Command line configuration.
70 #include <config_cmd_default.h>
72 #define CONFIG_CMD_ASKENV
73 #define CONFIG_CMD_BSP
74 #define CONFIG_CMD_DATE
75 #define CONFIG_CMD_DHCP
76 #define CONFIG_CMD_ELF
77 #define CONFIG_CMD_NET
78 #define CONFIG_CMD_IDE
79 #define CONFIG_CMD_FDC
80 #define CONFIG_CMD_CACHE
81 #define CONFIG_CMD_CONSOLE|
82 #define CONFIG_CMD_USB
83 #define CONFIG_CMD_BSP
84 #define CONFIG_CMD_PCI
88 /* #define CONFIG_PCI_SCAN_SHOW 1 */
89 #define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
92 * Miscellaneous configurable options
94 #define CFG_LONGHELP /* undef to save memory */
95 #define CFG_PROMPT "] " /* Monitor Command Prompt */
97 #define CFG_HUSH_PARSER 1 /* use "hush" command parser */
98 /* #undef CFG_HUSH_PARSER */
99 #ifdef CFG_HUSH_PARSER
100 #define CFG_PROMPT_HUSH_PS2 "> "
102 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
106 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
108 #define CFG_MAXARGS 64 /* max number of command args */
109 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
110 #define CFG_LOAD_ADDR 0x00500000 /* Default load address */
112 /*-----------------------------------------------------------------------
113 * Start addresses for the final memory configuration
114 * (Set up by the startup code)
115 * Please note that CFG_SDRAM_BASE _must_ start at 0
117 #define CFG_SDRAM_BASE 0x00000000
118 #define CFG_FLASH_BASE 0xFFF00000
119 #define CFG_FLASH_MAX_SIZE 0x00080000
120 /* Maximum amount of RAM.
122 #define CFG_MAX_RAM_SIZE 0x80000000 /* 2G */
124 #define CFG_RESET_ADDRESS 0xFFF00100
126 #define CFG_MONITOR_BASE TEXT_BASE
128 #define CFG_MONITOR_LEN (768 << 10) /* Reserve 512 kB for Monitor */
129 #define CFG_MALLOC_LEN (2500 << 10) /* Reserve 128 kB for malloc() */
131 #if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \
132 CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE
138 #define CFG_MEMTEST_START 0x00004000 /* memtest works on */
139 #define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
141 /*-----------------------------------------------------------------------
142 * Definitions for initial stack pointer and data area
145 /* Size in bytes reserved for initial data
147 /* HJF: used to be 0x400000 */
148 #define CFG_INIT_RAM_ADDR 0x40000000
149 #define CFG_INIT_RAM_END 0x8000
150 #define CFG_GBL_DATA_SIZE 128
151 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
152 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
154 #define CFG_INIT_RAM_LOCK
157 * Temporary buffer for serial data until the real serial driver
158 * is initialised (memtest will destroy this buffer)
160 #define CFG_SCONSOLE_ADDR CFG_INIT_RAM_ADDR
161 #define CFG_SCONSOLE_SIZE 0x0002000
166 /*HJF: #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
167 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_4M | BATU_VS | BATU_VP)
168 #define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
169 #define CFG_DBAT0U CFG_IBAT0U*/
171 #define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
172 #define CFG_DBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
173 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
174 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
177 #define CFG_DBAT1L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
178 #define CFG_DBAT1U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
179 #define CFG_IBAT1L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
180 #define CFG_IBAT1U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
182 #define CFG_IBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATL_PP_RW)
183 #define CFG_IBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATU_BL_256M | BATU_VS | BATU_VP)
184 #define CFG_DBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATL_PP_RW )
185 #define CFG_DBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATU_BL_256M | BATU_VS | BATU_VP)
188 /* Init RAM in the CPU DCache (no backing memory)
190 #define CFG_DBAT2L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
191 #define CFG_DBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
192 /* This used to be commented out */
193 #define CFG_IBAT2L CFG_DBAT2L
195 #define CFG_IBAT2U CFG_DBAT2U
198 /* I/O and PCI memory at 0xf0000000
200 #define CFG_DBAT3L (0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
201 #define CFG_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
203 #define CFG_IBAT3L (0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
204 #define CFG_IBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
207 * Low Level Configuration Settings
208 * (address mappings, register initial values, etc.)
211 #define CFG_BUS_HZ 133000000 /* bus speed - 100 mhz */
212 #define CFG_CPU_CLK 133000000
213 #define CFG_BUS_CLK 133000000
216 * For booting Linux, the board info and command line data
217 * have to be in the first 8 MB of memory, since this is
218 * the maximum mapped by the Linux kernel during initialization.
220 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
222 /*-----------------------------------------------------------------------
225 #define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
226 #define CFG_MAX_FLASH_SECT 8 /* Max number of sectors in one bank */
228 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
229 #define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
232 * Environment is stored in NVRAM.
234 #define CFG_ENV_IS_IN_NVRAM 1
235 #define CFG_ENV_ADDR 0xFD0E0000 /* This should be 0xFD0E0000, but we skip bytes to
236 * protect softex's settings for now.
237 * Original 768 bytes where not enough.
239 #define CFG_ENV_SIZE 0x8000 /* Size of the Environment. See comment above */
241 #define CFG_CONSOLE_IS_IN_ENV 1 /* stdin/stdout/stderr are in environment */
242 #define CFG_CONSOLE_OVERWRITE_ROUTINE 1
243 #define CONFIG_ENV_OVERWRITE 1
245 /*-----------------------------------------------------------------------
246 * Cache Configuration
248 #define CFG_CACHELINE_SIZE 32
249 #if defined(CONFIG_CMD_KGDB)
250 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
257 #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
258 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
259 #define L2_ENABLE (L2_INIT | L2CR_L2E)
262 * Internal Definitions
266 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
267 #define BOOTFLAG_WARM 0x02 /* Software reboot */
270 /*-----------------------------------------------------------------------
271 * IDE ATAPI Configuration
274 #define CONFIG_ATAPI 1
275 #define CFG_IDE_MAXBUS 2
276 #define CFG_IDE_MAXDEVICE 4
277 #define CONFIG_ISO_PARTITION 1
279 #define CFG_ATA_BASE_ADDR 0xFE000000 /* was: via_get_base_addr() */
280 #define CFG_ATA_IDE0_OFFSET 0x1F0
281 #define CFG_ATA_IDE1_OFFSET 0x170
283 #define CFG_ATA_REG_OFFSET 0
284 #define CFG_ATA_DATA_OFFSET 0
285 #define CFG_ATA_ALT_OFFSET 0x0200
287 /*-----------------------------------------------------------------------
288 * Disk-On-Chip configuration
291 #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
293 #define CFG_DOC_SUPPORT_2000
294 #undef CFG_DOC_SUPPORT_MILLENNIUM
296 /*-----------------------------------------------------------------------
299 #define CONFIG_RTC_MC146818
301 /*-----------------------------------------------------------------------
302 * NS16550 Configuration
307 #define CFG_NS16550_COM1 0xFE0003F8
308 #define CFG_NS16550_COM2 0xFE0002F8
310 #define CFG_NS16550_REG_SIZE 1
312 /* base address for ISA I/O
314 #define CFG_ISA_IO_BASE_ADDRESS 0xFE000000
316 /* ISA Interrupt stuff (taken from JWL) */
318 #define ISA_INT1_OCW1 0x21
319 #define ISA_INT2_OCW1 0xA1
320 #define ISA_INT1_OCW2 0x20
321 #define ISA_INT2_OCW2 0xA0
322 #define ISA_INT1_OCW3 0x20
323 #define ISA_INT2_OCW3 0xA0
325 #define ISA_INT1_ICW1 0x20
326 #define ISA_INT2_ICW1 0xA0
327 #define ISA_INT1_ICW2 0x21
328 #define ISA_INT2_ICW2 0xA1
329 #define ISA_INT1_ICW3 0x21
330 #define ISA_INT2_ICW3 0xA1
331 #define ISA_INT1_ICW4 0x21
332 #define ISA_INT2_ICW4 0xA1
339 #define CONFIG_NET_MULTI
340 #define CFG_BOARD_ASM_INIT
341 #define CONFIG_LAST_STAGE_INIT
343 /* #define CONFIG_ETHADDR 00:09:D2:10:00:76 */
344 /* #define CONFIG_IPADDR 192.168.0.2 */
345 /* #define CONFIG_NETMASK 255.255.255.240 */
346 /* #define CONFIG_GATEWAYIP 192.168.0.3 */
349 /* #define CONFIG_BOOTP_RANDOM_DELAY */
350 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
351 CONFIG_BOOTP_BOOTFILESIZE)
356 #define CONFIG_USB_UHCI 1
357 #define CONFIG_USB_STORAGE 1
358 #define CONFIG_USB_KEYBOARD 1
359 #define CFG_DEVICE_DEREGISTER 1 /* needed by CONFIG_USB_KEYBOARD */
364 #define CONFIG_BOOTDELAY 5 /* Boot automatically after five seconds */
365 #define CONFIG_PREBOOT ""
366 #define CONFIG_BOOTCOMMAND "fdcboot; diskboot"
367 #define CONFIG_MENUPROMPT "Press any key to interrupt autoboot: %2d "
368 #define CONFIG_MENUKEY ' '
369 #define CONFIG_MENUCOMMAND "menu"
370 /* #define CONFIG_AUTOBOOT_KEYED */
375 #define CONFIG_EXTRA_ENV_SETTINGS \
380 "ide_cd_timeout=30\0" \
383 "pci_irqa_select=edge\0" \
385 "pci_irqb_select=edge\0" \
387 "pci_irqc_select=edge\0" \
389 "pci_irqd_select=edge\0"
392 /* #define CONFIG_MII 1 */
393 /* #define CONFIG_BITBANGMII 1 */
396 #endif /* __CONFIG_H */