git.sur5r.net Git - u-boot/blob - include/configs/B4860QDS.h

   1 /*
   2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_DISPLAY_BOARDINFO
  11
  12 /*
  13  * B4860 QDS board configuration file
  14  */
  15 #define CONFIG_B4860QDS
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #define CONFIG_SYS_FSL_PBL_PBI  $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
  19 #define CONFIG_SYS_FSL_PBL_RCW  $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
  20 #ifndef CONFIG_NAND
  21 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  22 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  23 #else
  24 #define CONFIG_SPL_SERIAL_SUPPORT
  25 #define CONFIG_SPL_FLUSH_IMAGE
  26 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  27 #define CONFIG_FSL_LAW                 /* Use common FSL init code */
  28 #define CONFIG_SYS_TEXT_BASE            0x00201000
  29 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  30 #define CONFIG_SPL_PAD_TO               0x40000
  31 #define CONFIG_SPL_MAX_SIZE             0x28000
  32 #define RESET_VECTOR_OFFSET             0x27FFC
  33 #define BOOT_PAGE_OFFSET                0x27000
  34 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  35 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  36 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  37 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  38 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  39 #define CONFIG_SPL_NAND_BOOT
  40 #ifdef CONFIG_SPL_BUILD
  41 #define CONFIG_SPL_SKIP_RELOCATE
  42 #define CONFIG_SPL_COMMON_INIT_DDR
  43 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  44 #define CONFIG_SYS_NO_FLASH
  45 #endif
  46 #endif
  47 #endif
  48
  49 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  50 /* Set 1M boot space */
  51 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  52 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  53                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  54 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  55 #define CONFIG_SYS_NO_FLASH
  56 #endif
  57
  58 /* High Level Configuration Options */
  59 #define CONFIG_BOOKE
  60 #define CONFIG_E500                     /* BOOKE e500 family */
  61 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  62 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  63 #define CONFIG_MP                       /* support multiple processors */
  64
  65 #ifndef CONFIG_SYS_TEXT_BASE
  66 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  67 #endif
  68
  69 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  70 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  71 #endif
  72
  73 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  74 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  75 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
  76 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
  77 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  78 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  79 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  80 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  81
  82 #ifndef CONFIG_PPC_B4420
  83 #define CONFIG_SYS_SRIO
  84 #define CONFIG_SRIO1                    /* SRIO port 1 */
  85 #define CONFIG_SRIO2                    /* SRIO port 2 */
  86 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  87 #endif
  88
  89 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  90
  91 /* I2C bus multiplexer */
  92 #define I2C_MUX_PCA_ADDR                0x77
  93
  94 /* VSC Crossbar switches */
  95 #define CONFIG_VSC_CROSSBAR
  96 #define I2C_CH_DEFAULT                  0x8
  97 #define I2C_CH_VSC3316                  0xc
  98 #define I2C_CH_VSC3308                  0xd
  99
 100 #define VSC3316_TX_ADDRESS              0x70
 101 #define VSC3316_RX_ADDRESS              0x71
 102 #define VSC3308_TX_ADDRESS              0x02
 103 #define VSC3308_RX_ADDRESS              0x03
 104
 105 /* IDT clock synthesizers */
 106 #define CONFIG_IDT8T49N222A
 107 #define I2C_CH_IDT                     0x9
 108
 109 #define IDT_SERDES1_ADDRESS            0x6E
 110 #define IDT_SERDES2_ADDRESS            0x6C
 111
 112 /* Voltage monitor on channel 2*/
 113 #define I2C_MUX_CH_VOL_MONITOR          0xa
 114 #define I2C_VOL_MONITOR_ADDR            0x40
 115 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 116 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 117 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 118
 119 #define CONFIG_ZM7300
 120 #define I2C_MUX_CH_DPM                  0xa
 121 #define I2C_DPM_ADDR                    0x28
 122
 123 #define CONFIG_ENV_OVERWRITE
 124
 125 #ifdef CONFIG_SYS_NO_FLASH
 126 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
 127 #define CONFIG_ENV_IS_NOWHERE
 128 #endif
 129 #else
 130 #define CONFIG_FLASH_CFI_DRIVER
 131 #define CONFIG_SYS_FLASH_CFI
 132 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 133 #endif
 134
 135 #if defined(CONFIG_SPIFLASH)
 136 #define CONFIG_SYS_EXTRA_ENV_RELOC
 137 #define CONFIG_ENV_IS_IN_SPI_FLASH
 138 #define CONFIG_ENV_SPI_BUS              0
 139 #define CONFIG_ENV_SPI_CS               0
 140 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 141 #define CONFIG_ENV_SPI_MODE             0
 142 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 143 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 144 #define CONFIG_ENV_SECT_SIZE            0x10000
 145 #elif defined(CONFIG_SDCARD)
 146 #define CONFIG_SYS_EXTRA_ENV_RELOC
 147 #define CONFIG_ENV_IS_IN_MMC
 148 #define CONFIG_SYS_MMC_ENV_DEV          0
 149 #define CONFIG_ENV_SIZE                 0x2000
 150 #define CONFIG_ENV_OFFSET               (512 * 1097)
 151 #elif defined(CONFIG_NAND)
 152 #define CONFIG_SYS_EXTRA_ENV_RELOC
 153 #define CONFIG_ENV_IS_IN_NAND
 154 #define CONFIG_ENV_SIZE                 0x2000
 155 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 156 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 157 #define CONFIG_ENV_IS_IN_REMOTE
 158 #define CONFIG_ENV_ADDR         0xffe20000
 159 #define CONFIG_ENV_SIZE         0x2000
 160 #elif defined(CONFIG_ENV_IS_NOWHERE)
 161 #define CONFIG_ENV_SIZE         0x2000
 162 #else
 163 #define CONFIG_ENV_IS_IN_FLASH
 164 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 165 #define CONFIG_ENV_SIZE         0x2000
 166 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 167 #endif
 168
 169 #ifndef __ASSEMBLY__
 170 unsigned long get_board_sys_clk(void);
 171 unsigned long get_board_ddr_clk(void);
 172 #endif
 173 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
 174 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 175
 176 /*
 177  * These can be toggled for performance analysis, otherwise use default.
 178  */
 179 #define CONFIG_SYS_CACHE_STASHING
 180 #define CONFIG_BTB                      /* toggle branch predition */
 181 #define CONFIG_DDR_ECC
 182 #ifdef CONFIG_DDR_ECC
 183 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 184 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 185 #endif
 186
 187 #define CONFIG_ENABLE_36BIT_PHYS
 188
 189 #ifdef CONFIG_PHYS_64BIT
 190 #define CONFIG_ADDR_MAP
 191 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 192 #endif
 193
 194 #if 0
 195 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 196 #endif
 197 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 198 #define CONFIG_SYS_MEMTEST_END          0x00400000
 199 #define CONFIG_SYS_ALT_MEMTEST
 200 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 201
 202 /*
 203  *  Config the L3 Cache as L3 SRAM
 204  */
 205 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 206 #define CONFIG_SYS_L3_SIZE              256 << 10
 207 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 208 #ifdef CONFIG_NAND
 209 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 210 #endif
 211 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 212 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 213 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 214 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 215
 216 #ifdef CONFIG_PHYS_64BIT
 217 #define CONFIG_SYS_DCSRBAR              0xf0000000
 218 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 219 #endif
 220
 221 /* EEPROM */
 222 #define CONFIG_ID_EEPROM
 223 #define CONFIG_SYS_I2C_EEPROM_NXID
 224 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 225 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 226 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 227 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 228 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 229
 230 /*
 231  * DDR Setup
 232  */
 233 #define CONFIG_VERY_BIG_RAM
 234 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 235 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 236
 237 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
 238 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 239 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 240
 241 #define CONFIG_DDR_SPD
 242 #define CONFIG_SYS_DDR_RAW_TIMING
 243 #define CONFIG_SYS_FSL_DDR3
 244 #ifndef CONFIG_SPL_BUILD
 245 #define CONFIG_FSL_DDR_INTERACTIVE
 246 #endif
 247
 248 #define CONFIG_SYS_SPD_BUS_NUM  0
 249 #define SPD_EEPROM_ADDRESS1     0x51
 250 #define SPD_EEPROM_ADDRESS2     0x53
 251
 252 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 253 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 254
 255 /*
 256  * IFC Definitions
 257  */
 258 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 259 #ifdef CONFIG_PHYS_64BIT
 260 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 261 #else
 262 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 263 #endif
 264
 265 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 266 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 267                                 + 0x8000000) | \
 268                                 CSPR_PORT_SIZE_16 | \
 269                                 CSPR_MSEL_NOR | \
 270                                 CSPR_V)
 271 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 272 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 273                                 CSPR_PORT_SIZE_16 | \
 274                                 CSPR_MSEL_NOR | \
 275                                 CSPR_V)
 276 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128 * 1024 * 1024)
 277 /* NOR Flash Timing Params */
 278 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(4)
 279 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x01) | \
 280                                 FTIM0_NOR_TEADC(0x04) | \
 281                                 FTIM0_NOR_TEAHC(0x20))
 282 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 283                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 284                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 285 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x01) | \
 286                                 FTIM2_NOR_TCH(0x0E) | \
 287                                 FTIM2_NOR_TWPH(0x0E) | \
 288                                 FTIM2_NOR_TWP(0x1c))
 289 #define CONFIG_SYS_NOR_FTIM3    0x0
 290
 291 #define CONFIG_SYS_FLASH_QUIET_TEST
 292 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 293
 294 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 295 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 296 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 297 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 298
 299 #define CONFIG_SYS_FLASH_EMPTY_INFO
 300 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 301                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 302
 303 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 304 #define CONFIG_FSL_QIXIS_V2
 305 #define QIXIS_BASE              0xffdf0000
 306 #ifdef CONFIG_PHYS_64BIT
 307 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 308 #else
 309 #define QIXIS_BASE_PHYS         QIXIS_BASE
 310 #endif
 311 #define QIXIS_LBMAP_SWITCH              0x01
 312 #define QIXIS_LBMAP_MASK                0x0f
 313 #define QIXIS_LBMAP_SHIFT               0
 314 #define QIXIS_LBMAP_DFLTBANK            0x00
 315 #define QIXIS_LBMAP_ALTBANK             0x02
 316 #define QIXIS_RST_CTL_RESET             0x31
 317 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 318 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 319 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 320
 321 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 322 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 323                                 | CSPR_PORT_SIZE_8 \
 324                                 | CSPR_MSEL_GPCM \
 325                                 | CSPR_V)
 326 #define CONFIG_SYS_AMASK3       IFC_AMASK(4 * 1024)
 327 #define CONFIG_SYS_CSOR3        0x0
 328 /* QIXIS Timing parameters for IFC CS3 */
 329 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 330                                         FTIM0_GPCM_TEADC(0x0e) | \
 331                                         FTIM0_GPCM_TEAHC(0x0e))
 332 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 333                                         FTIM1_GPCM_TRAD(0x1f))
 334 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 335                                         FTIM2_GPCM_TCH(0x8) | \
 336                                         FTIM2_GPCM_TWP(0x1f))
 337 #define CONFIG_SYS_CS3_FTIM3            0x0
 338
 339 /* NAND Flash on IFC */
 340 #define CONFIG_NAND_FSL_IFC
 341 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 342 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 343 #define CONFIG_SYS_NAND_BASE            0xff800000
 344 #ifdef CONFIG_PHYS_64BIT
 345 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 346 #else
 347 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 348 #endif
 349
 350 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 351 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 352                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 353                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 354                                 | CSPR_V)
 355 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 356
 357 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 358                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 359                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 360                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 361                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 362                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 363                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 364
 365 #define CONFIG_SYS_NAND_ONFI_DETECTION
 366
 367 /* ONFI NAND Flash mode0 Timing Params */
 368 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 369                                         FTIM0_NAND_TWP(0x18)   | \
 370                                         FTIM0_NAND_TWCHT(0x07) | \
 371                                         FTIM0_NAND_TWH(0x0a))
 372 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 373                                         FTIM1_NAND_TWBE(0x39)  | \
 374                                         FTIM1_NAND_TRR(0x0e)   | \
 375                                         FTIM1_NAND_TRP(0x18))
 376 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 377                                         FTIM2_NAND_TREH(0x0a) | \
 378                                         FTIM2_NAND_TWHRE(0x1e))
 379 #define CONFIG_SYS_NAND_FTIM3           0x0
 380
 381 #define CONFIG_SYS_NAND_DDR_LAW         11
 382
 383 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 384 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 385 #define CONFIG_CMD_NAND
 386
 387 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 388
 389 #if defined(CONFIG_NAND)
 390 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 391 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 392 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 393 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 394 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 395 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 396 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 397 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 398 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 399 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 400 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 401 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 402 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 403 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 404 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 405 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 406 #else
 407 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 408 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 409 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 410 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 411 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 412 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 413 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 414 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 415 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 416 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 417 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 418 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 419 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 420 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 421 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 422 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 423 #endif
 424 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 425 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 426 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 427 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 428 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 429 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 430 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 431 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 432
 433 #ifdef CONFIG_SPL_BUILD
 434 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 435 #else
 436 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 437 #endif
 438
 439 #if defined(CONFIG_RAMBOOT_PBL)
 440 #define CONFIG_SYS_RAMBOOT
 441 #endif
 442
 443 #define CONFIG_BOARD_EARLY_INIT_R
 444 #define CONFIG_MISC_INIT_R
 445
 446 #define CONFIG_HWCONFIG
 447
 448 /* define to use L1 as initial stack */
 449 #define CONFIG_L1_INIT_RAM
 450 #define CONFIG_SYS_INIT_RAM_LOCK
 451 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 452 #ifdef CONFIG_PHYS_64BIT
 453 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 454 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 455 /* The assembler doesn't like typecast */
 456 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 457         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 458           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 459 #else
 460 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 461 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 462 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 463 #endif
 464 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 465
 466 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 467                                         GENERATED_GBL_DATA_SIZE)
 468 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 469
 470 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 471 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 472
 473 /* Serial Port - controlled on board with jumper J8
 474  * open - index 2
 475  * shorted - index 1
 476  */
 477 #define CONFIG_CONS_INDEX       1
 478 #define CONFIG_SYS_NS16550_SERIAL
 479 #define CONFIG_SYS_NS16550_REG_SIZE     1
 480 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 481
 482 #define CONFIG_SYS_BAUDRATE_TABLE       \
 483         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 484
 485 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 486 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 487 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 488 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 489 #ifndef CONFIG_SPL_BUILD
 490 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 491 #endif
 492
 493 /* I2C */
 494 #define CONFIG_SYS_I2C
 495 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 496 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
 497 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 498 #define CONFIG_SYS_FSL_I2C2_SPEED       400000  /* I2C speed in Hz */
 499 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 500 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 501 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x119000
 502
 503 /*
 504  * RTC configuration
 505  */
 506 #define RTC
 507 #define CONFIG_RTC_DS3231               1
 508 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 509
 510 /*
 511  * RapidIO
 512  */
 513 #ifdef CONFIG_SYS_SRIO
 514 #ifdef CONFIG_SRIO1
 515 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 516 #ifdef CONFIG_PHYS_64BIT
 517 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 518 #else
 519 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 520 #endif
 521 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 522 #endif
 523
 524 #ifdef CONFIG_SRIO2
 525 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 526 #ifdef CONFIG_PHYS_64BIT
 527 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 528 #else
 529 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 530 #endif
 531 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 532 #endif
 533 #endif
 534
 535 /*
 536  * for slave u-boot IMAGE instored in master memory space,
 537  * PHYS must be aligned based on the SIZE
 538  */
 539 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 540 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 541 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 542 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 543 /*
 544  * for slave UCODE and ENV instored in master memory space,
 545  * PHYS must be aligned based on the SIZE
 546  */
 547 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 548 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 549 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 550
 551 /* slave core release by master*/
 552 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 553 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 554
 555 /*
 556  * SRIO_PCIE_BOOT - SLAVE
 557  */
 558 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 559 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 560 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 561                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 562 #endif
 563
 564 /*
 565  * eSPI - Enhanced SPI
 566  */
 567 #define CONFIG_SF_DEFAULT_SPEED         10000000
 568 #define CONFIG_SF_DEFAULT_MODE          0
 569
 570 /*
 571  * MAPLE
 572  */
 573 #ifdef CONFIG_PHYS_64BIT
 574 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xFA0000000ull
 575 #else
 576 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xA0000000
 577 #endif
 578
 579 /*
 580  * General PCI
 581  * Memory space is mapped 1-1, but I/O space must start from 0.
 582  */
 583
 584 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 585 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 586 #ifdef CONFIG_PHYS_64BIT
 587 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 588 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 589 #else
 590 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 591 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 592 #endif
 593 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 594 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 595 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 596 #ifdef CONFIG_PHYS_64BIT
 597 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 598 #else
 599 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 600 #endif
 601 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 602
 603 /* Qman/Bman */
 604 #ifndef CONFIG_NOBQFMAN
 605 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 606 #define CONFIG_SYS_BMAN_NUM_PORTALS     25
 607 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 608 #ifdef CONFIG_PHYS_64BIT
 609 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 610 #else
 611 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 612 #endif
 613 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 614 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 615 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 616 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 617 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 618 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 619                                         CONFIG_SYS_BMAN_CENA_SIZE)
 620 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 621 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 622 #define CONFIG_SYS_QMAN_NUM_PORTALS     25
 623 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 624 #ifdef CONFIG_PHYS_64BIT
 625 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 626 #else
 627 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 628 #endif
 629 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 630 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 631 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 632 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 633 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 634 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 635                                         CONFIG_SYS_QMAN_CENA_SIZE)
 636 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 637 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 638
 639 #define CONFIG_SYS_DPAA_FMAN
 640
 641 #define CONFIG_SYS_DPAA_RMAN
 642
 643 /* Default address of microcode for the Linux Fman driver */
 644 #if defined(CONFIG_SPIFLASH)
 645 /*
 646  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 647  * env, so we got 0x110000.
 648  */
 649 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 650 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 651 #elif defined(CONFIG_SDCARD)
 652 /*
 653  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 654  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
 655  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
 656  */
 657 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 658 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
 659 #elif defined(CONFIG_NAND)
 660 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 661 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
 662 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 663 /*
 664  * Slave has no ucode locally, it can fetch this from remote. When implementing
 665  * in two corenet boards, slave's ucode could be stored in master's memory
 666  * space, the address can be mapped from slave TLB->slave LAW->
 667  * slave SRIO or PCIE outbound window->master inbound window->
 668  * master LAW->the ucode address in master's memory space.
 669  */
 670 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 671 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 672 #else
 673 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 674 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 675 #endif
 676 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 677 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 678 #endif /* CONFIG_NOBQFMAN */
 679
 680 #ifdef CONFIG_SYS_DPAA_FMAN
 681 #define CONFIG_FMAN_ENET
 682 #define CONFIG_PHYLIB_10G
 683 #define CONFIG_PHY_VITESSE
 684 #define CONFIG_PHY_TERANETICS
 685 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 686 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
 687 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 688 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
 689 #endif
 690
 691 #ifdef CONFIG_PCI
 692 #define CONFIG_PCI_INDIRECT_BRIDGE
 693 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 694
 695 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 696 #define CONFIG_DOS_PARTITION
 697 #endif  /* CONFIG_PCI */
 698
 699 #ifdef CONFIG_FMAN_ENET
 700 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
 701 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
 702
 703 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
 704 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7       /*SLOT 1*/
 705 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6       /*SLOT 2*/
 706
 707 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 708 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 709 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 710 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 711
 712 #define CONFIG_MII              /* MII PHY management */
 713 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 714 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 715 #endif
 716
 717 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
 718
 719 /*
 720  * Environment
 721  */
 722 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 723 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 724
 725 /*
 726  * Command line configuration.
 727  */
 728 #define CONFIG_CMD_DATE
 729 #define CONFIG_CMD_EEPROM
 730 #define CONFIG_CMD_ERRATA
 731 #define CONFIG_CMD_IRQ
 732 #define CONFIG_CMD_REGINFO
 733
 734 #ifdef CONFIG_PCI
 735 #define CONFIG_CMD_PCI
 736 #endif
 737
 738 /* Hash command with SHA acceleration supported in hardware */
 739 #ifdef CONFIG_FSL_CAAM
 740 #define CONFIG_CMD_HASH
 741 #define CONFIG_SHA_HW_ACCEL
 742 #endif
 743
 744 /*
 745 * USB
 746 */
 747 #define CONFIG_HAS_FSL_DR_USB
 748
 749 #ifdef CONFIG_HAS_FSL_DR_USB
 750 #define CONFIG_USB_EHCI
 751
 752 #ifdef CONFIG_USB_EHCI
 753 #define CONFIG_USB_EHCI_FSL
 754 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 755 #endif
 756 #endif
 757
 758 /*
 759  * Miscellaneous configurable options
 760  */
 761 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 762 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 763 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 764 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 765 #ifdef CONFIG_CMD_KGDB
 766 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 767 #else
 768 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 769 #endif
 770 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 771 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 772 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 773
 774 /*
 775  * For booting Linux, the board info and command line data
 776  * have to be in the first 64 MB of memory, since this is
 777  * the maximum mapped by the Linux kernel during initialization.
 778  */
 779 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 780 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 781
 782 #ifdef CONFIG_CMD_KGDB
 783 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 784 #endif
 785
 786 /*
 787  * Environment Configuration
 788  */
 789 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 790 #define CONFIG_BOOTFILE         "uImage"
 791 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 792
 793 /* default location for tftp and bootm */
 794 #define CONFIG_LOADADDR         1000000
 795
 796
 797 #define CONFIG_BAUDRATE 115200
 798
 799 #define __USB_PHY_TYPE  ulpi
 800
 801 #ifdef CONFIG_PPC_B4860
 802 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,"     \
 803                         "bank_intlv=cs0_cs1;"   \
 804                         "en_cpc:cpc2;"
 805 #else
 806 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
 807 #endif
 808
 809 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 810         HWCONFIG                                                \
 811         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 812         "netdev=eth0\0"                                         \
 813         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 814         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"                     \
 815         "tftpflash=tftpboot $loadaddr $uboot && "               \
 816         "protect off $ubootaddr +$filesize && "                 \
 817         "erase $ubootaddr +$filesize && "                       \
 818         "cp.b $loadaddr $ubootaddr $filesize && "               \
 819         "protect on $ubootaddr +$filesize && "                  \
 820         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 821         "consoledev=ttyS0\0"                                    \
 822         "ramdiskaddr=2000000\0"                                 \
 823         "ramdiskfile=b4860qds/ramdisk.uboot\0"                  \
 824         "fdtaddr=1e00000\0"                                     \
 825         "fdtfile=b4860qds/b4860qds.dtb\0"                               \
 826         "bdev=sda3\0"
 827
 828 /* For emulation this causes u-boot to jump to the start of the proof point
 829    app code automatically */
 830 #define CONFIG_PROOF_POINTS                     \
 831  "setenv bootargs root=/dev/$bdev rw "          \
 832  "console=$consoledev,$baudrate $othbootargs;"  \
 833  "cpu 1 release 0x29000000 - - -;"              \
 834  "cpu 2 release 0x29000000 - - -;"              \
 835  "cpu 3 release 0x29000000 - - -;"              \
 836  "cpu 4 release 0x29000000 - - -;"              \
 837  "cpu 5 release 0x29000000 - - -;"              \
 838  "cpu 6 release 0x29000000 - - -;"              \
 839  "cpu 7 release 0x29000000 - - -;"              \
 840  "go 0x29000000"
 841
 842 #define CONFIG_HVBOOT   \
 843  "setenv bootargs config-addr=0x60000000; "     \
 844  "bootm 0x01000000 - 0x00f00000"
 845
 846 #define CONFIG_ALU                              \
 847  "setenv bootargs root=/dev/$bdev rw "          \
 848  "console=$consoledev,$baudrate $othbootargs;"  \
 849  "cpu 1 release 0x01000000 - - -;"              \
 850  "cpu 2 release 0x01000000 - - -;"              \
 851  "cpu 3 release 0x01000000 - - -;"              \
 852  "cpu 4 release 0x01000000 - - -;"              \
 853  "cpu 5 release 0x01000000 - - -;"              \
 854  "cpu 6 release 0x01000000 - - -;"              \
 855  "cpu 7 release 0x01000000 - - -;"              \
 856  "go 0x01000000"
 857
 858 #define CONFIG_LINUX                            \
 859  "setenv bootargs root=/dev/ram rw "            \
 860  "console=$consoledev,$baudrate $othbootargs;"  \
 861  "setenv ramdiskaddr 0x02000000;"               \
 862  "setenv fdtaddr 0x01e00000;"                   \
 863  "setenv loadaddr 0x1000000;"                   \
 864  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 865
 866 #define CONFIG_HDBOOT                                   \
 867         "setenv bootargs root=/dev/$bdev rw "           \
 868         "console=$consoledev,$baudrate $othbootargs;"   \
 869         "tftp $loadaddr $bootfile;"                     \
 870         "tftp $fdtaddr $fdtfile;"                       \
 871         "bootm $loadaddr - $fdtaddr"
 872
 873 #define CONFIG_NFSBOOTCOMMAND                   \
 874         "setenv bootargs root=/dev/nfs rw "     \
 875         "nfsroot=$serverip:$rootpath "          \
 876         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 877         "console=$consoledev,$baudrate $othbootargs;"   \
 878         "tftp $loadaddr $bootfile;"             \
 879         "tftp $fdtaddr $fdtfile;"               \
 880         "bootm $loadaddr - $fdtaddr"
 881
 882 #define CONFIG_RAMBOOTCOMMAND                           \
 883         "setenv bootargs root=/dev/ram rw "             \
 884         "console=$consoledev,$baudrate $othbootargs;"   \
 885         "tftp $ramdiskaddr $ramdiskfile;"               \
 886         "tftp $loadaddr $bootfile;"                     \
 887         "tftp $fdtaddr $fdtfile;"                       \
 888         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 889
 890 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 891
 892 #include <asm/fsl_secure_boot.h>
 893
 894 #endif  /* __CONFIG_H */