git.sur5r.net Git - u-boot/blob - include/configs/B4860QDS.h

   1 /*
   2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_DISPLAY_BOARDINFO
  11
  12 /*
  13  * B4860 QDS board configuration file
  14  */
  15 #define CONFIG_B4860QDS
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #define CONFIG_SYS_FSL_PBL_PBI  $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
  19 #define CONFIG_SYS_FSL_PBL_RCW  $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
  20 #ifndef CONFIG_NAND
  21 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  22 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  23 #else
  24 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  25 #define CONFIG_SPL_SERIAL_SUPPORT
  26 #define CONFIG_SPL_FLUSH_IMAGE
  27 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  28 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  29 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  30 #define CONFIG_SPL_I2C_SUPPORT
  31 #define CONFIG_FSL_LAW                 /* Use common FSL init code */
  32 #define CONFIG_SYS_TEXT_BASE            0x00201000
  33 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  34 #define CONFIG_SPL_PAD_TO               0x40000
  35 #define CONFIG_SPL_MAX_SIZE             0x28000
  36 #define RESET_VECTOR_OFFSET             0x27FFC
  37 #define BOOT_PAGE_OFFSET                0x27000
  38 #define CONFIG_SPL_NAND_SUPPORT
  39 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  40 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  41 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  42 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  43 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  44 #define CONFIG_SPL_NAND_BOOT
  45 #ifdef CONFIG_SPL_BUILD
  46 #define CONFIG_SPL_SKIP_RELOCATE
  47 #define CONFIG_SPL_COMMON_INIT_DDR
  48 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  49 #define CONFIG_SYS_NO_FLASH
  50 #endif
  51 #endif
  52 #endif
  53
  54 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  55 /* Set 1M boot space */
  56 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  57 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  58                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  59 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  60 #define CONFIG_SYS_NO_FLASH
  61 #endif
  62
  63 /* High Level Configuration Options */
  64 #define CONFIG_BOOKE
  65 #define CONFIG_E500                     /* BOOKE e500 family */
  66 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  67 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  68 #define CONFIG_MP                       /* support multiple processors */
  69
  70 #ifndef CONFIG_SYS_TEXT_BASE
  71 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  72 #endif
  73
  74 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  75 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  76 #endif
  77
  78 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  79 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  80 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
  81 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
  82 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  83 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  84 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  85 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  86
  87 #ifndef CONFIG_PPC_B4420
  88 #define CONFIG_SYS_SRIO
  89 #define CONFIG_SRIO1                    /* SRIO port 1 */
  90 #define CONFIG_SRIO2                    /* SRIO port 2 */
  91 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  92 #endif
  93
  94 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  95
  96 /* I2C bus multiplexer */
  97 #define I2C_MUX_PCA_ADDR                0x77
  98
  99 /* VSC Crossbar switches */
 100 #define CONFIG_VSC_CROSSBAR
 101 #define I2C_CH_DEFAULT                  0x8
 102 #define I2C_CH_VSC3316                  0xc
 103 #define I2C_CH_VSC3308                  0xd
 104
 105 #define VSC3316_TX_ADDRESS              0x70
 106 #define VSC3316_RX_ADDRESS              0x71
 107 #define VSC3308_TX_ADDRESS              0x02
 108 #define VSC3308_RX_ADDRESS              0x03
 109
 110 /* IDT clock synthesizers */
 111 #define CONFIG_IDT8T49N222A
 112 #define I2C_CH_IDT                     0x9
 113
 114 #define IDT_SERDES1_ADDRESS            0x6E
 115 #define IDT_SERDES2_ADDRESS            0x6C
 116
 117 /* Voltage monitor on channel 2*/
 118 #define I2C_MUX_CH_VOL_MONITOR          0xa
 119 #define I2C_VOL_MONITOR_ADDR            0x40
 120 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 121 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 122 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 123
 124 #define CONFIG_ZM7300
 125 #define I2C_MUX_CH_DPM                  0xa
 126 #define I2C_DPM_ADDR                    0x28
 127
 128 #define CONFIG_ENV_OVERWRITE
 129
 130 #ifdef CONFIG_SYS_NO_FLASH
 131 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
 132 #define CONFIG_ENV_IS_NOWHERE
 133 #endif
 134 #else
 135 #define CONFIG_FLASH_CFI_DRIVER
 136 #define CONFIG_SYS_FLASH_CFI
 137 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 138 #endif
 139
 140 #if defined(CONFIG_SPIFLASH)
 141 #define CONFIG_SYS_EXTRA_ENV_RELOC
 142 #define CONFIG_ENV_IS_IN_SPI_FLASH
 143 #define CONFIG_ENV_SPI_BUS              0
 144 #define CONFIG_ENV_SPI_CS               0
 145 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 146 #define CONFIG_ENV_SPI_MODE             0
 147 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 148 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 149 #define CONFIG_ENV_SECT_SIZE            0x10000
 150 #elif defined(CONFIG_SDCARD)
 151 #define CONFIG_SYS_EXTRA_ENV_RELOC
 152 #define CONFIG_ENV_IS_IN_MMC
 153 #define CONFIG_SYS_MMC_ENV_DEV          0
 154 #define CONFIG_ENV_SIZE                 0x2000
 155 #define CONFIG_ENV_OFFSET               (512 * 1097)
 156 #elif defined(CONFIG_NAND)
 157 #define CONFIG_SYS_EXTRA_ENV_RELOC
 158 #define CONFIG_ENV_IS_IN_NAND
 159 #define CONFIG_ENV_SIZE                 0x2000
 160 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 161 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 162 #define CONFIG_ENV_IS_IN_REMOTE
 163 #define CONFIG_ENV_ADDR         0xffe20000
 164 #define CONFIG_ENV_SIZE         0x2000
 165 #elif defined(CONFIG_ENV_IS_NOWHERE)
 166 #define CONFIG_ENV_SIZE         0x2000
 167 #else
 168 #define CONFIG_ENV_IS_IN_FLASH
 169 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 170 #define CONFIG_ENV_SIZE         0x2000
 171 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 172 #endif
 173
 174 #ifndef __ASSEMBLY__
 175 unsigned long get_board_sys_clk(void);
 176 unsigned long get_board_ddr_clk(void);
 177 #endif
 178 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
 179 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 180
 181 /*
 182  * These can be toggled for performance analysis, otherwise use default.
 183  */
 184 #define CONFIG_SYS_CACHE_STASHING
 185 #define CONFIG_BTB                      /* toggle branch predition */
 186 #define CONFIG_DDR_ECC
 187 #ifdef CONFIG_DDR_ECC
 188 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 189 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 190 #endif
 191
 192 #define CONFIG_ENABLE_36BIT_PHYS
 193
 194 #ifdef CONFIG_PHYS_64BIT
 195 #define CONFIG_ADDR_MAP
 196 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 197 #endif
 198
 199 #if 0
 200 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 201 #endif
 202 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 203 #define CONFIG_SYS_MEMTEST_END          0x00400000
 204 #define CONFIG_SYS_ALT_MEMTEST
 205 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 206
 207 /*
 208  *  Config the L3 Cache as L3 SRAM
 209  */
 210 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 211 #define CONFIG_SYS_L3_SIZE              256 << 10
 212 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 213 #ifdef CONFIG_NAND
 214 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 215 #endif
 216 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 217 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 218 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 219 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 220
 221 #ifdef CONFIG_PHYS_64BIT
 222 #define CONFIG_SYS_DCSRBAR              0xf0000000
 223 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 224 #endif
 225
 226 /* EEPROM */
 227 #define CONFIG_ID_EEPROM
 228 #define CONFIG_SYS_I2C_EEPROM_NXID
 229 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 230 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 231 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 232 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 233 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 234
 235 /*
 236  * DDR Setup
 237  */
 238 #define CONFIG_VERY_BIG_RAM
 239 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 240 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 241
 242 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
 243 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 244 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 245
 246 #define CONFIG_DDR_SPD
 247 #define CONFIG_SYS_DDR_RAW_TIMING
 248 #define CONFIG_SYS_FSL_DDR3
 249 #ifndef CONFIG_SPL_BUILD
 250 #define CONFIG_FSL_DDR_INTERACTIVE
 251 #endif
 252
 253 #define CONFIG_SYS_SPD_BUS_NUM  0
 254 #define SPD_EEPROM_ADDRESS1     0x51
 255 #define SPD_EEPROM_ADDRESS2     0x53
 256
 257 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 258 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 259
 260 /*
 261  * IFC Definitions
 262  */
 263 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 264 #ifdef CONFIG_PHYS_64BIT
 265 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 266 #else
 267 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 268 #endif
 269
 270 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 271 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 272                                 + 0x8000000) | \
 273                                 CSPR_PORT_SIZE_16 | \
 274                                 CSPR_MSEL_NOR | \
 275                                 CSPR_V)
 276 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 277 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 278                                 CSPR_PORT_SIZE_16 | \
 279                                 CSPR_MSEL_NOR | \
 280                                 CSPR_V)
 281 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128 * 1024 * 1024)
 282 /* NOR Flash Timing Params */
 283 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(4)
 284 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x01) | \
 285                                 FTIM0_NOR_TEADC(0x04) | \
 286                                 FTIM0_NOR_TEAHC(0x20))
 287 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 288                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 289                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 290 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x01) | \
 291                                 FTIM2_NOR_TCH(0x0E) | \
 292                                 FTIM2_NOR_TWPH(0x0E) | \
 293                                 FTIM2_NOR_TWP(0x1c))
 294 #define CONFIG_SYS_NOR_FTIM3    0x0
 295
 296 #define CONFIG_SYS_FLASH_QUIET_TEST
 297 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 298
 299 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 300 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 301 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 302 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 303
 304 #define CONFIG_SYS_FLASH_EMPTY_INFO
 305 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 306                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 307
 308 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 309 #define CONFIG_FSL_QIXIS_V2
 310 #define QIXIS_BASE              0xffdf0000
 311 #ifdef CONFIG_PHYS_64BIT
 312 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 313 #else
 314 #define QIXIS_BASE_PHYS         QIXIS_BASE
 315 #endif
 316 #define QIXIS_LBMAP_SWITCH              0x01
 317 #define QIXIS_LBMAP_MASK                0x0f
 318 #define QIXIS_LBMAP_SHIFT               0
 319 #define QIXIS_LBMAP_DFLTBANK            0x00
 320 #define QIXIS_LBMAP_ALTBANK             0x02
 321 #define QIXIS_RST_CTL_RESET             0x31
 322 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 323 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 324 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 325
 326 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 327 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 328                                 | CSPR_PORT_SIZE_8 \
 329                                 | CSPR_MSEL_GPCM \
 330                                 | CSPR_V)
 331 #define CONFIG_SYS_AMASK3       IFC_AMASK(4 * 1024)
 332 #define CONFIG_SYS_CSOR3        0x0
 333 /* QIXIS Timing parameters for IFC CS3 */
 334 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 335                                         FTIM0_GPCM_TEADC(0x0e) | \
 336                                         FTIM0_GPCM_TEAHC(0x0e))
 337 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 338                                         FTIM1_GPCM_TRAD(0x1f))
 339 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 340                                         FTIM2_GPCM_TCH(0x8) | \
 341                                         FTIM2_GPCM_TWP(0x1f))
 342 #define CONFIG_SYS_CS3_FTIM3            0x0
 343
 344 /* NAND Flash on IFC */
 345 #define CONFIG_NAND_FSL_IFC
 346 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 347 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 348 #define CONFIG_SYS_NAND_BASE            0xff800000
 349 #ifdef CONFIG_PHYS_64BIT
 350 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 351 #else
 352 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 353 #endif
 354
 355 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 356 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 357                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 358                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 359                                 | CSPR_V)
 360 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 361
 362 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 363                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 364                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 365                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 366                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 367                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 368                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 369
 370 #define CONFIG_SYS_NAND_ONFI_DETECTION
 371
 372 /* ONFI NAND Flash mode0 Timing Params */
 373 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 374                                         FTIM0_NAND_TWP(0x18)   | \
 375                                         FTIM0_NAND_TWCHT(0x07) | \
 376                                         FTIM0_NAND_TWH(0x0a))
 377 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 378                                         FTIM1_NAND_TWBE(0x39)  | \
 379                                         FTIM1_NAND_TRR(0x0e)   | \
 380                                         FTIM1_NAND_TRP(0x18))
 381 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 382                                         FTIM2_NAND_TREH(0x0a) | \
 383                                         FTIM2_NAND_TWHRE(0x1e))
 384 #define CONFIG_SYS_NAND_FTIM3           0x0
 385
 386 #define CONFIG_SYS_NAND_DDR_LAW         11
 387
 388 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 389 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 390 #define CONFIG_CMD_NAND
 391
 392 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 393
 394 #if defined(CONFIG_NAND)
 395 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 396 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 397 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 398 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 399 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 400 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 401 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 402 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 403 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 404 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 405 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 406 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 407 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 408 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 409 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 410 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 411 #else
 412 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 413 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 414 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 415 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 416 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 417 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 418 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 419 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 420 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 421 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 422 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 423 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 424 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 425 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 426 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 427 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 428 #endif
 429 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 430 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 431 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 432 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 433 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 434 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 435 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 436 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 437
 438 #ifdef CONFIG_SPL_BUILD
 439 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 440 #else
 441 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 442 #endif
 443
 444 #if defined(CONFIG_RAMBOOT_PBL)
 445 #define CONFIG_SYS_RAMBOOT
 446 #endif
 447
 448 #define CONFIG_BOARD_EARLY_INIT_R
 449 #define CONFIG_MISC_INIT_R
 450
 451 #define CONFIG_HWCONFIG
 452
 453 /* define to use L1 as initial stack */
 454 #define CONFIG_L1_INIT_RAM
 455 #define CONFIG_SYS_INIT_RAM_LOCK
 456 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 457 #ifdef CONFIG_PHYS_64BIT
 458 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 459 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 460 /* The assembler doesn't like typecast */
 461 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 462         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 463           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 464 #else
 465 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 466 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 467 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 468 #endif
 469 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 470
 471 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 472                                         GENERATED_GBL_DATA_SIZE)
 473 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 474
 475 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 476 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 477
 478 /* Serial Port - controlled on board with jumper J8
 479  * open - index 2
 480  * shorted - index 1
 481  */
 482 #define CONFIG_CONS_INDEX       1
 483 #define CONFIG_SYS_NS16550_SERIAL
 484 #define CONFIG_SYS_NS16550_REG_SIZE     1
 485 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 486
 487 #define CONFIG_SYS_BAUDRATE_TABLE       \
 488         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 489
 490 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 491 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 492 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 493 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 494 #ifndef CONFIG_SPL_BUILD
 495 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 496 #endif
 497
 498 /* I2C */
 499 #define CONFIG_SYS_I2C
 500 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 501 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
 502 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 503 #define CONFIG_SYS_FSL_I2C2_SPEED       400000  /* I2C speed in Hz */
 504 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 505 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 506 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x119000
 507
 508 /*
 509  * RTC configuration
 510  */
 511 #define RTC
 512 #define CONFIG_RTC_DS3231               1
 513 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 514
 515 /*
 516  * RapidIO
 517  */
 518 #ifdef CONFIG_SYS_SRIO
 519 #ifdef CONFIG_SRIO1
 520 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 521 #ifdef CONFIG_PHYS_64BIT
 522 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 523 #else
 524 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 525 #endif
 526 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 527 #endif
 528
 529 #ifdef CONFIG_SRIO2
 530 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 531 #ifdef CONFIG_PHYS_64BIT
 532 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 533 #else
 534 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 535 #endif
 536 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 537 #endif
 538 #endif
 539
 540 /*
 541  * for slave u-boot IMAGE instored in master memory space,
 542  * PHYS must be aligned based on the SIZE
 543  */
 544 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 545 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 546 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 547 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 548 /*
 549  * for slave UCODE and ENV instored in master memory space,
 550  * PHYS must be aligned based on the SIZE
 551  */
 552 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 553 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 554 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 555
 556 /* slave core release by master*/
 557 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 558 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 559
 560 /*
 561  * SRIO_PCIE_BOOT - SLAVE
 562  */
 563 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 564 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 565 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 566                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 567 #endif
 568
 569 /*
 570  * eSPI - Enhanced SPI
 571  */
 572 #define CONFIG_SF_DEFAULT_SPEED         10000000
 573 #define CONFIG_SF_DEFAULT_MODE          0
 574
 575 /*
 576  * MAPLE
 577  */
 578 #ifdef CONFIG_PHYS_64BIT
 579 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xFA0000000ull
 580 #else
 581 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xA0000000
 582 #endif
 583
 584 /*
 585  * General PCI
 586  * Memory space is mapped 1-1, but I/O space must start from 0.
 587  */
 588
 589 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 590 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 591 #ifdef CONFIG_PHYS_64BIT
 592 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 593 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 594 #else
 595 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 596 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 597 #endif
 598 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 599 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 600 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 601 #ifdef CONFIG_PHYS_64BIT
 602 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 603 #else
 604 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 605 #endif
 606 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 607
 608 /* Qman/Bman */
 609 #ifndef CONFIG_NOBQFMAN
 610 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 611 #define CONFIG_SYS_BMAN_NUM_PORTALS     25
 612 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 613 #ifdef CONFIG_PHYS_64BIT
 614 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 615 #else
 616 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 617 #endif
 618 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 619 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 620 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 621 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 622 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 623 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 624                                         CONFIG_SYS_BMAN_CENA_SIZE)
 625 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 626 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 627 #define CONFIG_SYS_QMAN_NUM_PORTALS     25
 628 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 629 #ifdef CONFIG_PHYS_64BIT
 630 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 631 #else
 632 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 633 #endif
 634 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 635 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 636 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 637 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 638 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 639 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 640                                         CONFIG_SYS_QMAN_CENA_SIZE)
 641 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 642 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 643
 644 #define CONFIG_SYS_DPAA_FMAN
 645
 646 #define CONFIG_SYS_DPAA_RMAN
 647
 648 /* Default address of microcode for the Linux Fman driver */
 649 #if defined(CONFIG_SPIFLASH)
 650 /*
 651  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 652  * env, so we got 0x110000.
 653  */
 654 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 655 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 656 #elif defined(CONFIG_SDCARD)
 657 /*
 658  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 659  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
 660  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
 661  */
 662 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 663 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
 664 #elif defined(CONFIG_NAND)
 665 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 666 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
 667 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 668 /*
 669  * Slave has no ucode locally, it can fetch this from remote. When implementing
 670  * in two corenet boards, slave's ucode could be stored in master's memory
 671  * space, the address can be mapped from slave TLB->slave LAW->
 672  * slave SRIO or PCIE outbound window->master inbound window->
 673  * master LAW->the ucode address in master's memory space.
 674  */
 675 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 676 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 677 #else
 678 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 679 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 680 #endif
 681 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 682 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 683 #endif /* CONFIG_NOBQFMAN */
 684
 685 #ifdef CONFIG_SYS_DPAA_FMAN
 686 #define CONFIG_FMAN_ENET
 687 #define CONFIG_PHYLIB_10G
 688 #define CONFIG_PHY_VITESSE
 689 #define CONFIG_PHY_TERANETICS
 690 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 691 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
 692 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 693 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
 694 #endif
 695
 696 #ifdef CONFIG_PCI
 697 #define CONFIG_PCI_INDIRECT_BRIDGE
 698 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 699
 700 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 701 #define CONFIG_DOS_PARTITION
 702 #endif  /* CONFIG_PCI */
 703
 704 #ifdef CONFIG_FMAN_ENET
 705 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
 706 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
 707
 708 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
 709 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7       /*SLOT 1*/
 710 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6       /*SLOT 2*/
 711
 712 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 713 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 714 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 715 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 716
 717 #define CONFIG_MII              /* MII PHY management */
 718 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 719 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 720 #endif
 721
 722 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
 723
 724 /*
 725  * Environment
 726  */
 727 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 728 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 729
 730 /*
 731  * Command line configuration.
 732  */
 733 #define CONFIG_CMD_DATE
 734 #define CONFIG_CMD_EEPROM
 735 #define CONFIG_CMD_ERRATA
 736 #define CONFIG_CMD_IRQ
 737 #define CONFIG_CMD_REGINFO
 738
 739 #ifdef CONFIG_PCI
 740 #define CONFIG_CMD_PCI
 741 #endif
 742
 743 /* Hash command with SHA acceleration supported in hardware */
 744 #ifdef CONFIG_FSL_CAAM
 745 #define CONFIG_CMD_HASH
 746 #define CONFIG_SHA_HW_ACCEL
 747 #endif
 748
 749 /*
 750 * USB
 751 */
 752 #define CONFIG_HAS_FSL_DR_USB
 753
 754 #ifdef CONFIG_HAS_FSL_DR_USB
 755 #define CONFIG_USB_EHCI
 756
 757 #ifdef CONFIG_USB_EHCI
 758 #define CONFIG_USB_EHCI_FSL
 759 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 760 #endif
 761 #endif
 762
 763 /*
 764  * Miscellaneous configurable options
 765  */
 766 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 767 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 768 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 769 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 770 #ifdef CONFIG_CMD_KGDB
 771 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 772 #else
 773 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 774 #endif
 775 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 776 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 777 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 778
 779 /*
 780  * For booting Linux, the board info and command line data
 781  * have to be in the first 64 MB of memory, since this is
 782  * the maximum mapped by the Linux kernel during initialization.
 783  */
 784 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 785 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 786
 787 #ifdef CONFIG_CMD_KGDB
 788 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 789 #endif
 790
 791 /*
 792  * Environment Configuration
 793  */
 794 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 795 #define CONFIG_BOOTFILE         "uImage"
 796 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 797
 798 /* default location for tftp and bootm */
 799 #define CONFIG_LOADADDR         1000000
 800
 801
 802 #define CONFIG_BAUDRATE 115200
 803
 804 #define __USB_PHY_TYPE  ulpi
 805
 806 #ifdef CONFIG_PPC_B4860
 807 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,"     \
 808                         "bank_intlv=cs0_cs1;"   \
 809                         "en_cpc:cpc2;"
 810 #else
 811 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
 812 #endif
 813
 814 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 815         HWCONFIG                                                \
 816         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 817         "netdev=eth0\0"                                         \
 818         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 819         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"                     \
 820         "tftpflash=tftpboot $loadaddr $uboot && "               \
 821         "protect off $ubootaddr +$filesize && "                 \
 822         "erase $ubootaddr +$filesize && "                       \
 823         "cp.b $loadaddr $ubootaddr $filesize && "               \
 824         "protect on $ubootaddr +$filesize && "                  \
 825         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 826         "consoledev=ttyS0\0"                                    \
 827         "ramdiskaddr=2000000\0"                                 \
 828         "ramdiskfile=b4860qds/ramdisk.uboot\0"                  \
 829         "fdtaddr=1e00000\0"                                     \
 830         "fdtfile=b4860qds/b4860qds.dtb\0"                               \
 831         "bdev=sda3\0"
 832
 833 /* For emulation this causes u-boot to jump to the start of the proof point
 834    app code automatically */
 835 #define CONFIG_PROOF_POINTS                     \
 836  "setenv bootargs root=/dev/$bdev rw "          \
 837  "console=$consoledev,$baudrate $othbootargs;"  \
 838  "cpu 1 release 0x29000000 - - -;"              \
 839  "cpu 2 release 0x29000000 - - -;"              \
 840  "cpu 3 release 0x29000000 - - -;"              \
 841  "cpu 4 release 0x29000000 - - -;"              \
 842  "cpu 5 release 0x29000000 - - -;"              \
 843  "cpu 6 release 0x29000000 - - -;"              \
 844  "cpu 7 release 0x29000000 - - -;"              \
 845  "go 0x29000000"
 846
 847 #define CONFIG_HVBOOT   \
 848  "setenv bootargs config-addr=0x60000000; "     \
 849  "bootm 0x01000000 - 0x00f00000"
 850
 851 #define CONFIG_ALU                              \
 852  "setenv bootargs root=/dev/$bdev rw "          \
 853  "console=$consoledev,$baudrate $othbootargs;"  \
 854  "cpu 1 release 0x01000000 - - -;"              \
 855  "cpu 2 release 0x01000000 - - -;"              \
 856  "cpu 3 release 0x01000000 - - -;"              \
 857  "cpu 4 release 0x01000000 - - -;"              \
 858  "cpu 5 release 0x01000000 - - -;"              \
 859  "cpu 6 release 0x01000000 - - -;"              \
 860  "cpu 7 release 0x01000000 - - -;"              \
 861  "go 0x01000000"
 862
 863 #define CONFIG_LINUX                            \
 864  "setenv bootargs root=/dev/ram rw "            \
 865  "console=$consoledev,$baudrate $othbootargs;"  \
 866  "setenv ramdiskaddr 0x02000000;"               \
 867  "setenv fdtaddr 0x01e00000;"                   \
 868  "setenv loadaddr 0x1000000;"                   \
 869  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 870
 871 #define CONFIG_HDBOOT                                   \
 872         "setenv bootargs root=/dev/$bdev rw "           \
 873         "console=$consoledev,$baudrate $othbootargs;"   \
 874         "tftp $loadaddr $bootfile;"                     \
 875         "tftp $fdtaddr $fdtfile;"                       \
 876         "bootm $loadaddr - $fdtaddr"
 877
 878 #define CONFIG_NFSBOOTCOMMAND                   \
 879         "setenv bootargs root=/dev/nfs rw "     \
 880         "nfsroot=$serverip:$rootpath "          \
 881         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 882         "console=$consoledev,$baudrate $othbootargs;"   \
 883         "tftp $loadaddr $bootfile;"             \
 884         "tftp $fdtaddr $fdtfile;"               \
 885         "bootm $loadaddr - $fdtaddr"
 886
 887 #define CONFIG_RAMBOOTCOMMAND                           \
 888         "setenv bootargs root=/dev/ram rw "             \
 889         "console=$consoledev,$baudrate $othbootargs;"   \
 890         "tftp $ramdiskaddr $ramdiskfile;"               \
 891         "tftp $loadaddr $bootfile;"                     \
 892         "tftp $fdtaddr $fdtfile;"                       \
 893         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 894
 895 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 896
 897 #include <asm/fsl_secure_boot.h>
 898
 899 #endif  /* __CONFIG_H */