2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 * B4860 QDS board configuration file
13 #ifdef CONFIG_RAMBOOT_PBL
14 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
15 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
20 #define CONFIG_SPL_FLUSH_IMAGE
21 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
22 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
23 #define CONFIG_SPL_PAD_TO 0x40000
24 #define CONFIG_SPL_MAX_SIZE 0x28000
25 #define RESET_VECTOR_OFFSET 0x27FFC
26 #define BOOT_PAGE_OFFSET 0x27000
27 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
28 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
29 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
30 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
31 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
32 #define CONFIG_SPL_NAND_BOOT
33 #ifdef CONFIG_SPL_BUILD
34 #define CONFIG_SPL_SKIP_RELOCATE
35 #define CONFIG_SPL_COMMON_INIT_DDR
36 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
41 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
42 /* Set 1M boot space */
43 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
44 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
45 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
46 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
49 /* High Level Configuration Options */
50 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
51 #define CONFIG_MP /* support multiple processors */
53 #ifndef CONFIG_RESET_VECTOR_ADDRESS
54 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
57 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
58 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
59 #define CONFIG_PCIE1 /* PCIE controller 1 */
60 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
61 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
63 #ifndef CONFIG_ARCH_B4420
64 #define CONFIG_SYS_SRIO
65 #define CONFIG_SRIO1 /* SRIO port 1 */
66 #define CONFIG_SRIO2 /* SRIO port 2 */
67 #define CONFIG_SRIO_PCIE_BOOT_MASTER
70 /* I2C bus multiplexer */
71 #define I2C_MUX_PCA_ADDR 0x77
73 /* VSC Crossbar switches */
74 #define CONFIG_VSC_CROSSBAR
75 #define I2C_CH_DEFAULT 0x8
76 #define I2C_CH_VSC3316 0xc
77 #define I2C_CH_VSC3308 0xd
79 #define VSC3316_TX_ADDRESS 0x70
80 #define VSC3316_RX_ADDRESS 0x71
81 #define VSC3308_TX_ADDRESS 0x02
82 #define VSC3308_RX_ADDRESS 0x03
84 /* IDT clock synthesizers */
85 #define CONFIG_IDT8T49N222A
86 #define I2C_CH_IDT 0x9
88 #define IDT_SERDES1_ADDRESS 0x6E
89 #define IDT_SERDES2_ADDRESS 0x6C
91 /* Voltage monitor on channel 2*/
92 #define I2C_MUX_CH_VOL_MONITOR 0xa
93 #define I2C_VOL_MONITOR_ADDR 0x40
94 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
95 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
96 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
99 #define I2C_MUX_CH_DPM 0xa
100 #define I2C_DPM_ADDR 0x28
102 #define CONFIG_ENV_OVERWRITE
104 #ifndef CONFIG_MTD_NOR_FLASH
106 #define CONFIG_FLASH_CFI_DRIVER
107 #define CONFIG_SYS_FLASH_CFI
108 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
111 #if defined(CONFIG_SPIFLASH)
112 #define CONFIG_SYS_EXTRA_ENV_RELOC
113 #define CONFIG_ENV_SPI_BUS 0
114 #define CONFIG_ENV_SPI_CS 0
115 #define CONFIG_ENV_SPI_MAX_HZ 10000000
116 #define CONFIG_ENV_SPI_MODE 0
117 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
118 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
119 #define CONFIG_ENV_SECT_SIZE 0x10000
120 #elif defined(CONFIG_SDCARD)
121 #define CONFIG_SYS_EXTRA_ENV_RELOC
122 #define CONFIG_SYS_MMC_ENV_DEV 0
123 #define CONFIG_ENV_SIZE 0x2000
124 #define CONFIG_ENV_OFFSET (512 * 1097)
125 #elif defined(CONFIG_NAND)
126 #define CONFIG_SYS_EXTRA_ENV_RELOC
127 #define CONFIG_ENV_SIZE 0x2000
128 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
129 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
130 #define CONFIG_ENV_ADDR 0xffe20000
131 #define CONFIG_ENV_SIZE 0x2000
132 #elif defined(CONFIG_ENV_IS_NOWHERE)
133 #define CONFIG_ENV_SIZE 0x2000
135 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
136 #define CONFIG_ENV_SIZE 0x2000
137 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
141 unsigned long get_board_sys_clk(void);
142 unsigned long get_board_ddr_clk(void);
144 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
145 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
148 * These can be toggled for performance analysis, otherwise use default.
150 #define CONFIG_SYS_CACHE_STASHING
151 #define CONFIG_BTB /* toggle branch predition */
152 #define CONFIG_DDR_ECC
153 #ifdef CONFIG_DDR_ECC
154 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
155 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
158 #define CONFIG_ENABLE_36BIT_PHYS
160 #ifdef CONFIG_PHYS_64BIT
161 #define CONFIG_ADDR_MAP
162 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
166 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
168 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
169 #define CONFIG_SYS_MEMTEST_END 0x00400000
172 * Config the L3 Cache as L3 SRAM
174 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
175 #define CONFIG_SYS_L3_SIZE 256 << 10
176 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
178 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
180 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
181 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
182 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
183 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
185 #ifdef CONFIG_PHYS_64BIT
186 #define CONFIG_SYS_DCSRBAR 0xf0000000
187 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
191 #define CONFIG_ID_EEPROM
192 #define CONFIG_SYS_I2C_EEPROM_NXID
193 #define CONFIG_SYS_EEPROM_BUS_NUM 0
194 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
195 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
196 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
197 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
202 #define CONFIG_VERY_BIG_RAM
203 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
204 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
206 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
207 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
209 #define CONFIG_DDR_SPD
210 #define CONFIG_SYS_DDR_RAW_TIMING
211 #ifndef CONFIG_SPL_BUILD
212 #define CONFIG_FSL_DDR_INTERACTIVE
215 #define CONFIG_SYS_SPD_BUS_NUM 0
216 #define SPD_EEPROM_ADDRESS1 0x51
217 #define SPD_EEPROM_ADDRESS2 0x53
219 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
220 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
225 #define CONFIG_SYS_FLASH_BASE 0xe0000000
226 #ifdef CONFIG_PHYS_64BIT
227 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
229 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
232 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
233 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
235 CSPR_PORT_SIZE_16 | \
238 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
239 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
240 CSPR_PORT_SIZE_16 | \
243 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
244 /* NOR Flash Timing Params */
245 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
246 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
247 FTIM0_NOR_TEADC(0x04) | \
248 FTIM0_NOR_TEAHC(0x20))
249 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
250 FTIM1_NOR_TRAD_NOR(0x1A) |\
251 FTIM1_NOR_TSEQRAD_NOR(0x13))
252 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
253 FTIM2_NOR_TCH(0x0E) | \
254 FTIM2_NOR_TWPH(0x0E) | \
256 #define CONFIG_SYS_NOR_FTIM3 0x0
258 #define CONFIG_SYS_FLASH_QUIET_TEST
259 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
261 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
262 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
263 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
264 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
266 #define CONFIG_SYS_FLASH_EMPTY_INFO
267 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
268 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
270 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
271 #define CONFIG_FSL_QIXIS_V2
272 #define QIXIS_BASE 0xffdf0000
273 #ifdef CONFIG_PHYS_64BIT
274 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
276 #define QIXIS_BASE_PHYS QIXIS_BASE
278 #define QIXIS_LBMAP_SWITCH 0x01
279 #define QIXIS_LBMAP_MASK 0x0f
280 #define QIXIS_LBMAP_SHIFT 0
281 #define QIXIS_LBMAP_DFLTBANK 0x00
282 #define QIXIS_LBMAP_ALTBANK 0x02
283 #define QIXIS_RST_CTL_RESET 0x31
284 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
285 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
286 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
288 #define CONFIG_SYS_CSPR3_EXT (0xf)
289 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
293 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024)
294 #define CONFIG_SYS_CSOR3 0x0
295 /* QIXIS Timing parameters for IFC CS3 */
296 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
297 FTIM0_GPCM_TEADC(0x0e) | \
298 FTIM0_GPCM_TEAHC(0x0e))
299 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
300 FTIM1_GPCM_TRAD(0x1f))
301 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
302 FTIM2_GPCM_TCH(0x8) | \
303 FTIM2_GPCM_TWP(0x1f))
304 #define CONFIG_SYS_CS3_FTIM3 0x0
306 /* NAND Flash on IFC */
307 #define CONFIG_NAND_FSL_IFC
308 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
309 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
310 #define CONFIG_SYS_NAND_BASE 0xff800000
311 #ifdef CONFIG_PHYS_64BIT
312 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
314 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
317 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
318 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
319 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
320 | CSPR_MSEL_NAND /* MSEL = NAND */ \
322 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
324 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
325 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
326 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
327 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
328 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
329 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
330 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
332 #define CONFIG_SYS_NAND_ONFI_DETECTION
334 /* ONFI NAND Flash mode0 Timing Params */
335 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
336 FTIM0_NAND_TWP(0x18) | \
337 FTIM0_NAND_TWCHT(0x07) | \
338 FTIM0_NAND_TWH(0x0a))
339 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
340 FTIM1_NAND_TWBE(0x39) | \
341 FTIM1_NAND_TRR(0x0e) | \
342 FTIM1_NAND_TRP(0x18))
343 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
344 FTIM2_NAND_TREH(0x0a) | \
345 FTIM2_NAND_TWHRE(0x1e))
346 #define CONFIG_SYS_NAND_FTIM3 0x0
348 #define CONFIG_SYS_NAND_DDR_LAW 11
350 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
351 #define CONFIG_SYS_MAX_NAND_DEVICE 1
353 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
355 #if defined(CONFIG_NAND)
356 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
357 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
358 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
359 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
360 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
361 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
362 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
363 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
364 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
365 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
366 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
367 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
368 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
369 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
370 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
371 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
373 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
374 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
375 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
376 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
377 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
378 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
379 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
380 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
381 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
382 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
383 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
384 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
385 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
386 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
387 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
388 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
390 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
391 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
392 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
393 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
394 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
395 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
396 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
397 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
399 #ifdef CONFIG_SPL_BUILD
400 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
402 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
405 #if defined(CONFIG_RAMBOOT_PBL)
406 #define CONFIG_SYS_RAMBOOT
409 #define CONFIG_BOARD_EARLY_INIT_R
410 #define CONFIG_MISC_INIT_R
412 #define CONFIG_HWCONFIG
414 /* define to use L1 as initial stack */
415 #define CONFIG_L1_INIT_RAM
416 #define CONFIG_SYS_INIT_RAM_LOCK
417 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
418 #ifdef CONFIG_PHYS_64BIT
419 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
420 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
421 /* The assembler doesn't like typecast */
422 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
423 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
424 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
426 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
427 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
428 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
430 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
432 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
433 GENERATED_GBL_DATA_SIZE)
434 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
436 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
437 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
439 /* Serial Port - controlled on board with jumper J8
443 #define CONFIG_SYS_NS16550_SERIAL
444 #define CONFIG_SYS_NS16550_REG_SIZE 1
445 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
447 #define CONFIG_SYS_BAUDRATE_TABLE \
448 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
450 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
451 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
452 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
453 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
456 #define CONFIG_SYS_I2C
457 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
458 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
459 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
460 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
461 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
462 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
463 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
469 #define CONFIG_RTC_DS3231 1
470 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
475 #ifdef CONFIG_SYS_SRIO
477 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
478 #ifdef CONFIG_PHYS_64BIT
479 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
481 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
483 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
487 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
488 #ifdef CONFIG_PHYS_64BIT
489 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
491 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
493 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
498 * for slave u-boot IMAGE instored in master memory space,
499 * PHYS must be aligned based on the SIZE
501 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
502 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
503 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
504 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
506 * for slave UCODE and ENV instored in master memory space,
507 * PHYS must be aligned based on the SIZE
509 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
510 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
511 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
513 /* slave core release by master*/
514 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
515 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
518 * SRIO_PCIE_BOOT - SLAVE
520 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
521 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
522 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
523 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
527 * eSPI - Enhanced SPI
529 #define CONFIG_SF_DEFAULT_SPEED 10000000
530 #define CONFIG_SF_DEFAULT_MODE 0
535 #ifdef CONFIG_PHYS_64BIT
536 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull
538 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000
543 * Memory space is mapped 1-1, but I/O space must start from 0.
546 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
547 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
548 #ifdef CONFIG_PHYS_64BIT
549 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
550 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
552 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
553 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
555 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
556 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
557 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
558 #ifdef CONFIG_PHYS_64BIT
559 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
561 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
563 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
566 #ifndef CONFIG_NOBQFMAN
567 #define CONFIG_SYS_BMAN_NUM_PORTALS 25
568 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
569 #ifdef CONFIG_PHYS_64BIT
570 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
572 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
574 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
575 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
576 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
577 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
578 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
579 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
580 CONFIG_SYS_BMAN_CENA_SIZE)
581 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
582 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
583 #define CONFIG_SYS_QMAN_NUM_PORTALS 25
584 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
585 #ifdef CONFIG_PHYS_64BIT
586 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
588 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
590 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
591 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
592 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
593 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
594 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
595 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
596 CONFIG_SYS_QMAN_CENA_SIZE)
597 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
598 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
600 #define CONFIG_SYS_DPAA_FMAN
602 #define CONFIG_SYS_DPAA_RMAN
604 /* Default address of microcode for the Linux Fman driver */
605 #if defined(CONFIG_SPIFLASH)
607 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
608 * env, so we got 0x110000.
610 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
611 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
612 #elif defined(CONFIG_SDCARD)
614 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
615 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
616 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
618 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
619 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
620 #elif defined(CONFIG_NAND)
621 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
622 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
623 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
625 * Slave has no ucode locally, it can fetch this from remote. When implementing
626 * in two corenet boards, slave's ucode could be stored in master's memory
627 * space, the address can be mapped from slave TLB->slave LAW->
628 * slave SRIO or PCIE outbound window->master inbound window->
629 * master LAW->the ucode address in master's memory space.
631 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
632 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
634 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
635 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
637 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
638 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
639 #endif /* CONFIG_NOBQFMAN */
641 #ifdef CONFIG_SYS_DPAA_FMAN
642 #define CONFIG_FMAN_ENET
643 #define CONFIG_PHYLIB_10G
644 #define CONFIG_PHY_VITESSE
645 #define CONFIG_PHY_TERANETICS
646 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
647 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
648 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
649 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
653 #define CONFIG_PCI_INDIRECT_BRIDGE
655 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
656 #endif /* CONFIG_PCI */
658 #ifdef CONFIG_FMAN_ENET
659 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
660 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
662 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
663 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
664 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/
666 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
667 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
668 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
669 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
671 #define CONFIG_MII /* MII PHY management */
672 #define CONFIG_ETHPRIME "FM1@DTSEC1"
675 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
680 #define CONFIG_LOADS_ECHO /* echo on for serial download */
681 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
686 #define CONFIG_HAS_FSL_DR_USB
688 #ifdef CONFIG_HAS_FSL_DR_USB
689 #ifdef CONFIG_USB_EHCI_HCD
690 #define CONFIG_USB_EHCI_FSL
691 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
696 * Miscellaneous configurable options
698 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
701 * For booting Linux, the board info and command line data
702 * have to be in the first 64 MB of memory, since this is
703 * the maximum mapped by the Linux kernel during initialization.
705 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
706 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
708 #ifdef CONFIG_CMD_KGDB
709 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
713 * Environment Configuration
715 #define CONFIG_ROOTPATH "/opt/nfsroot"
716 #define CONFIG_BOOTFILE "uImage"
717 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
719 /* default location for tftp and bootm */
720 #define CONFIG_LOADADDR 1000000
722 #define __USB_PHY_TYPE ulpi
724 #ifdef CONFIG_ARCH_B4860
725 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \
726 "bank_intlv=cs0_cs1;" \
729 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
732 #define CONFIG_EXTRA_ENV_SETTINGS \
734 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
736 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
737 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
738 "tftpflash=tftpboot $loadaddr $uboot && " \
739 "protect off $ubootaddr +$filesize && " \
740 "erase $ubootaddr +$filesize && " \
741 "cp.b $loadaddr $ubootaddr $filesize && " \
742 "protect on $ubootaddr +$filesize && " \
743 "cmp.b $loadaddr $ubootaddr $filesize\0" \
744 "consoledev=ttyS0\0" \
745 "ramdiskaddr=2000000\0" \
746 "ramdiskfile=b4860qds/ramdisk.uboot\0" \
747 "fdtaddr=1e00000\0" \
748 "fdtfile=b4860qds/b4860qds.dtb\0" \
751 /* For emulation this causes u-boot to jump to the start of the proof point
752 app code automatically */
753 #define CONFIG_PROOF_POINTS \
754 "setenv bootargs root=/dev/$bdev rw " \
755 "console=$consoledev,$baudrate $othbootargs;" \
756 "cpu 1 release 0x29000000 - - -;" \
757 "cpu 2 release 0x29000000 - - -;" \
758 "cpu 3 release 0x29000000 - - -;" \
759 "cpu 4 release 0x29000000 - - -;" \
760 "cpu 5 release 0x29000000 - - -;" \
761 "cpu 6 release 0x29000000 - - -;" \
762 "cpu 7 release 0x29000000 - - -;" \
765 #define CONFIG_HVBOOT \
766 "setenv bootargs config-addr=0x60000000; " \
767 "bootm 0x01000000 - 0x00f00000"
770 "setenv bootargs root=/dev/$bdev rw " \
771 "console=$consoledev,$baudrate $othbootargs;" \
772 "cpu 1 release 0x01000000 - - -;" \
773 "cpu 2 release 0x01000000 - - -;" \
774 "cpu 3 release 0x01000000 - - -;" \
775 "cpu 4 release 0x01000000 - - -;" \
776 "cpu 5 release 0x01000000 - - -;" \
777 "cpu 6 release 0x01000000 - - -;" \
778 "cpu 7 release 0x01000000 - - -;" \
781 #define CONFIG_LINUX \
782 "setenv bootargs root=/dev/ram rw " \
783 "console=$consoledev,$baudrate $othbootargs;" \
784 "setenv ramdiskaddr 0x02000000;" \
785 "setenv fdtaddr 0x01e00000;" \
786 "setenv loadaddr 0x1000000;" \
787 "bootm $loadaddr $ramdiskaddr $fdtaddr"
789 #define CONFIG_HDBOOT \
790 "setenv bootargs root=/dev/$bdev rw " \
791 "console=$consoledev,$baudrate $othbootargs;" \
792 "tftp $loadaddr $bootfile;" \
793 "tftp $fdtaddr $fdtfile;" \
794 "bootm $loadaddr - $fdtaddr"
796 #define CONFIG_NFSBOOTCOMMAND \
797 "setenv bootargs root=/dev/nfs rw " \
798 "nfsroot=$serverip:$rootpath " \
799 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
800 "console=$consoledev,$baudrate $othbootargs;" \
801 "tftp $loadaddr $bootfile;" \
802 "tftp $fdtaddr $fdtfile;" \
803 "bootm $loadaddr - $fdtaddr"
805 #define CONFIG_RAMBOOTCOMMAND \
806 "setenv bootargs root=/dev/ram rw " \
807 "console=$consoledev,$baudrate $othbootargs;" \
808 "tftp $ramdiskaddr $ramdiskfile;" \
809 "tftp $loadaddr $bootfile;" \
810 "tftp $fdtaddr $fdtfile;" \
811 "bootm $loadaddr $ramdiskaddr $fdtaddr"
813 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
815 #include <asm/fsl_secure_boot.h>
817 #endif /* __CONFIG_H */