git.sur5r.net Git - u-boot/blob - include/configs/B4860QDS.h

   1 /*
   2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_DISPLAY_BOARDINFO
  11
  12 /*
  13  * B4860 QDS board configuration file
  14  */
  15 #define CONFIG_B4860QDS
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #define CONFIG_SYS_FSL_PBL_PBI  $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
  19 #define CONFIG_SYS_FSL_PBL_RCW  $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
  20 #ifndef CONFIG_NAND
  21 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  22 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  23 #else
  24 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  25 #define CONFIG_SPL_ENV_SUPPORT
  26 #define CONFIG_SPL_SERIAL_SUPPORT
  27 #define CONFIG_SPL_FLUSH_IMAGE
  28 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  29 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  30 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  31 #define CONFIG_SPL_I2C_SUPPORT
  32 #define CONFIG_FSL_LAW                 /* Use common FSL init code */
  33 #define CONFIG_SYS_TEXT_BASE            0x00201000
  34 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  35 #define CONFIG_SPL_PAD_TO               0x40000
  36 #define CONFIG_SPL_MAX_SIZE             0x28000
  37 #define RESET_VECTOR_OFFSET             0x27FFC
  38 #define BOOT_PAGE_OFFSET                0x27000
  39 #define CONFIG_SPL_NAND_SUPPORT
  40 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  41 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  42 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  43 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  44 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  45 #define CONFIG_SPL_NAND_BOOT
  46 #ifdef CONFIG_SPL_BUILD
  47 #define CONFIG_SPL_SKIP_RELOCATE
  48 #define CONFIG_SPL_COMMON_INIT_DDR
  49 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  50 #define CONFIG_SYS_NO_FLASH
  51 #endif
  52 #endif
  53 #endif
  54
  55 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  56 /* Set 1M boot space */
  57 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  58 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  59                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  60 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  61 #define CONFIG_SYS_NO_FLASH
  62 #endif
  63
  64 /* High Level Configuration Options */
  65 #define CONFIG_BOOKE
  66 #define CONFIG_E500                     /* BOOKE e500 family */
  67 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  68 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  69 #define CONFIG_MP                       /* support multiple processors */
  70
  71 #ifndef CONFIG_SYS_TEXT_BASE
  72 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  73 #endif
  74
  75 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  76 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  77 #endif
  78
  79 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  80 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  81 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
  82 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
  83 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  84 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  85 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  86 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  87
  88 #ifndef CONFIG_PPC_B4420
  89 #define CONFIG_SYS_SRIO
  90 #define CONFIG_SRIO1                    /* SRIO port 1 */
  91 #define CONFIG_SRIO2                    /* SRIO port 2 */
  92 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  93 #endif
  94
  95 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  96
  97 /* I2C bus multiplexer */
  98 #define I2C_MUX_PCA_ADDR                0x77
  99
 100 /* VSC Crossbar switches */
 101 #define CONFIG_VSC_CROSSBAR
 102 #define I2C_CH_DEFAULT                  0x8
 103 #define I2C_CH_VSC3316                  0xc
 104 #define I2C_CH_VSC3308                  0xd
 105
 106 #define VSC3316_TX_ADDRESS              0x70
 107 #define VSC3316_RX_ADDRESS              0x71
 108 #define VSC3308_TX_ADDRESS              0x02
 109 #define VSC3308_RX_ADDRESS              0x03
 110
 111 /* IDT clock synthesizers */
 112 #define CONFIG_IDT8T49N222A
 113 #define I2C_CH_IDT                     0x9
 114
 115 #define IDT_SERDES1_ADDRESS            0x6E
 116 #define IDT_SERDES2_ADDRESS            0x6C
 117
 118 /* Voltage monitor on channel 2*/
 119 #define I2C_MUX_CH_VOL_MONITOR          0xa
 120 #define I2C_VOL_MONITOR_ADDR            0x40
 121 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 122 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 123 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 124
 125 #define CONFIG_ZM7300
 126 #define I2C_MUX_CH_DPM                  0xa
 127 #define I2C_DPM_ADDR                    0x28
 128
 129 #define CONFIG_ENV_OVERWRITE
 130
 131 #ifdef CONFIG_SYS_NO_FLASH
 132 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
 133 #define CONFIG_ENV_IS_NOWHERE
 134 #endif
 135 #else
 136 #define CONFIG_FLASH_CFI_DRIVER
 137 #define CONFIG_SYS_FLASH_CFI
 138 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 139 #endif
 140
 141 #if defined(CONFIG_SPIFLASH)
 142 #define CONFIG_SYS_EXTRA_ENV_RELOC
 143 #define CONFIG_ENV_IS_IN_SPI_FLASH
 144 #define CONFIG_ENV_SPI_BUS              0
 145 #define CONFIG_ENV_SPI_CS               0
 146 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 147 #define CONFIG_ENV_SPI_MODE             0
 148 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 149 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 150 #define CONFIG_ENV_SECT_SIZE            0x10000
 151 #elif defined(CONFIG_SDCARD)
 152 #define CONFIG_SYS_EXTRA_ENV_RELOC
 153 #define CONFIG_ENV_IS_IN_MMC
 154 #define CONFIG_SYS_MMC_ENV_DEV          0
 155 #define CONFIG_ENV_SIZE                 0x2000
 156 #define CONFIG_ENV_OFFSET               (512 * 1097)
 157 #elif defined(CONFIG_NAND)
 158 #define CONFIG_SYS_EXTRA_ENV_RELOC
 159 #define CONFIG_ENV_IS_IN_NAND
 160 #define CONFIG_ENV_SIZE                 0x2000
 161 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 162 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 163 #define CONFIG_ENV_IS_IN_REMOTE
 164 #define CONFIG_ENV_ADDR         0xffe20000
 165 #define CONFIG_ENV_SIZE         0x2000
 166 #elif defined(CONFIG_ENV_IS_NOWHERE)
 167 #define CONFIG_ENV_SIZE         0x2000
 168 #else
 169 #define CONFIG_ENV_IS_IN_FLASH
 170 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 171 #define CONFIG_ENV_SIZE         0x2000
 172 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 173 #endif
 174
 175 #ifndef __ASSEMBLY__
 176 unsigned long get_board_sys_clk(void);
 177 unsigned long get_board_ddr_clk(void);
 178 #endif
 179 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
 180 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 181
 182 /*
 183  * These can be toggled for performance analysis, otherwise use default.
 184  */
 185 #define CONFIG_SYS_CACHE_STASHING
 186 #define CONFIG_BTB                      /* toggle branch predition */
 187 #define CONFIG_DDR_ECC
 188 #ifdef CONFIG_DDR_ECC
 189 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 190 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 191 #endif
 192
 193 #define CONFIG_ENABLE_36BIT_PHYS
 194
 195 #ifdef CONFIG_PHYS_64BIT
 196 #define CONFIG_ADDR_MAP
 197 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 198 #endif
 199
 200 #if 0
 201 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 202 #endif
 203 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 204 #define CONFIG_SYS_MEMTEST_END          0x00400000
 205 #define CONFIG_SYS_ALT_MEMTEST
 206 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 207
 208 /*
 209  *  Config the L3 Cache as L3 SRAM
 210  */
 211 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 212 #define CONFIG_SYS_L3_SIZE              256 << 10
 213 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 214 #ifdef CONFIG_NAND
 215 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 216 #endif
 217 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 218 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 219 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 220 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 221
 222 #ifdef CONFIG_PHYS_64BIT
 223 #define CONFIG_SYS_DCSRBAR              0xf0000000
 224 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 225 #endif
 226
 227 /* EEPROM */
 228 #define CONFIG_ID_EEPROM
 229 #define CONFIG_SYS_I2C_EEPROM_NXID
 230 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 231 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 232 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 233 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 234 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 235
 236 /*
 237  * DDR Setup
 238  */
 239 #define CONFIG_VERY_BIG_RAM
 240 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 241 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 242
 243 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
 244 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 245 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 246
 247 #define CONFIG_DDR_SPD
 248 #define CONFIG_SYS_DDR_RAW_TIMING
 249 #define CONFIG_SYS_FSL_DDR3
 250 #ifndef CONFIG_SPL_BUILD
 251 #define CONFIG_FSL_DDR_INTERACTIVE
 252 #endif
 253
 254 #define CONFIG_SYS_SPD_BUS_NUM  0
 255 #define SPD_EEPROM_ADDRESS1     0x51
 256 #define SPD_EEPROM_ADDRESS2     0x53
 257
 258 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 259 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 260
 261 /*
 262  * IFC Definitions
 263  */
 264 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 265 #ifdef CONFIG_PHYS_64BIT
 266 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 267 #else
 268 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 269 #endif
 270
 271 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 272 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 273                                 + 0x8000000) | \
 274                                 CSPR_PORT_SIZE_16 | \
 275                                 CSPR_MSEL_NOR | \
 276                                 CSPR_V)
 277 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 278 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 279                                 CSPR_PORT_SIZE_16 | \
 280                                 CSPR_MSEL_NOR | \
 281                                 CSPR_V)
 282 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128 * 1024 * 1024)
 283 /* NOR Flash Timing Params */
 284 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(4)
 285 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x01) | \
 286                                 FTIM0_NOR_TEADC(0x04) | \
 287                                 FTIM0_NOR_TEAHC(0x20))
 288 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 289                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 290                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 291 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x01) | \
 292                                 FTIM2_NOR_TCH(0x0E) | \
 293                                 FTIM2_NOR_TWPH(0x0E) | \
 294                                 FTIM2_NOR_TWP(0x1c))
 295 #define CONFIG_SYS_NOR_FTIM3    0x0
 296
 297 #define CONFIG_SYS_FLASH_QUIET_TEST
 298 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 299
 300 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 301 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 302 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 303 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 304
 305 #define CONFIG_SYS_FLASH_EMPTY_INFO
 306 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 307                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 308
 309 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 310 #define CONFIG_FSL_QIXIS_V2
 311 #define QIXIS_BASE              0xffdf0000
 312 #ifdef CONFIG_PHYS_64BIT
 313 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 314 #else
 315 #define QIXIS_BASE_PHYS         QIXIS_BASE
 316 #endif
 317 #define QIXIS_LBMAP_SWITCH              0x01
 318 #define QIXIS_LBMAP_MASK                0x0f
 319 #define QIXIS_LBMAP_SHIFT               0
 320 #define QIXIS_LBMAP_DFLTBANK            0x00
 321 #define QIXIS_LBMAP_ALTBANK             0x02
 322 #define QIXIS_RST_CTL_RESET             0x31
 323 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 324 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 325 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 326
 327 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 328 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 329                                 | CSPR_PORT_SIZE_8 \
 330                                 | CSPR_MSEL_GPCM \
 331                                 | CSPR_V)
 332 #define CONFIG_SYS_AMASK3       IFC_AMASK(4 * 1024)
 333 #define CONFIG_SYS_CSOR3        0x0
 334 /* QIXIS Timing parameters for IFC CS3 */
 335 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 336                                         FTIM0_GPCM_TEADC(0x0e) | \
 337                                         FTIM0_GPCM_TEAHC(0x0e))
 338 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 339                                         FTIM1_GPCM_TRAD(0x1f))
 340 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 341                                         FTIM2_GPCM_TCH(0x8) | \
 342                                         FTIM2_GPCM_TWP(0x1f))
 343 #define CONFIG_SYS_CS3_FTIM3            0x0
 344
 345 /* NAND Flash on IFC */
 346 #define CONFIG_NAND_FSL_IFC
 347 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 348 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 349 #define CONFIG_SYS_NAND_BASE            0xff800000
 350 #ifdef CONFIG_PHYS_64BIT
 351 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 352 #else
 353 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 354 #endif
 355
 356 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 357 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 358                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 359                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 360                                 | CSPR_V)
 361 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 362
 363 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 364                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 365                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 366                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 367                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 368                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 369                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 370
 371 #define CONFIG_SYS_NAND_ONFI_DETECTION
 372
 373 /* ONFI NAND Flash mode0 Timing Params */
 374 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 375                                         FTIM0_NAND_TWP(0x18)   | \
 376                                         FTIM0_NAND_TWCHT(0x07) | \
 377                                         FTIM0_NAND_TWH(0x0a))
 378 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 379                                         FTIM1_NAND_TWBE(0x39)  | \
 380                                         FTIM1_NAND_TRR(0x0e)   | \
 381                                         FTIM1_NAND_TRP(0x18))
 382 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 383                                         FTIM2_NAND_TREH(0x0a) | \
 384                                         FTIM2_NAND_TWHRE(0x1e))
 385 #define CONFIG_SYS_NAND_FTIM3           0x0
 386
 387 #define CONFIG_SYS_NAND_DDR_LAW         11
 388
 389 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 390 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 391 #define CONFIG_CMD_NAND
 392
 393 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 394
 395 #if defined(CONFIG_NAND)
 396 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 397 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 398 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 399 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 400 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 401 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 402 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 403 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 404 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 405 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 406 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 407 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 408 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 409 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 410 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 411 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 412 #else
 413 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 414 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 415 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 416 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 417 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 418 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 419 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 420 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 421 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 422 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 423 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 424 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 425 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 426 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 427 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 428 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 429 #endif
 430 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 431 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 432 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 433 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 434 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 435 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 436 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 437 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 438
 439 #ifdef CONFIG_SPL_BUILD
 440 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 441 #else
 442 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 443 #endif
 444
 445 #if defined(CONFIG_RAMBOOT_PBL)
 446 #define CONFIG_SYS_RAMBOOT
 447 #endif
 448
 449 #define CONFIG_BOARD_EARLY_INIT_R
 450 #define CONFIG_MISC_INIT_R
 451
 452 #define CONFIG_HWCONFIG
 453
 454 /* define to use L1 as initial stack */
 455 #define CONFIG_L1_INIT_RAM
 456 #define CONFIG_SYS_INIT_RAM_LOCK
 457 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 458 #ifdef CONFIG_PHYS_64BIT
 459 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 460 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 461 /* The assembler doesn't like typecast */
 462 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 463         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 464           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 465 #else
 466 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 467 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 468 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 469 #endif
 470 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 471
 472 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 473                                         GENERATED_GBL_DATA_SIZE)
 474 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 475
 476 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 477 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 478
 479 /* Serial Port - controlled on board with jumper J8
 480  * open - index 2
 481  * shorted - index 1
 482  */
 483 #define CONFIG_CONS_INDEX       1
 484 #define CONFIG_SYS_NS16550_SERIAL
 485 #define CONFIG_SYS_NS16550_REG_SIZE     1
 486 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 487
 488 #define CONFIG_SYS_BAUDRATE_TABLE       \
 489         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 490
 491 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 492 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 493 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 494 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 495 #ifndef CONFIG_SPL_BUILD
 496 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 497 #endif
 498
 499 /* I2C */
 500 #define CONFIG_SYS_I2C
 501 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 502 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
 503 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 504 #define CONFIG_SYS_FSL_I2C2_SPEED       400000  /* I2C speed in Hz */
 505 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 506 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 507 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x119000
 508
 509 /*
 510  * RTC configuration
 511  */
 512 #define RTC
 513 #define CONFIG_RTC_DS3231               1
 514 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 515
 516 /*
 517  * RapidIO
 518  */
 519 #ifdef CONFIG_SYS_SRIO
 520 #ifdef CONFIG_SRIO1
 521 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 522 #ifdef CONFIG_PHYS_64BIT
 523 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 524 #else
 525 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 526 #endif
 527 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 528 #endif
 529
 530 #ifdef CONFIG_SRIO2
 531 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 532 #ifdef CONFIG_PHYS_64BIT
 533 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 534 #else
 535 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 536 #endif
 537 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 538 #endif
 539 #endif
 540
 541 /*
 542  * for slave u-boot IMAGE instored in master memory space,
 543  * PHYS must be aligned based on the SIZE
 544  */
 545 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 546 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 547 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 548 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 549 /*
 550  * for slave UCODE and ENV instored in master memory space,
 551  * PHYS must be aligned based on the SIZE
 552  */
 553 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 554 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 555 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 556
 557 /* slave core release by master*/
 558 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 559 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 560
 561 /*
 562  * SRIO_PCIE_BOOT - SLAVE
 563  */
 564 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 565 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 566 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 567                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 568 #endif
 569
 570 /*
 571  * eSPI - Enhanced SPI
 572  */
 573 #define CONFIG_SF_DEFAULT_SPEED         10000000
 574 #define CONFIG_SF_DEFAULT_MODE          0
 575
 576 /*
 577  * MAPLE
 578  */
 579 #ifdef CONFIG_PHYS_64BIT
 580 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xFA0000000ull
 581 #else
 582 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xA0000000
 583 #endif
 584
 585 /*
 586  * General PCI
 587  * Memory space is mapped 1-1, but I/O space must start from 0.
 588  */
 589
 590 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 591 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 592 #ifdef CONFIG_PHYS_64BIT
 593 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 594 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 595 #else
 596 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 597 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 598 #endif
 599 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 600 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 601 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 602 #ifdef CONFIG_PHYS_64BIT
 603 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 604 #else
 605 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 606 #endif
 607 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 608
 609 /* Qman/Bman */
 610 #ifndef CONFIG_NOBQFMAN
 611 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 612 #define CONFIG_SYS_BMAN_NUM_PORTALS     25
 613 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 614 #ifdef CONFIG_PHYS_64BIT
 615 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 616 #else
 617 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 618 #endif
 619 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 620 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 621 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 622 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 623 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 624 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 625                                         CONFIG_SYS_BMAN_CENA_SIZE)
 626 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 627 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 628 #define CONFIG_SYS_QMAN_NUM_PORTALS     25
 629 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 630 #ifdef CONFIG_PHYS_64BIT
 631 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 632 #else
 633 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 634 #endif
 635 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 636 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 637 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 638 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 639 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 640 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 641                                         CONFIG_SYS_QMAN_CENA_SIZE)
 642 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 643 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 644
 645 #define CONFIG_SYS_DPAA_FMAN
 646
 647 #define CONFIG_SYS_DPAA_RMAN
 648
 649 /* Default address of microcode for the Linux Fman driver */
 650 #if defined(CONFIG_SPIFLASH)
 651 /*
 652  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 653  * env, so we got 0x110000.
 654  */
 655 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 656 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 657 #elif defined(CONFIG_SDCARD)
 658 /*
 659  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 660  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
 661  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
 662  */
 663 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 664 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
 665 #elif defined(CONFIG_NAND)
 666 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 667 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
 668 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 669 /*
 670  * Slave has no ucode locally, it can fetch this from remote. When implementing
 671  * in two corenet boards, slave's ucode could be stored in master's memory
 672  * space, the address can be mapped from slave TLB->slave LAW->
 673  * slave SRIO or PCIE outbound window->master inbound window->
 674  * master LAW->the ucode address in master's memory space.
 675  */
 676 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 677 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 678 #else
 679 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 680 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 681 #endif
 682 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 683 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 684 #endif /* CONFIG_NOBQFMAN */
 685
 686 #ifdef CONFIG_SYS_DPAA_FMAN
 687 #define CONFIG_FMAN_ENET
 688 #define CONFIG_PHYLIB_10G
 689 #define CONFIG_PHY_VITESSE
 690 #define CONFIG_PHY_TERANETICS
 691 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 692 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
 693 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 694 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
 695 #endif
 696
 697 #ifdef CONFIG_PCI
 698 #define CONFIG_PCI_INDIRECT_BRIDGE
 699 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 700
 701 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 702 #define CONFIG_DOS_PARTITION
 703 #endif  /* CONFIG_PCI */
 704
 705 #ifdef CONFIG_FMAN_ENET
 706 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
 707 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
 708
 709 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
 710 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7       /*SLOT 1*/
 711 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6       /*SLOT 2*/
 712
 713 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 714 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 715 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 716 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 717
 718 #define CONFIG_MII              /* MII PHY management */
 719 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 720 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 721 #endif
 722
 723 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
 724
 725 /*
 726  * Environment
 727  */
 728 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 729 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 730
 731 /*
 732  * Command line configuration.
 733  */
 734 #define CONFIG_CMD_DATE
 735 #define CONFIG_CMD_EEPROM
 736 #define CONFIG_CMD_ERRATA
 737 #define CONFIG_CMD_IRQ
 738 #define CONFIG_CMD_REGINFO
 739
 740 #ifdef CONFIG_PCI
 741 #define CONFIG_CMD_PCI
 742 #endif
 743
 744 /* Hash command with SHA acceleration supported in hardware */
 745 #ifdef CONFIG_FSL_CAAM
 746 #define CONFIG_CMD_HASH
 747 #define CONFIG_SHA_HW_ACCEL
 748 #endif
 749
 750 /*
 751 * USB
 752 */
 753 #define CONFIG_HAS_FSL_DR_USB
 754
 755 #ifdef CONFIG_HAS_FSL_DR_USB
 756 #define CONFIG_USB_EHCI
 757
 758 #ifdef CONFIG_USB_EHCI
 759 #define CONFIG_USB_EHCI_FSL
 760 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 761 #endif
 762 #endif
 763
 764 /*
 765  * Miscellaneous configurable options
 766  */
 767 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 768 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 769 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 770 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 771 #ifdef CONFIG_CMD_KGDB
 772 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 773 #else
 774 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 775 #endif
 776 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 777 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 778 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 779
 780 /*
 781  * For booting Linux, the board info and command line data
 782  * have to be in the first 64 MB of memory, since this is
 783  * the maximum mapped by the Linux kernel during initialization.
 784  */
 785 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 786 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 787
 788 #ifdef CONFIG_CMD_KGDB
 789 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 790 #endif
 791
 792 /*
 793  * Environment Configuration
 794  */
 795 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 796 #define CONFIG_BOOTFILE         "uImage"
 797 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 798
 799 /* default location for tftp and bootm */
 800 #define CONFIG_LOADADDR         1000000
 801
 802
 803 #define CONFIG_BAUDRATE 115200
 804
 805 #define __USB_PHY_TYPE  ulpi
 806
 807 #ifdef CONFIG_PPC_B4860
 808 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,"     \
 809                         "bank_intlv=cs0_cs1;"   \
 810                         "en_cpc:cpc2;"
 811 #else
 812 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
 813 #endif
 814
 815 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 816         HWCONFIG                                                \
 817         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 818         "netdev=eth0\0"                                         \
 819         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 820         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"                     \
 821         "tftpflash=tftpboot $loadaddr $uboot && "               \
 822         "protect off $ubootaddr +$filesize && "                 \
 823         "erase $ubootaddr +$filesize && "                       \
 824         "cp.b $loadaddr $ubootaddr $filesize && "               \
 825         "protect on $ubootaddr +$filesize && "                  \
 826         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 827         "consoledev=ttyS0\0"                                    \
 828         "ramdiskaddr=2000000\0"                                 \
 829         "ramdiskfile=b4860qds/ramdisk.uboot\0"                  \
 830         "fdtaddr=1e00000\0"                                     \
 831         "fdtfile=b4860qds/b4860qds.dtb\0"                               \
 832         "bdev=sda3\0"
 833
 834 /* For emulation this causes u-boot to jump to the start of the proof point
 835    app code automatically */
 836 #define CONFIG_PROOF_POINTS                     \
 837  "setenv bootargs root=/dev/$bdev rw "          \
 838  "console=$consoledev,$baudrate $othbootargs;"  \
 839  "cpu 1 release 0x29000000 - - -;"              \
 840  "cpu 2 release 0x29000000 - - -;"              \
 841  "cpu 3 release 0x29000000 - - -;"              \
 842  "cpu 4 release 0x29000000 - - -;"              \
 843  "cpu 5 release 0x29000000 - - -;"              \
 844  "cpu 6 release 0x29000000 - - -;"              \
 845  "cpu 7 release 0x29000000 - - -;"              \
 846  "go 0x29000000"
 847
 848 #define CONFIG_HVBOOT   \
 849  "setenv bootargs config-addr=0x60000000; "     \
 850  "bootm 0x01000000 - 0x00f00000"
 851
 852 #define CONFIG_ALU                              \
 853  "setenv bootargs root=/dev/$bdev rw "          \
 854  "console=$consoledev,$baudrate $othbootargs;"  \
 855  "cpu 1 release 0x01000000 - - -;"              \
 856  "cpu 2 release 0x01000000 - - -;"              \
 857  "cpu 3 release 0x01000000 - - -;"              \
 858  "cpu 4 release 0x01000000 - - -;"              \
 859  "cpu 5 release 0x01000000 - - -;"              \
 860  "cpu 6 release 0x01000000 - - -;"              \
 861  "cpu 7 release 0x01000000 - - -;"              \
 862  "go 0x01000000"
 863
 864 #define CONFIG_LINUX                            \
 865  "setenv bootargs root=/dev/ram rw "            \
 866  "console=$consoledev,$baudrate $othbootargs;"  \
 867  "setenv ramdiskaddr 0x02000000;"               \
 868  "setenv fdtaddr 0x01e00000;"                   \
 869  "setenv loadaddr 0x1000000;"                   \
 870  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 871
 872 #define CONFIG_HDBOOT                                   \
 873         "setenv bootargs root=/dev/$bdev rw "           \
 874         "console=$consoledev,$baudrate $othbootargs;"   \
 875         "tftp $loadaddr $bootfile;"                     \
 876         "tftp $fdtaddr $fdtfile;"                       \
 877         "bootm $loadaddr - $fdtaddr"
 878
 879 #define CONFIG_NFSBOOTCOMMAND                   \
 880         "setenv bootargs root=/dev/nfs rw "     \
 881         "nfsroot=$serverip:$rootpath "          \
 882         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 883         "console=$consoledev,$baudrate $othbootargs;"   \
 884         "tftp $loadaddr $bootfile;"             \
 885         "tftp $fdtaddr $fdtfile;"               \
 886         "bootm $loadaddr - $fdtaddr"
 887
 888 #define CONFIG_RAMBOOTCOMMAND                           \
 889         "setenv bootargs root=/dev/ram rw "             \
 890         "console=$consoledev,$baudrate $othbootargs;"   \
 891         "tftp $ramdiskaddr $ramdiskfile;"               \
 892         "tftp $loadaddr $bootfile;"                     \
 893         "tftp $fdtaddr $fdtfile;"                       \
 894         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 895
 896 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 897
 898 #include <asm/fsl_secure_boot.h>
 899
 900 #endif  /* __CONFIG_H */