2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 * B4860 QDS board configuration file
13 #ifdef CONFIG_RAMBOOT_PBL
14 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
15 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
20 #define CONFIG_SPL_FLUSH_IMAGE
21 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
22 #define CONFIG_SYS_TEXT_BASE 0x00201000
23 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
24 #define CONFIG_SPL_PAD_TO 0x40000
25 #define CONFIG_SPL_MAX_SIZE 0x28000
26 #define RESET_VECTOR_OFFSET 0x27FFC
27 #define BOOT_PAGE_OFFSET 0x27000
28 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
29 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
30 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
31 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
32 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
33 #define CONFIG_SPL_NAND_BOOT
34 #ifdef CONFIG_SPL_BUILD
35 #define CONFIG_SPL_SKIP_RELOCATE
36 #define CONFIG_SPL_COMMON_INIT_DDR
37 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
42 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
43 /* Set 1M boot space */
44 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
45 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
46 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
47 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
50 /* High Level Configuration Options */
51 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
52 #define CONFIG_MP /* support multiple processors */
54 #ifndef CONFIG_SYS_TEXT_BASE
55 #define CONFIG_SYS_TEXT_BASE 0xeff40000
58 #ifndef CONFIG_RESET_VECTOR_ADDRESS
59 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
62 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
63 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
64 #define CONFIG_PCIE1 /* PCIE controller 1 */
65 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
66 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
68 #ifndef CONFIG_ARCH_B4420
69 #define CONFIG_SYS_SRIO
70 #define CONFIG_SRIO1 /* SRIO port 1 */
71 #define CONFIG_SRIO2 /* SRIO port 2 */
72 #define CONFIG_SRIO_PCIE_BOOT_MASTER
75 /* I2C bus multiplexer */
76 #define I2C_MUX_PCA_ADDR 0x77
78 /* VSC Crossbar switches */
79 #define CONFIG_VSC_CROSSBAR
80 #define I2C_CH_DEFAULT 0x8
81 #define I2C_CH_VSC3316 0xc
82 #define I2C_CH_VSC3308 0xd
84 #define VSC3316_TX_ADDRESS 0x70
85 #define VSC3316_RX_ADDRESS 0x71
86 #define VSC3308_TX_ADDRESS 0x02
87 #define VSC3308_RX_ADDRESS 0x03
89 /* IDT clock synthesizers */
90 #define CONFIG_IDT8T49N222A
91 #define I2C_CH_IDT 0x9
93 #define IDT_SERDES1_ADDRESS 0x6E
94 #define IDT_SERDES2_ADDRESS 0x6C
96 /* Voltage monitor on channel 2*/
97 #define I2C_MUX_CH_VOL_MONITOR 0xa
98 #define I2C_VOL_MONITOR_ADDR 0x40
99 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
100 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
101 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
103 #define CONFIG_ZM7300
104 #define I2C_MUX_CH_DPM 0xa
105 #define I2C_DPM_ADDR 0x28
107 #define CONFIG_ENV_OVERWRITE
109 #ifndef CONFIG_MTD_NOR_FLASH
111 #define CONFIG_FLASH_CFI_DRIVER
112 #define CONFIG_SYS_FLASH_CFI
113 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
116 #if defined(CONFIG_SPIFLASH)
117 #define CONFIG_SYS_EXTRA_ENV_RELOC
118 #define CONFIG_ENV_IS_IN_SPI_FLASH
119 #define CONFIG_ENV_SPI_BUS 0
120 #define CONFIG_ENV_SPI_CS 0
121 #define CONFIG_ENV_SPI_MAX_HZ 10000000
122 #define CONFIG_ENV_SPI_MODE 0
123 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
124 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
125 #define CONFIG_ENV_SECT_SIZE 0x10000
126 #elif defined(CONFIG_SDCARD)
127 #define CONFIG_SYS_EXTRA_ENV_RELOC
128 #define CONFIG_SYS_MMC_ENV_DEV 0
129 #define CONFIG_ENV_SIZE 0x2000
130 #define CONFIG_ENV_OFFSET (512 * 1097)
131 #elif defined(CONFIG_NAND)
132 #define CONFIG_SYS_EXTRA_ENV_RELOC
133 #define CONFIG_ENV_SIZE 0x2000
134 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
135 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
136 #define CONFIG_ENV_IS_IN_REMOTE
137 #define CONFIG_ENV_ADDR 0xffe20000
138 #define CONFIG_ENV_SIZE 0x2000
139 #elif defined(CONFIG_ENV_IS_NOWHERE)
140 #define CONFIG_ENV_SIZE 0x2000
142 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
143 #define CONFIG_ENV_SIZE 0x2000
144 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
148 unsigned long get_board_sys_clk(void);
149 unsigned long get_board_ddr_clk(void);
151 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
152 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
155 * These can be toggled for performance analysis, otherwise use default.
157 #define CONFIG_SYS_CACHE_STASHING
158 #define CONFIG_BTB /* toggle branch predition */
159 #define CONFIG_DDR_ECC
160 #ifdef CONFIG_DDR_ECC
161 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
162 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
165 #define CONFIG_ENABLE_36BIT_PHYS
167 #ifdef CONFIG_PHYS_64BIT
168 #define CONFIG_ADDR_MAP
169 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
173 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
175 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
176 #define CONFIG_SYS_MEMTEST_END 0x00400000
177 #define CONFIG_SYS_ALT_MEMTEST
178 #define CONFIG_PANIC_HANG /* do not reset board on panic */
181 * Config the L3 Cache as L3 SRAM
183 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
184 #define CONFIG_SYS_L3_SIZE 256 << 10
185 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
187 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
189 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
190 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
191 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
192 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
194 #ifdef CONFIG_PHYS_64BIT
195 #define CONFIG_SYS_DCSRBAR 0xf0000000
196 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
200 #define CONFIG_ID_EEPROM
201 #define CONFIG_SYS_I2C_EEPROM_NXID
202 #define CONFIG_SYS_EEPROM_BUS_NUM 0
203 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
204 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
205 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
206 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
211 #define CONFIG_VERY_BIG_RAM
212 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
213 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
215 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
216 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
218 #define CONFIG_DDR_SPD
219 #define CONFIG_SYS_DDR_RAW_TIMING
220 #ifndef CONFIG_SPL_BUILD
221 #define CONFIG_FSL_DDR_INTERACTIVE
224 #define CONFIG_SYS_SPD_BUS_NUM 0
225 #define SPD_EEPROM_ADDRESS1 0x51
226 #define SPD_EEPROM_ADDRESS2 0x53
228 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
229 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
234 #define CONFIG_SYS_FLASH_BASE 0xe0000000
235 #ifdef CONFIG_PHYS_64BIT
236 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
238 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
241 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
242 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
244 CSPR_PORT_SIZE_16 | \
247 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
248 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
249 CSPR_PORT_SIZE_16 | \
252 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
253 /* NOR Flash Timing Params */
254 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
255 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
256 FTIM0_NOR_TEADC(0x04) | \
257 FTIM0_NOR_TEAHC(0x20))
258 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
259 FTIM1_NOR_TRAD_NOR(0x1A) |\
260 FTIM1_NOR_TSEQRAD_NOR(0x13))
261 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
262 FTIM2_NOR_TCH(0x0E) | \
263 FTIM2_NOR_TWPH(0x0E) | \
265 #define CONFIG_SYS_NOR_FTIM3 0x0
267 #define CONFIG_SYS_FLASH_QUIET_TEST
268 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
270 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
271 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
272 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
273 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
275 #define CONFIG_SYS_FLASH_EMPTY_INFO
276 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
277 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
279 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
280 #define CONFIG_FSL_QIXIS_V2
281 #define QIXIS_BASE 0xffdf0000
282 #ifdef CONFIG_PHYS_64BIT
283 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
285 #define QIXIS_BASE_PHYS QIXIS_BASE
287 #define QIXIS_LBMAP_SWITCH 0x01
288 #define QIXIS_LBMAP_MASK 0x0f
289 #define QIXIS_LBMAP_SHIFT 0
290 #define QIXIS_LBMAP_DFLTBANK 0x00
291 #define QIXIS_LBMAP_ALTBANK 0x02
292 #define QIXIS_RST_CTL_RESET 0x31
293 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
294 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
295 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
297 #define CONFIG_SYS_CSPR3_EXT (0xf)
298 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
302 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024)
303 #define CONFIG_SYS_CSOR3 0x0
304 /* QIXIS Timing parameters for IFC CS3 */
305 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
306 FTIM0_GPCM_TEADC(0x0e) | \
307 FTIM0_GPCM_TEAHC(0x0e))
308 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
309 FTIM1_GPCM_TRAD(0x1f))
310 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
311 FTIM2_GPCM_TCH(0x8) | \
312 FTIM2_GPCM_TWP(0x1f))
313 #define CONFIG_SYS_CS3_FTIM3 0x0
315 /* NAND Flash on IFC */
316 #define CONFIG_NAND_FSL_IFC
317 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
318 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
319 #define CONFIG_SYS_NAND_BASE 0xff800000
320 #ifdef CONFIG_PHYS_64BIT
321 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
323 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
326 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
327 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
328 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
329 | CSPR_MSEL_NAND /* MSEL = NAND */ \
331 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
333 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
334 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
335 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
336 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
337 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
338 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
339 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
341 #define CONFIG_SYS_NAND_ONFI_DETECTION
343 /* ONFI NAND Flash mode0 Timing Params */
344 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
345 FTIM0_NAND_TWP(0x18) | \
346 FTIM0_NAND_TWCHT(0x07) | \
347 FTIM0_NAND_TWH(0x0a))
348 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
349 FTIM1_NAND_TWBE(0x39) | \
350 FTIM1_NAND_TRR(0x0e) | \
351 FTIM1_NAND_TRP(0x18))
352 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
353 FTIM2_NAND_TREH(0x0a) | \
354 FTIM2_NAND_TWHRE(0x1e))
355 #define CONFIG_SYS_NAND_FTIM3 0x0
357 #define CONFIG_SYS_NAND_DDR_LAW 11
359 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
360 #define CONFIG_SYS_MAX_NAND_DEVICE 1
361 #define CONFIG_CMD_NAND
363 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
365 #if defined(CONFIG_NAND)
366 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
367 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
368 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
369 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
370 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
371 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
372 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
373 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
374 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
375 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
376 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
377 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
378 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
379 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
380 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
381 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
383 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
384 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
385 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
386 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
387 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
388 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
389 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
390 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
391 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
392 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
393 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
394 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
395 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
396 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
397 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
398 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
400 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
401 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
402 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
403 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
404 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
405 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
406 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
407 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
409 #ifdef CONFIG_SPL_BUILD
410 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
412 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
415 #if defined(CONFIG_RAMBOOT_PBL)
416 #define CONFIG_SYS_RAMBOOT
419 #define CONFIG_BOARD_EARLY_INIT_R
420 #define CONFIG_MISC_INIT_R
422 #define CONFIG_HWCONFIG
424 /* define to use L1 as initial stack */
425 #define CONFIG_L1_INIT_RAM
426 #define CONFIG_SYS_INIT_RAM_LOCK
427 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
428 #ifdef CONFIG_PHYS_64BIT
429 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
430 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
431 /* The assembler doesn't like typecast */
432 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
433 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
434 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
436 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
437 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
438 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
440 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
442 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
443 GENERATED_GBL_DATA_SIZE)
444 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
446 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
447 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
449 /* Serial Port - controlled on board with jumper J8
453 #define CONFIG_CONS_INDEX 1
454 #define CONFIG_SYS_NS16550_SERIAL
455 #define CONFIG_SYS_NS16550_REG_SIZE 1
456 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
458 #define CONFIG_SYS_BAUDRATE_TABLE \
459 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
461 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
462 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
463 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
464 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
467 #define CONFIG_SYS_I2C
468 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
469 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
470 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
471 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
472 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
473 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
474 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
480 #define CONFIG_RTC_DS3231 1
481 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
486 #ifdef CONFIG_SYS_SRIO
488 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
489 #ifdef CONFIG_PHYS_64BIT
490 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
492 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
494 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
498 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
499 #ifdef CONFIG_PHYS_64BIT
500 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
502 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
504 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
509 * for slave u-boot IMAGE instored in master memory space,
510 * PHYS must be aligned based on the SIZE
512 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
513 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
514 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
515 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
517 * for slave UCODE and ENV instored in master memory space,
518 * PHYS must be aligned based on the SIZE
520 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
521 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
522 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
524 /* slave core release by master*/
525 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
526 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
529 * SRIO_PCIE_BOOT - SLAVE
531 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
532 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
533 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
534 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
538 * eSPI - Enhanced SPI
540 #define CONFIG_SF_DEFAULT_SPEED 10000000
541 #define CONFIG_SF_DEFAULT_MODE 0
546 #ifdef CONFIG_PHYS_64BIT
547 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull
549 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000
554 * Memory space is mapped 1-1, but I/O space must start from 0.
557 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
558 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
559 #ifdef CONFIG_PHYS_64BIT
560 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
561 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
563 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
564 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
566 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
567 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
568 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
569 #ifdef CONFIG_PHYS_64BIT
570 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
572 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
574 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
577 #ifndef CONFIG_NOBQFMAN
578 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
579 #define CONFIG_SYS_BMAN_NUM_PORTALS 25
580 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
581 #ifdef CONFIG_PHYS_64BIT
582 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
584 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
586 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
587 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
588 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
589 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
590 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
591 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
592 CONFIG_SYS_BMAN_CENA_SIZE)
593 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
594 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
595 #define CONFIG_SYS_QMAN_NUM_PORTALS 25
596 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
597 #ifdef CONFIG_PHYS_64BIT
598 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
600 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
602 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
603 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
604 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
605 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
606 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
607 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
608 CONFIG_SYS_QMAN_CENA_SIZE)
609 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
610 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
612 #define CONFIG_SYS_DPAA_FMAN
614 #define CONFIG_SYS_DPAA_RMAN
616 /* Default address of microcode for the Linux Fman driver */
617 #if defined(CONFIG_SPIFLASH)
619 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
620 * env, so we got 0x110000.
622 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
623 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
624 #elif defined(CONFIG_SDCARD)
626 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
627 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
628 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
630 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
631 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
632 #elif defined(CONFIG_NAND)
633 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
634 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
635 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
637 * Slave has no ucode locally, it can fetch this from remote. When implementing
638 * in two corenet boards, slave's ucode could be stored in master's memory
639 * space, the address can be mapped from slave TLB->slave LAW->
640 * slave SRIO or PCIE outbound window->master inbound window->
641 * master LAW->the ucode address in master's memory space.
643 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
644 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
646 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
647 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
649 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
650 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
651 #endif /* CONFIG_NOBQFMAN */
653 #ifdef CONFIG_SYS_DPAA_FMAN
654 #define CONFIG_FMAN_ENET
655 #define CONFIG_PHYLIB_10G
656 #define CONFIG_PHY_VITESSE
657 #define CONFIG_PHY_TERANETICS
658 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
659 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
660 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
661 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
665 #define CONFIG_PCI_INDIRECT_BRIDGE
667 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
668 #endif /* CONFIG_PCI */
670 #ifdef CONFIG_FMAN_ENET
671 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
672 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
674 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
675 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
676 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/
678 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
679 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
680 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
681 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
683 #define CONFIG_MII /* MII PHY management */
684 #define CONFIG_ETHPRIME "FM1@DTSEC1"
685 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
688 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
693 #define CONFIG_LOADS_ECHO /* echo on for serial download */
694 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
697 * Command line configuration.
699 #define CONFIG_CMD_REGINFO
702 #define CONFIG_CMD_PCI
708 #define CONFIG_HAS_FSL_DR_USB
710 #ifdef CONFIG_HAS_FSL_DR_USB
711 #ifdef CONFIG_USB_EHCI_HCD
712 #define CONFIG_USB_EHCI_FSL
713 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
718 * Miscellaneous configurable options
720 #define CONFIG_SYS_LONGHELP /* undef to save memory */
721 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
722 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
723 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
724 #ifdef CONFIG_CMD_KGDB
725 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
727 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
729 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
730 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
731 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
734 * For booting Linux, the board info and command line data
735 * have to be in the first 64 MB of memory, since this is
736 * the maximum mapped by the Linux kernel during initialization.
738 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
739 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
741 #ifdef CONFIG_CMD_KGDB
742 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
746 * Environment Configuration
748 #define CONFIG_ROOTPATH "/opt/nfsroot"
749 #define CONFIG_BOOTFILE "uImage"
750 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
752 /* default location for tftp and bootm */
753 #define CONFIG_LOADADDR 1000000
755 #define __USB_PHY_TYPE ulpi
757 #ifdef CONFIG_ARCH_B4860
758 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \
759 "bank_intlv=cs0_cs1;" \
762 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
765 #define CONFIG_EXTRA_ENV_SETTINGS \
767 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
769 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
770 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
771 "tftpflash=tftpboot $loadaddr $uboot && " \
772 "protect off $ubootaddr +$filesize && " \
773 "erase $ubootaddr +$filesize && " \
774 "cp.b $loadaddr $ubootaddr $filesize && " \
775 "protect on $ubootaddr +$filesize && " \
776 "cmp.b $loadaddr $ubootaddr $filesize\0" \
777 "consoledev=ttyS0\0" \
778 "ramdiskaddr=2000000\0" \
779 "ramdiskfile=b4860qds/ramdisk.uboot\0" \
780 "fdtaddr=1e00000\0" \
781 "fdtfile=b4860qds/b4860qds.dtb\0" \
784 /* For emulation this causes u-boot to jump to the start of the proof point
785 app code automatically */
786 #define CONFIG_PROOF_POINTS \
787 "setenv bootargs root=/dev/$bdev rw " \
788 "console=$consoledev,$baudrate $othbootargs;" \
789 "cpu 1 release 0x29000000 - - -;" \
790 "cpu 2 release 0x29000000 - - -;" \
791 "cpu 3 release 0x29000000 - - -;" \
792 "cpu 4 release 0x29000000 - - -;" \
793 "cpu 5 release 0x29000000 - - -;" \
794 "cpu 6 release 0x29000000 - - -;" \
795 "cpu 7 release 0x29000000 - - -;" \
798 #define CONFIG_HVBOOT \
799 "setenv bootargs config-addr=0x60000000; " \
800 "bootm 0x01000000 - 0x00f00000"
803 "setenv bootargs root=/dev/$bdev rw " \
804 "console=$consoledev,$baudrate $othbootargs;" \
805 "cpu 1 release 0x01000000 - - -;" \
806 "cpu 2 release 0x01000000 - - -;" \
807 "cpu 3 release 0x01000000 - - -;" \
808 "cpu 4 release 0x01000000 - - -;" \
809 "cpu 5 release 0x01000000 - - -;" \
810 "cpu 6 release 0x01000000 - - -;" \
811 "cpu 7 release 0x01000000 - - -;" \
814 #define CONFIG_LINUX \
815 "setenv bootargs root=/dev/ram rw " \
816 "console=$consoledev,$baudrate $othbootargs;" \
817 "setenv ramdiskaddr 0x02000000;" \
818 "setenv fdtaddr 0x01e00000;" \
819 "setenv loadaddr 0x1000000;" \
820 "bootm $loadaddr $ramdiskaddr $fdtaddr"
822 #define CONFIG_HDBOOT \
823 "setenv bootargs root=/dev/$bdev rw " \
824 "console=$consoledev,$baudrate $othbootargs;" \
825 "tftp $loadaddr $bootfile;" \
826 "tftp $fdtaddr $fdtfile;" \
827 "bootm $loadaddr - $fdtaddr"
829 #define CONFIG_NFSBOOTCOMMAND \
830 "setenv bootargs root=/dev/nfs rw " \
831 "nfsroot=$serverip:$rootpath " \
832 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
833 "console=$consoledev,$baudrate $othbootargs;" \
834 "tftp $loadaddr $bootfile;" \
835 "tftp $fdtaddr $fdtfile;" \
836 "bootm $loadaddr - $fdtaddr"
838 #define CONFIG_RAMBOOTCOMMAND \
839 "setenv bootargs root=/dev/ram rw " \
840 "console=$consoledev,$baudrate $othbootargs;" \
841 "tftp $ramdiskaddr $ramdiskfile;" \
842 "tftp $loadaddr $bootfile;" \
843 "tftp $fdtaddr $fdtfile;" \
844 "bootm $loadaddr $ramdiskaddr $fdtaddr"
846 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
848 #include <asm/fsl_secure_boot.h>
850 #endif /* __CONFIG_H */