2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 * B4860 QDS board configuration file
13 #define CONFIG_B4860QDS
15 #ifdef CONFIG_RAMBOOT_PBL
16 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
17 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
19 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
20 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
22 #define CONFIG_SPL_FLUSH_IMAGE
23 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
24 #define CONFIG_FSL_LAW /* Use common FSL init code */
25 #define CONFIG_SYS_TEXT_BASE 0x00201000
26 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
27 #define CONFIG_SPL_PAD_TO 0x40000
28 #define CONFIG_SPL_MAX_SIZE 0x28000
29 #define RESET_VECTOR_OFFSET 0x27FFC
30 #define BOOT_PAGE_OFFSET 0x27000
31 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
32 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
33 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
34 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
35 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
36 #define CONFIG_SPL_NAND_BOOT
37 #ifdef CONFIG_SPL_BUILD
38 #define CONFIG_SPL_SKIP_RELOCATE
39 #define CONFIG_SPL_COMMON_INIT_DDR
40 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
41 #define CONFIG_SYS_NO_FLASH
46 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
47 /* Set 1M boot space */
48 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
49 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
50 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
51 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
52 #define CONFIG_SYS_NO_FLASH
55 /* High Level Configuration Options */
57 #define CONFIG_E500 /* BOOKE e500 family */
58 #define CONFIG_E500MC /* BOOKE e500mc family */
59 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
60 #define CONFIG_MP /* support multiple processors */
62 #ifndef CONFIG_SYS_TEXT_BASE
63 #define CONFIG_SYS_TEXT_BASE 0xeff40000
66 #ifndef CONFIG_RESET_VECTOR_ADDRESS
67 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
70 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
71 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
72 #define CONFIG_FSL_IFC /* Enable IFC Support */
73 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
74 #define CONFIG_PCI /* Enable PCI/PCIE */
75 #define CONFIG_PCIE1 /* PCIE controller 1 */
76 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
77 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
79 #ifndef CONFIG_PPC_B4420
80 #define CONFIG_SYS_SRIO
81 #define CONFIG_SRIO1 /* SRIO port 1 */
82 #define CONFIG_SRIO2 /* SRIO port 2 */
83 #define CONFIG_SRIO_PCIE_BOOT_MASTER
86 #define CONFIG_FSL_LAW /* Use common FSL init code */
88 /* I2C bus multiplexer */
89 #define I2C_MUX_PCA_ADDR 0x77
91 /* VSC Crossbar switches */
92 #define CONFIG_VSC_CROSSBAR
93 #define I2C_CH_DEFAULT 0x8
94 #define I2C_CH_VSC3316 0xc
95 #define I2C_CH_VSC3308 0xd
97 #define VSC3316_TX_ADDRESS 0x70
98 #define VSC3316_RX_ADDRESS 0x71
99 #define VSC3308_TX_ADDRESS 0x02
100 #define VSC3308_RX_ADDRESS 0x03
102 /* IDT clock synthesizers */
103 #define CONFIG_IDT8T49N222A
104 #define I2C_CH_IDT 0x9
106 #define IDT_SERDES1_ADDRESS 0x6E
107 #define IDT_SERDES2_ADDRESS 0x6C
109 /* Voltage monitor on channel 2*/
110 #define I2C_MUX_CH_VOL_MONITOR 0xa
111 #define I2C_VOL_MONITOR_ADDR 0x40
112 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
113 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
114 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
116 #define CONFIG_ZM7300
117 #define I2C_MUX_CH_DPM 0xa
118 #define I2C_DPM_ADDR 0x28
120 #define CONFIG_ENV_OVERWRITE
122 #ifdef CONFIG_SYS_NO_FLASH
123 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
124 #define CONFIG_ENV_IS_NOWHERE
127 #define CONFIG_FLASH_CFI_DRIVER
128 #define CONFIG_SYS_FLASH_CFI
129 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
132 #if defined(CONFIG_SPIFLASH)
133 #define CONFIG_SYS_EXTRA_ENV_RELOC
134 #define CONFIG_ENV_IS_IN_SPI_FLASH
135 #define CONFIG_ENV_SPI_BUS 0
136 #define CONFIG_ENV_SPI_CS 0
137 #define CONFIG_ENV_SPI_MAX_HZ 10000000
138 #define CONFIG_ENV_SPI_MODE 0
139 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
140 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
141 #define CONFIG_ENV_SECT_SIZE 0x10000
142 #elif defined(CONFIG_SDCARD)
143 #define CONFIG_SYS_EXTRA_ENV_RELOC
144 #define CONFIG_ENV_IS_IN_MMC
145 #define CONFIG_SYS_MMC_ENV_DEV 0
146 #define CONFIG_ENV_SIZE 0x2000
147 #define CONFIG_ENV_OFFSET (512 * 1097)
148 #elif defined(CONFIG_NAND)
149 #define CONFIG_SYS_EXTRA_ENV_RELOC
150 #define CONFIG_ENV_IS_IN_NAND
151 #define CONFIG_ENV_SIZE 0x2000
152 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
153 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
154 #define CONFIG_ENV_IS_IN_REMOTE
155 #define CONFIG_ENV_ADDR 0xffe20000
156 #define CONFIG_ENV_SIZE 0x2000
157 #elif defined(CONFIG_ENV_IS_NOWHERE)
158 #define CONFIG_ENV_SIZE 0x2000
160 #define CONFIG_ENV_IS_IN_FLASH
161 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
162 #define CONFIG_ENV_SIZE 0x2000
163 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
167 unsigned long get_board_sys_clk(void);
168 unsigned long get_board_ddr_clk(void);
170 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
171 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
174 * These can be toggled for performance analysis, otherwise use default.
176 #define CONFIG_SYS_CACHE_STASHING
177 #define CONFIG_BTB /* toggle branch predition */
178 #define CONFIG_DDR_ECC
179 #ifdef CONFIG_DDR_ECC
180 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
181 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
184 #define CONFIG_ENABLE_36BIT_PHYS
186 #ifdef CONFIG_PHYS_64BIT
187 #define CONFIG_ADDR_MAP
188 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
192 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
194 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
195 #define CONFIG_SYS_MEMTEST_END 0x00400000
196 #define CONFIG_SYS_ALT_MEMTEST
197 #define CONFIG_PANIC_HANG /* do not reset board on panic */
200 * Config the L3 Cache as L3 SRAM
202 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
203 #define CONFIG_SYS_L3_SIZE 256 << 10
204 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
206 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
208 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
209 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
210 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
211 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
213 #ifdef CONFIG_PHYS_64BIT
214 #define CONFIG_SYS_DCSRBAR 0xf0000000
215 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
219 #define CONFIG_ID_EEPROM
220 #define CONFIG_SYS_I2C_EEPROM_NXID
221 #define CONFIG_SYS_EEPROM_BUS_NUM 0
222 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
223 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
224 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
225 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
230 #define CONFIG_VERY_BIG_RAM
231 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
232 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
234 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
235 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
236 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
238 #define CONFIG_DDR_SPD
239 #define CONFIG_SYS_DDR_RAW_TIMING
240 #define CONFIG_SYS_FSL_DDR3
241 #ifndef CONFIG_SPL_BUILD
242 #define CONFIG_FSL_DDR_INTERACTIVE
245 #define CONFIG_SYS_SPD_BUS_NUM 0
246 #define SPD_EEPROM_ADDRESS1 0x51
247 #define SPD_EEPROM_ADDRESS2 0x53
249 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
250 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
255 #define CONFIG_SYS_FLASH_BASE 0xe0000000
256 #ifdef CONFIG_PHYS_64BIT
257 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
259 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
262 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
263 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
265 CSPR_PORT_SIZE_16 | \
268 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
269 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
270 CSPR_PORT_SIZE_16 | \
273 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
274 /* NOR Flash Timing Params */
275 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
276 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
277 FTIM0_NOR_TEADC(0x04) | \
278 FTIM0_NOR_TEAHC(0x20))
279 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
280 FTIM1_NOR_TRAD_NOR(0x1A) |\
281 FTIM1_NOR_TSEQRAD_NOR(0x13))
282 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
283 FTIM2_NOR_TCH(0x0E) | \
284 FTIM2_NOR_TWPH(0x0E) | \
286 #define CONFIG_SYS_NOR_FTIM3 0x0
288 #define CONFIG_SYS_FLASH_QUIET_TEST
289 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
291 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
292 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
293 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
294 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
296 #define CONFIG_SYS_FLASH_EMPTY_INFO
297 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
298 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
300 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
301 #define CONFIG_FSL_QIXIS_V2
302 #define QIXIS_BASE 0xffdf0000
303 #ifdef CONFIG_PHYS_64BIT
304 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
306 #define QIXIS_BASE_PHYS QIXIS_BASE
308 #define QIXIS_LBMAP_SWITCH 0x01
309 #define QIXIS_LBMAP_MASK 0x0f
310 #define QIXIS_LBMAP_SHIFT 0
311 #define QIXIS_LBMAP_DFLTBANK 0x00
312 #define QIXIS_LBMAP_ALTBANK 0x02
313 #define QIXIS_RST_CTL_RESET 0x31
314 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
315 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
316 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
318 #define CONFIG_SYS_CSPR3_EXT (0xf)
319 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
323 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024)
324 #define CONFIG_SYS_CSOR3 0x0
325 /* QIXIS Timing parameters for IFC CS3 */
326 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
327 FTIM0_GPCM_TEADC(0x0e) | \
328 FTIM0_GPCM_TEAHC(0x0e))
329 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
330 FTIM1_GPCM_TRAD(0x1f))
331 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
332 FTIM2_GPCM_TCH(0x8) | \
333 FTIM2_GPCM_TWP(0x1f))
334 #define CONFIG_SYS_CS3_FTIM3 0x0
336 /* NAND Flash on IFC */
337 #define CONFIG_NAND_FSL_IFC
338 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
339 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
340 #define CONFIG_SYS_NAND_BASE 0xff800000
341 #ifdef CONFIG_PHYS_64BIT
342 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
344 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
347 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
348 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
349 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
350 | CSPR_MSEL_NAND /* MSEL = NAND */ \
352 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
354 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
355 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
356 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
357 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
358 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
359 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
360 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
362 #define CONFIG_SYS_NAND_ONFI_DETECTION
364 /* ONFI NAND Flash mode0 Timing Params */
365 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
366 FTIM0_NAND_TWP(0x18) | \
367 FTIM0_NAND_TWCHT(0x07) | \
368 FTIM0_NAND_TWH(0x0a))
369 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
370 FTIM1_NAND_TWBE(0x39) | \
371 FTIM1_NAND_TRR(0x0e) | \
372 FTIM1_NAND_TRP(0x18))
373 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
374 FTIM2_NAND_TREH(0x0a) | \
375 FTIM2_NAND_TWHRE(0x1e))
376 #define CONFIG_SYS_NAND_FTIM3 0x0
378 #define CONFIG_SYS_NAND_DDR_LAW 11
380 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
381 #define CONFIG_SYS_MAX_NAND_DEVICE 1
382 #define CONFIG_CMD_NAND
384 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
386 #if defined(CONFIG_NAND)
387 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
388 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
389 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
390 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
391 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
392 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
393 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
394 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
395 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
396 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
397 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
398 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
399 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
400 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
401 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
402 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
404 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
405 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
406 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
407 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
408 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
409 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
410 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
411 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
412 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
413 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
414 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
415 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
416 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
417 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
418 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
419 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
421 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
422 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
423 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
424 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
425 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
426 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
427 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
428 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
430 #ifdef CONFIG_SPL_BUILD
431 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
433 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
436 #if defined(CONFIG_RAMBOOT_PBL)
437 #define CONFIG_SYS_RAMBOOT
440 #define CONFIG_BOARD_EARLY_INIT_R
441 #define CONFIG_MISC_INIT_R
443 #define CONFIG_HWCONFIG
445 /* define to use L1 as initial stack */
446 #define CONFIG_L1_INIT_RAM
447 #define CONFIG_SYS_INIT_RAM_LOCK
448 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
449 #ifdef CONFIG_PHYS_64BIT
450 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
451 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
452 /* The assembler doesn't like typecast */
453 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
454 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
455 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
457 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
458 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
459 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
461 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
463 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
464 GENERATED_GBL_DATA_SIZE)
465 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
467 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
468 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
470 /* Serial Port - controlled on board with jumper J8
474 #define CONFIG_CONS_INDEX 1
475 #define CONFIG_SYS_NS16550_SERIAL
476 #define CONFIG_SYS_NS16550_REG_SIZE 1
477 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
479 #define CONFIG_SYS_BAUDRATE_TABLE \
480 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
482 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
483 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
484 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
485 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
486 #ifndef CONFIG_SPL_BUILD
487 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
491 #define CONFIG_SYS_I2C
492 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
493 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
494 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
495 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
496 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
497 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
498 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
504 #define CONFIG_RTC_DS3231 1
505 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
510 #ifdef CONFIG_SYS_SRIO
512 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
513 #ifdef CONFIG_PHYS_64BIT
514 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
516 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
518 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
522 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
523 #ifdef CONFIG_PHYS_64BIT
524 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
526 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
528 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
533 * for slave u-boot IMAGE instored in master memory space,
534 * PHYS must be aligned based on the SIZE
536 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
537 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
538 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
539 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
541 * for slave UCODE and ENV instored in master memory space,
542 * PHYS must be aligned based on the SIZE
544 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
545 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
546 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
548 /* slave core release by master*/
549 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
550 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
553 * SRIO_PCIE_BOOT - SLAVE
555 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
556 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
557 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
558 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
562 * eSPI - Enhanced SPI
564 #define CONFIG_SF_DEFAULT_SPEED 10000000
565 #define CONFIG_SF_DEFAULT_MODE 0
570 #ifdef CONFIG_PHYS_64BIT
571 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull
573 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000
578 * Memory space is mapped 1-1, but I/O space must start from 0.
581 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
582 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
583 #ifdef CONFIG_PHYS_64BIT
584 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
585 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
587 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
588 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
590 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
591 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
592 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
593 #ifdef CONFIG_PHYS_64BIT
594 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
596 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
598 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
601 #ifndef CONFIG_NOBQFMAN
602 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
603 #define CONFIG_SYS_BMAN_NUM_PORTALS 25
604 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
605 #ifdef CONFIG_PHYS_64BIT
606 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
608 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
610 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
611 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
612 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
613 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
614 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
615 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
616 CONFIG_SYS_BMAN_CENA_SIZE)
617 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
618 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
619 #define CONFIG_SYS_QMAN_NUM_PORTALS 25
620 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
621 #ifdef CONFIG_PHYS_64BIT
622 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
624 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
626 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
627 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
628 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
629 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
630 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
631 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
632 CONFIG_SYS_QMAN_CENA_SIZE)
633 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
634 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
636 #define CONFIG_SYS_DPAA_FMAN
638 #define CONFIG_SYS_DPAA_RMAN
640 /* Default address of microcode for the Linux Fman driver */
641 #if defined(CONFIG_SPIFLASH)
643 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
644 * env, so we got 0x110000.
646 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
647 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
648 #elif defined(CONFIG_SDCARD)
650 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
651 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
652 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
654 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
655 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
656 #elif defined(CONFIG_NAND)
657 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
658 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
659 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
661 * Slave has no ucode locally, it can fetch this from remote. When implementing
662 * in two corenet boards, slave's ucode could be stored in master's memory
663 * space, the address can be mapped from slave TLB->slave LAW->
664 * slave SRIO or PCIE outbound window->master inbound window->
665 * master LAW->the ucode address in master's memory space.
667 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
668 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
670 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
671 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
673 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
674 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
675 #endif /* CONFIG_NOBQFMAN */
677 #ifdef CONFIG_SYS_DPAA_FMAN
678 #define CONFIG_FMAN_ENET
679 #define CONFIG_PHYLIB_10G
680 #define CONFIG_PHY_VITESSE
681 #define CONFIG_PHY_TERANETICS
682 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
683 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
684 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
685 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
689 #define CONFIG_PCI_INDIRECT_BRIDGE
690 #define CONFIG_PCI_PNP /* do pci plug-and-play */
692 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
693 #define CONFIG_DOS_PARTITION
694 #endif /* CONFIG_PCI */
696 #ifdef CONFIG_FMAN_ENET
697 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
698 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
700 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
701 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
702 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/
704 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
705 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
706 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
707 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
709 #define CONFIG_MII /* MII PHY management */
710 #define CONFIG_ETHPRIME "FM1@DTSEC1"
711 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
714 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
719 #define CONFIG_LOADS_ECHO /* echo on for serial download */
720 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
723 * Command line configuration.
725 #define CONFIG_CMD_DATE
726 #define CONFIG_CMD_EEPROM
727 #define CONFIG_CMD_ERRATA
728 #define CONFIG_CMD_IRQ
729 #define CONFIG_CMD_REGINFO
732 #define CONFIG_CMD_PCI
735 /* Hash command with SHA acceleration supported in hardware */
736 #ifdef CONFIG_FSL_CAAM
737 #define CONFIG_CMD_HASH
738 #define CONFIG_SHA_HW_ACCEL
744 #define CONFIG_HAS_FSL_DR_USB
746 #ifdef CONFIG_HAS_FSL_DR_USB
747 #define CONFIG_USB_EHCI
749 #ifdef CONFIG_USB_EHCI
750 #define CONFIG_USB_EHCI_FSL
751 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
756 * Miscellaneous configurable options
758 #define CONFIG_SYS_LONGHELP /* undef to save memory */
759 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
760 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
761 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
762 #ifdef CONFIG_CMD_KGDB
763 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
765 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
767 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
768 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
769 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
772 * For booting Linux, the board info and command line data
773 * have to be in the first 64 MB of memory, since this is
774 * the maximum mapped by the Linux kernel during initialization.
776 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
777 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
779 #ifdef CONFIG_CMD_KGDB
780 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
784 * Environment Configuration
786 #define CONFIG_ROOTPATH "/opt/nfsroot"
787 #define CONFIG_BOOTFILE "uImage"
788 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
790 /* default location for tftp and bootm */
791 #define CONFIG_LOADADDR 1000000
794 #define CONFIG_BAUDRATE 115200
796 #define __USB_PHY_TYPE ulpi
798 #ifdef CONFIG_PPC_B4860
799 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \
800 "bank_intlv=cs0_cs1;" \
803 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
806 #define CONFIG_EXTRA_ENV_SETTINGS \
808 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
810 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
811 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
812 "tftpflash=tftpboot $loadaddr $uboot && " \
813 "protect off $ubootaddr +$filesize && " \
814 "erase $ubootaddr +$filesize && " \
815 "cp.b $loadaddr $ubootaddr $filesize && " \
816 "protect on $ubootaddr +$filesize && " \
817 "cmp.b $loadaddr $ubootaddr $filesize\0" \
818 "consoledev=ttyS0\0" \
819 "ramdiskaddr=2000000\0" \
820 "ramdiskfile=b4860qds/ramdisk.uboot\0" \
821 "fdtaddr=1e00000\0" \
822 "fdtfile=b4860qds/b4860qds.dtb\0" \
825 /* For emulation this causes u-boot to jump to the start of the proof point
826 app code automatically */
827 #define CONFIG_PROOF_POINTS \
828 "setenv bootargs root=/dev/$bdev rw " \
829 "console=$consoledev,$baudrate $othbootargs;" \
830 "cpu 1 release 0x29000000 - - -;" \
831 "cpu 2 release 0x29000000 - - -;" \
832 "cpu 3 release 0x29000000 - - -;" \
833 "cpu 4 release 0x29000000 - - -;" \
834 "cpu 5 release 0x29000000 - - -;" \
835 "cpu 6 release 0x29000000 - - -;" \
836 "cpu 7 release 0x29000000 - - -;" \
839 #define CONFIG_HVBOOT \
840 "setenv bootargs config-addr=0x60000000; " \
841 "bootm 0x01000000 - 0x00f00000"
844 "setenv bootargs root=/dev/$bdev rw " \
845 "console=$consoledev,$baudrate $othbootargs;" \
846 "cpu 1 release 0x01000000 - - -;" \
847 "cpu 2 release 0x01000000 - - -;" \
848 "cpu 3 release 0x01000000 - - -;" \
849 "cpu 4 release 0x01000000 - - -;" \
850 "cpu 5 release 0x01000000 - - -;" \
851 "cpu 6 release 0x01000000 - - -;" \
852 "cpu 7 release 0x01000000 - - -;" \
855 #define CONFIG_LINUX \
856 "setenv bootargs root=/dev/ram rw " \
857 "console=$consoledev,$baudrate $othbootargs;" \
858 "setenv ramdiskaddr 0x02000000;" \
859 "setenv fdtaddr 0x01e00000;" \
860 "setenv loadaddr 0x1000000;" \
861 "bootm $loadaddr $ramdiskaddr $fdtaddr"
863 #define CONFIG_HDBOOT \
864 "setenv bootargs root=/dev/$bdev rw " \
865 "console=$consoledev,$baudrate $othbootargs;" \
866 "tftp $loadaddr $bootfile;" \
867 "tftp $fdtaddr $fdtfile;" \
868 "bootm $loadaddr - $fdtaddr"
870 #define CONFIG_NFSBOOTCOMMAND \
871 "setenv bootargs root=/dev/nfs rw " \
872 "nfsroot=$serverip:$rootpath " \
873 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
874 "console=$consoledev,$baudrate $othbootargs;" \
875 "tftp $loadaddr $bootfile;" \
876 "tftp $fdtaddr $fdtfile;" \
877 "bootm $loadaddr - $fdtaddr"
879 #define CONFIG_RAMBOOTCOMMAND \
880 "setenv bootargs root=/dev/ram rw " \
881 "console=$consoledev,$baudrate $othbootargs;" \
882 "tftp $ramdiskaddr $ramdiskfile;" \
883 "tftp $loadaddr $bootfile;" \
884 "tftp $fdtaddr $fdtfile;" \
885 "bootm $loadaddr $ramdiskaddr $fdtaddr"
887 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
889 #include <asm/fsl_secure_boot.h>
891 #endif /* __CONFIG_H */