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[u-boot] / include / configs / B4860QDS.h
1 /*
2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9
10 /*
11  * B4860 QDS board configuration file
12  */
13 #ifdef CONFIG_RAMBOOT_PBL
14 #define CONFIG_SYS_FSL_PBL_PBI  $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
15 #define CONFIG_SYS_FSL_PBL_RCW  $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
16 #ifndef CONFIG_NAND
17 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
18 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
19 #else
20 #define CONFIG_SPL_FLUSH_IMAGE
21 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
22 #define CONFIG_SYS_TEXT_BASE            0x00201000
23 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
24 #define CONFIG_SPL_PAD_TO               0x40000
25 #define CONFIG_SPL_MAX_SIZE             0x28000
26 #define RESET_VECTOR_OFFSET             0x27FFC
27 #define BOOT_PAGE_OFFSET                0x27000
28 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
29 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
30 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
31 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
32 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
33 #define CONFIG_SPL_NAND_BOOT
34 #ifdef CONFIG_SPL_BUILD
35 #define CONFIG_SPL_SKIP_RELOCATE
36 #define CONFIG_SPL_COMMON_INIT_DDR
37 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
38 #endif
39 #endif
40 #endif
41
42 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
43 /* Set 1M boot space */
44 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
45 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
46                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
47 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
48 #endif
49
50 /* High Level Configuration Options */
51 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
52 #define CONFIG_MP                       /* support multiple processors */
53
54 #ifndef CONFIG_SYS_TEXT_BASE
55 #define CONFIG_SYS_TEXT_BASE    0xeff40000
56 #endif
57
58 #ifndef CONFIG_RESET_VECTOR_ADDRESS
59 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
60 #endif
61
62 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
63 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
64 #define CONFIG_PCIE1                    /* PCIE controller 1 */
65 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
66 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
67
68 #ifndef CONFIG_ARCH_B4420
69 #define CONFIG_SYS_SRIO
70 #define CONFIG_SRIO1                    /* SRIO port 1 */
71 #define CONFIG_SRIO2                    /* SRIO port 2 */
72 #define CONFIG_SRIO_PCIE_BOOT_MASTER
73 #endif
74
75 /* I2C bus multiplexer */
76 #define I2C_MUX_PCA_ADDR                0x77
77
78 /* VSC Crossbar switches */
79 #define CONFIG_VSC_CROSSBAR
80 #define I2C_CH_DEFAULT                  0x8
81 #define I2C_CH_VSC3316                  0xc
82 #define I2C_CH_VSC3308                  0xd
83
84 #define VSC3316_TX_ADDRESS              0x70
85 #define VSC3316_RX_ADDRESS              0x71
86 #define VSC3308_TX_ADDRESS              0x02
87 #define VSC3308_RX_ADDRESS              0x03
88
89 /* IDT clock synthesizers */
90 #define CONFIG_IDT8T49N222A
91 #define I2C_CH_IDT                     0x9
92
93 #define IDT_SERDES1_ADDRESS            0x6E
94 #define IDT_SERDES2_ADDRESS            0x6C
95
96 /* Voltage monitor on channel 2*/
97 #define I2C_MUX_CH_VOL_MONITOR          0xa
98 #define I2C_VOL_MONITOR_ADDR            0x40
99 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
100 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
101 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
102
103 #define CONFIG_ZM7300
104 #define I2C_MUX_CH_DPM                  0xa
105 #define I2C_DPM_ADDR                    0x28
106
107 #define CONFIG_ENV_OVERWRITE
108
109 #ifndef CONFIG_MTD_NOR_FLASH
110 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
111 #define CONFIG_ENV_IS_NOWHERE
112 #endif
113 #else
114 #define CONFIG_FLASH_CFI_DRIVER
115 #define CONFIG_SYS_FLASH_CFI
116 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
117 #endif
118
119 #if defined(CONFIG_SPIFLASH)
120 #define CONFIG_SYS_EXTRA_ENV_RELOC
121 #define CONFIG_ENV_IS_IN_SPI_FLASH
122 #define CONFIG_ENV_SPI_BUS              0
123 #define CONFIG_ENV_SPI_CS               0
124 #define CONFIG_ENV_SPI_MAX_HZ           10000000
125 #define CONFIG_ENV_SPI_MODE             0
126 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
127 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
128 #define CONFIG_ENV_SECT_SIZE            0x10000
129 #elif defined(CONFIG_SDCARD)
130 #define CONFIG_SYS_EXTRA_ENV_RELOC
131 #define CONFIG_ENV_IS_IN_MMC
132 #define CONFIG_SYS_MMC_ENV_DEV          0
133 #define CONFIG_ENV_SIZE                 0x2000
134 #define CONFIG_ENV_OFFSET               (512 * 1097)
135 #elif defined(CONFIG_NAND)
136 #define CONFIG_SYS_EXTRA_ENV_RELOC
137 #define CONFIG_ENV_IS_IN_NAND
138 #define CONFIG_ENV_SIZE                 0x2000
139 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
140 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
141 #define CONFIG_ENV_IS_IN_REMOTE
142 #define CONFIG_ENV_ADDR         0xffe20000
143 #define CONFIG_ENV_SIZE         0x2000
144 #elif defined(CONFIG_ENV_IS_NOWHERE)
145 #define CONFIG_ENV_SIZE         0x2000
146 #else
147 #define CONFIG_ENV_IS_IN_FLASH
148 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
149 #define CONFIG_ENV_SIZE         0x2000
150 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
151 #endif
152
153 #ifndef __ASSEMBLY__
154 unsigned long get_board_sys_clk(void);
155 unsigned long get_board_ddr_clk(void);
156 #endif
157 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
158 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
159
160 /*
161  * These can be toggled for performance analysis, otherwise use default.
162  */
163 #define CONFIG_SYS_CACHE_STASHING
164 #define CONFIG_BTB                      /* toggle branch predition */
165 #define CONFIG_DDR_ECC
166 #ifdef CONFIG_DDR_ECC
167 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
168 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
169 #endif
170
171 #define CONFIG_ENABLE_36BIT_PHYS
172
173 #ifdef CONFIG_PHYS_64BIT
174 #define CONFIG_ADDR_MAP
175 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
176 #endif
177
178 #if 0
179 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
180 #endif
181 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
182 #define CONFIG_SYS_MEMTEST_END          0x00400000
183 #define CONFIG_SYS_ALT_MEMTEST
184 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
185
186 /*
187  *  Config the L3 Cache as L3 SRAM
188  */
189 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
190 #define CONFIG_SYS_L3_SIZE              256 << 10
191 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
192 #ifdef CONFIG_NAND
193 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
194 #endif
195 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
196 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
197 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
198 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
199
200 #ifdef CONFIG_PHYS_64BIT
201 #define CONFIG_SYS_DCSRBAR              0xf0000000
202 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
203 #endif
204
205 /* EEPROM */
206 #define CONFIG_ID_EEPROM
207 #define CONFIG_SYS_I2C_EEPROM_NXID
208 #define CONFIG_SYS_EEPROM_BUS_NUM       0
209 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
210 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
211 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
212 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
213
214 /*
215  * DDR Setup
216  */
217 #define CONFIG_VERY_BIG_RAM
218 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
219 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
220
221 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
222 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
223
224 #define CONFIG_DDR_SPD
225 #define CONFIG_SYS_DDR_RAW_TIMING
226 #ifndef CONFIG_SPL_BUILD
227 #define CONFIG_FSL_DDR_INTERACTIVE
228 #endif
229
230 #define CONFIG_SYS_SPD_BUS_NUM  0
231 #define SPD_EEPROM_ADDRESS1     0x51
232 #define SPD_EEPROM_ADDRESS2     0x53
233
234 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
235 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
236
237 /*
238  * IFC Definitions
239  */
240 #define CONFIG_SYS_FLASH_BASE   0xe0000000
241 #ifdef CONFIG_PHYS_64BIT
242 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
243 #else
244 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
245 #endif
246
247 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
248 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
249                                 + 0x8000000) | \
250                                 CSPR_PORT_SIZE_16 | \
251                                 CSPR_MSEL_NOR | \
252                                 CSPR_V)
253 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
254 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
255                                 CSPR_PORT_SIZE_16 | \
256                                 CSPR_MSEL_NOR | \
257                                 CSPR_V)
258 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128 * 1024 * 1024)
259 /* NOR Flash Timing Params */
260 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(4)
261 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x01) | \
262                                 FTIM0_NOR_TEADC(0x04) | \
263                                 FTIM0_NOR_TEAHC(0x20))
264 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
265                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
266                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
267 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x01) | \
268                                 FTIM2_NOR_TCH(0x0E) | \
269                                 FTIM2_NOR_TWPH(0x0E) | \
270                                 FTIM2_NOR_TWP(0x1c))
271 #define CONFIG_SYS_NOR_FTIM3    0x0
272
273 #define CONFIG_SYS_FLASH_QUIET_TEST
274 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
275
276 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
277 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
278 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
279 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
280
281 #define CONFIG_SYS_FLASH_EMPTY_INFO
282 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
283                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
284
285 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
286 #define CONFIG_FSL_QIXIS_V2
287 #define QIXIS_BASE              0xffdf0000
288 #ifdef CONFIG_PHYS_64BIT
289 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
290 #else
291 #define QIXIS_BASE_PHYS         QIXIS_BASE
292 #endif
293 #define QIXIS_LBMAP_SWITCH              0x01
294 #define QIXIS_LBMAP_MASK                0x0f
295 #define QIXIS_LBMAP_SHIFT               0
296 #define QIXIS_LBMAP_DFLTBANK            0x00
297 #define QIXIS_LBMAP_ALTBANK             0x02
298 #define QIXIS_RST_CTL_RESET             0x31
299 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
300 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
301 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
302
303 #define CONFIG_SYS_CSPR3_EXT    (0xf)
304 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
305                                 | CSPR_PORT_SIZE_8 \
306                                 | CSPR_MSEL_GPCM \
307                                 | CSPR_V)
308 #define CONFIG_SYS_AMASK3       IFC_AMASK(4 * 1024)
309 #define CONFIG_SYS_CSOR3        0x0
310 /* QIXIS Timing parameters for IFC CS3 */
311 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
312                                         FTIM0_GPCM_TEADC(0x0e) | \
313                                         FTIM0_GPCM_TEAHC(0x0e))
314 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
315                                         FTIM1_GPCM_TRAD(0x1f))
316 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
317                                         FTIM2_GPCM_TCH(0x8) | \
318                                         FTIM2_GPCM_TWP(0x1f))
319 #define CONFIG_SYS_CS3_FTIM3            0x0
320
321 /* NAND Flash on IFC */
322 #define CONFIG_NAND_FSL_IFC
323 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
324 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
325 #define CONFIG_SYS_NAND_BASE            0xff800000
326 #ifdef CONFIG_PHYS_64BIT
327 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
328 #else
329 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
330 #endif
331
332 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
333 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
334                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
335                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
336                                 | CSPR_V)
337 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
338
339 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
340                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
341                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
342                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
343                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
344                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
345                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
346
347 #define CONFIG_SYS_NAND_ONFI_DETECTION
348
349 /* ONFI NAND Flash mode0 Timing Params */
350 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
351                                         FTIM0_NAND_TWP(0x18)   | \
352                                         FTIM0_NAND_TWCHT(0x07) | \
353                                         FTIM0_NAND_TWH(0x0a))
354 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
355                                         FTIM1_NAND_TWBE(0x39)  | \
356                                         FTIM1_NAND_TRR(0x0e)   | \
357                                         FTIM1_NAND_TRP(0x18))
358 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
359                                         FTIM2_NAND_TREH(0x0a) | \
360                                         FTIM2_NAND_TWHRE(0x1e))
361 #define CONFIG_SYS_NAND_FTIM3           0x0
362
363 #define CONFIG_SYS_NAND_DDR_LAW         11
364
365 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
366 #define CONFIG_SYS_MAX_NAND_DEVICE      1
367 #define CONFIG_CMD_NAND
368
369 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
370
371 #if defined(CONFIG_NAND)
372 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
373 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
374 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
375 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
376 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
377 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
378 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
379 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
380 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
381 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
382 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
383 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
384 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
385 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
386 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
387 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
388 #else
389 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
390 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
391 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
392 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
393 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
394 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
395 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
396 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
397 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
398 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
399 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
400 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
401 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
402 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
403 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
404 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
405 #endif
406 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
407 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
408 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
409 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
410 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
411 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
412 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
413 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
414
415 #ifdef CONFIG_SPL_BUILD
416 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
417 #else
418 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
419 #endif
420
421 #if defined(CONFIG_RAMBOOT_PBL)
422 #define CONFIG_SYS_RAMBOOT
423 #endif
424
425 #define CONFIG_BOARD_EARLY_INIT_R
426 #define CONFIG_MISC_INIT_R
427
428 #define CONFIG_HWCONFIG
429
430 /* define to use L1 as initial stack */
431 #define CONFIG_L1_INIT_RAM
432 #define CONFIG_SYS_INIT_RAM_LOCK
433 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
434 #ifdef CONFIG_PHYS_64BIT
435 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
436 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
437 /* The assembler doesn't like typecast */
438 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
439         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
440           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
441 #else
442 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
443 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
444 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
445 #endif
446 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
447
448 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
449                                         GENERATED_GBL_DATA_SIZE)
450 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
451
452 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
453 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
454
455 /* Serial Port - controlled on board with jumper J8
456  * open - index 2
457  * shorted - index 1
458  */
459 #define CONFIG_CONS_INDEX       1
460 #define CONFIG_SYS_NS16550_SERIAL
461 #define CONFIG_SYS_NS16550_REG_SIZE     1
462 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
463
464 #define CONFIG_SYS_BAUDRATE_TABLE       \
465         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
466
467 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
468 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
469 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
470 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
471
472 /* I2C */
473 #define CONFIG_SYS_I2C
474 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
475 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
476 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
477 #define CONFIG_SYS_FSL_I2C2_SPEED       400000  /* I2C speed in Hz */
478 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
479 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
480 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x119000
481
482 /*
483  * RTC configuration
484  */
485 #define RTC
486 #define CONFIG_RTC_DS3231               1
487 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
488
489 /*
490  * RapidIO
491  */
492 #ifdef CONFIG_SYS_SRIO
493 #ifdef CONFIG_SRIO1
494 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
495 #ifdef CONFIG_PHYS_64BIT
496 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
497 #else
498 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
499 #endif
500 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
501 #endif
502
503 #ifdef CONFIG_SRIO2
504 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
505 #ifdef CONFIG_PHYS_64BIT
506 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
507 #else
508 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
509 #endif
510 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
511 #endif
512 #endif
513
514 /*
515  * for slave u-boot IMAGE instored in master memory space,
516  * PHYS must be aligned based on the SIZE
517  */
518 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
519 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
520 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
521 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
522 /*
523  * for slave UCODE and ENV instored in master memory space,
524  * PHYS must be aligned based on the SIZE
525  */
526 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
527 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
528 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
529
530 /* slave core release by master*/
531 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
532 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
533
534 /*
535  * SRIO_PCIE_BOOT - SLAVE
536  */
537 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
538 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
539 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
540                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
541 #endif
542
543 /*
544  * eSPI - Enhanced SPI
545  */
546 #define CONFIG_SF_DEFAULT_SPEED         10000000
547 #define CONFIG_SF_DEFAULT_MODE          0
548
549 /*
550  * MAPLE
551  */
552 #ifdef CONFIG_PHYS_64BIT
553 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xFA0000000ull
554 #else
555 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xA0000000
556 #endif
557
558 /*
559  * General PCI
560  * Memory space is mapped 1-1, but I/O space must start from 0.
561  */
562
563 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
564 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
565 #ifdef CONFIG_PHYS_64BIT
566 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
567 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
568 #else
569 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
570 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
571 #endif
572 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
573 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
574 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
575 #ifdef CONFIG_PHYS_64BIT
576 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
577 #else
578 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
579 #endif
580 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
581
582 /* Qman/Bman */
583 #ifndef CONFIG_NOBQFMAN
584 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
585 #define CONFIG_SYS_BMAN_NUM_PORTALS     25
586 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
587 #ifdef CONFIG_PHYS_64BIT
588 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
589 #else
590 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
591 #endif
592 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
593 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
594 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
595 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
596 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
597 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
598                                         CONFIG_SYS_BMAN_CENA_SIZE)
599 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
600 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
601 #define CONFIG_SYS_QMAN_NUM_PORTALS     25
602 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
603 #ifdef CONFIG_PHYS_64BIT
604 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
605 #else
606 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
607 #endif
608 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
609 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
610 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
611 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
612 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
613 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
614                                         CONFIG_SYS_QMAN_CENA_SIZE)
615 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
616 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
617
618 #define CONFIG_SYS_DPAA_FMAN
619
620 #define CONFIG_SYS_DPAA_RMAN
621
622 /* Default address of microcode for the Linux Fman driver */
623 #if defined(CONFIG_SPIFLASH)
624 /*
625  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
626  * env, so we got 0x110000.
627  */
628 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
629 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
630 #elif defined(CONFIG_SDCARD)
631 /*
632  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
633  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
634  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
635  */
636 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
637 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
638 #elif defined(CONFIG_NAND)
639 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
640 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
641 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
642 /*
643  * Slave has no ucode locally, it can fetch this from remote. When implementing
644  * in two corenet boards, slave's ucode could be stored in master's memory
645  * space, the address can be mapped from slave TLB->slave LAW->
646  * slave SRIO or PCIE outbound window->master inbound window->
647  * master LAW->the ucode address in master's memory space.
648  */
649 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
650 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
651 #else
652 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
653 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
654 #endif
655 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
656 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
657 #endif /* CONFIG_NOBQFMAN */
658
659 #ifdef CONFIG_SYS_DPAA_FMAN
660 #define CONFIG_FMAN_ENET
661 #define CONFIG_PHYLIB_10G
662 #define CONFIG_PHY_VITESSE
663 #define CONFIG_PHY_TERANETICS
664 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
665 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
666 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
667 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
668 #endif
669
670 #ifdef CONFIG_PCI
671 #define CONFIG_PCI_INDIRECT_BRIDGE
672
673 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
674 #endif  /* CONFIG_PCI */
675
676 #ifdef CONFIG_FMAN_ENET
677 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
678 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
679
680 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
681 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7       /*SLOT 1*/
682 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6       /*SLOT 2*/
683
684 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
685 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
686 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
687 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
688
689 #define CONFIG_MII              /* MII PHY management */
690 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
691 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
692 #endif
693
694 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
695
696 /*
697  * Environment
698  */
699 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
700 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
701
702 /*
703  * Command line configuration.
704  */
705 #define CONFIG_CMD_EEPROM
706 #define CONFIG_CMD_ERRATA
707 #define CONFIG_CMD_IRQ
708 #define CONFIG_CMD_REGINFO
709
710 #ifdef CONFIG_PCI
711 #define CONFIG_CMD_PCI
712 #endif
713
714 /* Hash command with SHA acceleration supported in hardware */
715 #ifdef CONFIG_FSL_CAAM
716 #define CONFIG_CMD_HASH
717 #define CONFIG_SHA_HW_ACCEL
718 #endif
719
720 /*
721 * USB
722 */
723 #define CONFIG_HAS_FSL_DR_USB
724
725 #ifdef CONFIG_HAS_FSL_DR_USB
726 #define CONFIG_USB_EHCI_HCD
727
728 #ifdef CONFIG_USB_EHCI_HCD
729 #define CONFIG_USB_EHCI_FSL
730 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
731 #endif
732 #endif
733
734 /*
735  * Miscellaneous configurable options
736  */
737 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
738 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
739 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
740 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
741 #ifdef CONFIG_CMD_KGDB
742 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
743 #else
744 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
745 #endif
746 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
747 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
748 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
749
750 /*
751  * For booting Linux, the board info and command line data
752  * have to be in the first 64 MB of memory, since this is
753  * the maximum mapped by the Linux kernel during initialization.
754  */
755 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
756 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
757
758 #ifdef CONFIG_CMD_KGDB
759 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
760 #endif
761
762 /*
763  * Environment Configuration
764  */
765 #define CONFIG_ROOTPATH         "/opt/nfsroot"
766 #define CONFIG_BOOTFILE         "uImage"
767 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
768
769 /* default location for tftp and bootm */
770 #define CONFIG_LOADADDR         1000000
771
772 #define __USB_PHY_TYPE  ulpi
773
774 #ifdef CONFIG_ARCH_B4860
775 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,"     \
776                         "bank_intlv=cs0_cs1;"   \
777                         "en_cpc:cpc2;"
778 #else
779 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
780 #endif
781
782 #define CONFIG_EXTRA_ENV_SETTINGS                               \
783         HWCONFIG                                                \
784         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
785         "netdev=eth0\0"                                         \
786         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
787         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"                     \
788         "tftpflash=tftpboot $loadaddr $uboot && "               \
789         "protect off $ubootaddr +$filesize && "                 \
790         "erase $ubootaddr +$filesize && "                       \
791         "cp.b $loadaddr $ubootaddr $filesize && "               \
792         "protect on $ubootaddr +$filesize && "                  \
793         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
794         "consoledev=ttyS0\0"                                    \
795         "ramdiskaddr=2000000\0"                                 \
796         "ramdiskfile=b4860qds/ramdisk.uboot\0"                  \
797         "fdtaddr=1e00000\0"                                     \
798         "fdtfile=b4860qds/b4860qds.dtb\0"                               \
799         "bdev=sda3\0"
800
801 /* For emulation this causes u-boot to jump to the start of the proof point
802    app code automatically */
803 #define CONFIG_PROOF_POINTS                     \
804  "setenv bootargs root=/dev/$bdev rw "          \
805  "console=$consoledev,$baudrate $othbootargs;"  \
806  "cpu 1 release 0x29000000 - - -;"              \
807  "cpu 2 release 0x29000000 - - -;"              \
808  "cpu 3 release 0x29000000 - - -;"              \
809  "cpu 4 release 0x29000000 - - -;"              \
810  "cpu 5 release 0x29000000 - - -;"              \
811  "cpu 6 release 0x29000000 - - -;"              \
812  "cpu 7 release 0x29000000 - - -;"              \
813  "go 0x29000000"
814
815 #define CONFIG_HVBOOT   \
816  "setenv bootargs config-addr=0x60000000; "     \
817  "bootm 0x01000000 - 0x00f00000"
818
819 #define CONFIG_ALU                              \
820  "setenv bootargs root=/dev/$bdev rw "          \
821  "console=$consoledev,$baudrate $othbootargs;"  \
822  "cpu 1 release 0x01000000 - - -;"              \
823  "cpu 2 release 0x01000000 - - -;"              \
824  "cpu 3 release 0x01000000 - - -;"              \
825  "cpu 4 release 0x01000000 - - -;"              \
826  "cpu 5 release 0x01000000 - - -;"              \
827  "cpu 6 release 0x01000000 - - -;"              \
828  "cpu 7 release 0x01000000 - - -;"              \
829  "go 0x01000000"
830
831 #define CONFIG_LINUX                            \
832  "setenv bootargs root=/dev/ram rw "            \
833  "console=$consoledev,$baudrate $othbootargs;"  \
834  "setenv ramdiskaddr 0x02000000;"               \
835  "setenv fdtaddr 0x01e00000;"                   \
836  "setenv loadaddr 0x1000000;"                   \
837  "bootm $loadaddr $ramdiskaddr $fdtaddr"
838
839 #define CONFIG_HDBOOT                                   \
840         "setenv bootargs root=/dev/$bdev rw "           \
841         "console=$consoledev,$baudrate $othbootargs;"   \
842         "tftp $loadaddr $bootfile;"                     \
843         "tftp $fdtaddr $fdtfile;"                       \
844         "bootm $loadaddr - $fdtaddr"
845
846 #define CONFIG_NFSBOOTCOMMAND                   \
847         "setenv bootargs root=/dev/nfs rw "     \
848         "nfsroot=$serverip:$rootpath "          \
849         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
850         "console=$consoledev,$baudrate $othbootargs;"   \
851         "tftp $loadaddr $bootfile;"             \
852         "tftp $fdtaddr $fdtfile;"               \
853         "bootm $loadaddr - $fdtaddr"
854
855 #define CONFIG_RAMBOOTCOMMAND                           \
856         "setenv bootargs root=/dev/ram rw "             \
857         "console=$consoledev,$baudrate $othbootargs;"   \
858         "tftp $ramdiskaddr $ramdiskfile;"               \
859         "tftp $loadaddr $bootfile;"                     \
860         "tftp $fdtaddr $fdtfile;"                       \
861         "bootm $loadaddr $ramdiskaddr $fdtaddr"
862
863 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
864
865 #include <asm/fsl_secure_boot.h>
866
867 #endif  /* __CONFIG_H */