2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #define CONFIG_DISPLAY_BOARDINFO
13 * B4860 QDS board configuration file
15 #define CONFIG_B4860QDS
17 #ifdef CONFIG_RAMBOOT_PBL
18 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
19 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
21 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
22 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
24 #define CONFIG_SPL_SERIAL_SUPPORT
25 #define CONFIG_SPL_FLUSH_IMAGE
26 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
27 #define CONFIG_FSL_LAW /* Use common FSL init code */
28 #define CONFIG_SYS_TEXT_BASE 0x00201000
29 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
30 #define CONFIG_SPL_PAD_TO 0x40000
31 #define CONFIG_SPL_MAX_SIZE 0x28000
32 #define RESET_VECTOR_OFFSET 0x27FFC
33 #define BOOT_PAGE_OFFSET 0x27000
34 #define CONFIG_SPL_NAND_SUPPORT
35 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
36 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
37 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
38 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
39 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
40 #define CONFIG_SPL_NAND_BOOT
41 #ifdef CONFIG_SPL_BUILD
42 #define CONFIG_SPL_SKIP_RELOCATE
43 #define CONFIG_SPL_COMMON_INIT_DDR
44 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
45 #define CONFIG_SYS_NO_FLASH
50 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
51 /* Set 1M boot space */
52 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
53 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
54 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
55 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
56 #define CONFIG_SYS_NO_FLASH
59 /* High Level Configuration Options */
61 #define CONFIG_E500 /* BOOKE e500 family */
62 #define CONFIG_E500MC /* BOOKE e500mc family */
63 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
64 #define CONFIG_MP /* support multiple processors */
66 #ifndef CONFIG_SYS_TEXT_BASE
67 #define CONFIG_SYS_TEXT_BASE 0xeff40000
70 #ifndef CONFIG_RESET_VECTOR_ADDRESS
71 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
74 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
75 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
76 #define CONFIG_FSL_IFC /* Enable IFC Support */
77 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
78 #define CONFIG_PCI /* Enable PCI/PCIE */
79 #define CONFIG_PCIE1 /* PCIE controller 1 */
80 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
81 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
83 #ifndef CONFIG_PPC_B4420
84 #define CONFIG_SYS_SRIO
85 #define CONFIG_SRIO1 /* SRIO port 1 */
86 #define CONFIG_SRIO2 /* SRIO port 2 */
87 #define CONFIG_SRIO_PCIE_BOOT_MASTER
90 #define CONFIG_FSL_LAW /* Use common FSL init code */
92 /* I2C bus multiplexer */
93 #define I2C_MUX_PCA_ADDR 0x77
95 /* VSC Crossbar switches */
96 #define CONFIG_VSC_CROSSBAR
97 #define I2C_CH_DEFAULT 0x8
98 #define I2C_CH_VSC3316 0xc
99 #define I2C_CH_VSC3308 0xd
101 #define VSC3316_TX_ADDRESS 0x70
102 #define VSC3316_RX_ADDRESS 0x71
103 #define VSC3308_TX_ADDRESS 0x02
104 #define VSC3308_RX_ADDRESS 0x03
106 /* IDT clock synthesizers */
107 #define CONFIG_IDT8T49N222A
108 #define I2C_CH_IDT 0x9
110 #define IDT_SERDES1_ADDRESS 0x6E
111 #define IDT_SERDES2_ADDRESS 0x6C
113 /* Voltage monitor on channel 2*/
114 #define I2C_MUX_CH_VOL_MONITOR 0xa
115 #define I2C_VOL_MONITOR_ADDR 0x40
116 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
117 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
118 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
120 #define CONFIG_ZM7300
121 #define I2C_MUX_CH_DPM 0xa
122 #define I2C_DPM_ADDR 0x28
124 #define CONFIG_ENV_OVERWRITE
126 #ifdef CONFIG_SYS_NO_FLASH
127 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
128 #define CONFIG_ENV_IS_NOWHERE
131 #define CONFIG_FLASH_CFI_DRIVER
132 #define CONFIG_SYS_FLASH_CFI
133 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
136 #if defined(CONFIG_SPIFLASH)
137 #define CONFIG_SYS_EXTRA_ENV_RELOC
138 #define CONFIG_ENV_IS_IN_SPI_FLASH
139 #define CONFIG_ENV_SPI_BUS 0
140 #define CONFIG_ENV_SPI_CS 0
141 #define CONFIG_ENV_SPI_MAX_HZ 10000000
142 #define CONFIG_ENV_SPI_MODE 0
143 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
144 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
145 #define CONFIG_ENV_SECT_SIZE 0x10000
146 #elif defined(CONFIG_SDCARD)
147 #define CONFIG_SYS_EXTRA_ENV_RELOC
148 #define CONFIG_ENV_IS_IN_MMC
149 #define CONFIG_SYS_MMC_ENV_DEV 0
150 #define CONFIG_ENV_SIZE 0x2000
151 #define CONFIG_ENV_OFFSET (512 * 1097)
152 #elif defined(CONFIG_NAND)
153 #define CONFIG_SYS_EXTRA_ENV_RELOC
154 #define CONFIG_ENV_IS_IN_NAND
155 #define CONFIG_ENV_SIZE 0x2000
156 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
157 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
158 #define CONFIG_ENV_IS_IN_REMOTE
159 #define CONFIG_ENV_ADDR 0xffe20000
160 #define CONFIG_ENV_SIZE 0x2000
161 #elif defined(CONFIG_ENV_IS_NOWHERE)
162 #define CONFIG_ENV_SIZE 0x2000
164 #define CONFIG_ENV_IS_IN_FLASH
165 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
166 #define CONFIG_ENV_SIZE 0x2000
167 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
171 unsigned long get_board_sys_clk(void);
172 unsigned long get_board_ddr_clk(void);
174 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
175 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
178 * These can be toggled for performance analysis, otherwise use default.
180 #define CONFIG_SYS_CACHE_STASHING
181 #define CONFIG_BTB /* toggle branch predition */
182 #define CONFIG_DDR_ECC
183 #ifdef CONFIG_DDR_ECC
184 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
185 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
188 #define CONFIG_ENABLE_36BIT_PHYS
190 #ifdef CONFIG_PHYS_64BIT
191 #define CONFIG_ADDR_MAP
192 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
196 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
198 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
199 #define CONFIG_SYS_MEMTEST_END 0x00400000
200 #define CONFIG_SYS_ALT_MEMTEST
201 #define CONFIG_PANIC_HANG /* do not reset board on panic */
204 * Config the L3 Cache as L3 SRAM
206 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
207 #define CONFIG_SYS_L3_SIZE 256 << 10
208 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
210 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
212 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
213 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
214 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
215 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
217 #ifdef CONFIG_PHYS_64BIT
218 #define CONFIG_SYS_DCSRBAR 0xf0000000
219 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
223 #define CONFIG_ID_EEPROM
224 #define CONFIG_SYS_I2C_EEPROM_NXID
225 #define CONFIG_SYS_EEPROM_BUS_NUM 0
226 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
227 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
228 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
229 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
234 #define CONFIG_VERY_BIG_RAM
235 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
236 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
238 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
239 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
240 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
242 #define CONFIG_DDR_SPD
243 #define CONFIG_SYS_DDR_RAW_TIMING
244 #define CONFIG_SYS_FSL_DDR3
245 #ifndef CONFIG_SPL_BUILD
246 #define CONFIG_FSL_DDR_INTERACTIVE
249 #define CONFIG_SYS_SPD_BUS_NUM 0
250 #define SPD_EEPROM_ADDRESS1 0x51
251 #define SPD_EEPROM_ADDRESS2 0x53
253 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
254 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
259 #define CONFIG_SYS_FLASH_BASE 0xe0000000
260 #ifdef CONFIG_PHYS_64BIT
261 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
263 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
266 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
267 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
269 CSPR_PORT_SIZE_16 | \
272 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
273 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
274 CSPR_PORT_SIZE_16 | \
277 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
278 /* NOR Flash Timing Params */
279 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
280 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
281 FTIM0_NOR_TEADC(0x04) | \
282 FTIM0_NOR_TEAHC(0x20))
283 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
284 FTIM1_NOR_TRAD_NOR(0x1A) |\
285 FTIM1_NOR_TSEQRAD_NOR(0x13))
286 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
287 FTIM2_NOR_TCH(0x0E) | \
288 FTIM2_NOR_TWPH(0x0E) | \
290 #define CONFIG_SYS_NOR_FTIM3 0x0
292 #define CONFIG_SYS_FLASH_QUIET_TEST
293 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
295 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
296 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
297 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
298 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
300 #define CONFIG_SYS_FLASH_EMPTY_INFO
301 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
302 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
304 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
305 #define CONFIG_FSL_QIXIS_V2
306 #define QIXIS_BASE 0xffdf0000
307 #ifdef CONFIG_PHYS_64BIT
308 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
310 #define QIXIS_BASE_PHYS QIXIS_BASE
312 #define QIXIS_LBMAP_SWITCH 0x01
313 #define QIXIS_LBMAP_MASK 0x0f
314 #define QIXIS_LBMAP_SHIFT 0
315 #define QIXIS_LBMAP_DFLTBANK 0x00
316 #define QIXIS_LBMAP_ALTBANK 0x02
317 #define QIXIS_RST_CTL_RESET 0x31
318 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
319 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
320 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
322 #define CONFIG_SYS_CSPR3_EXT (0xf)
323 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
327 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024)
328 #define CONFIG_SYS_CSOR3 0x0
329 /* QIXIS Timing parameters for IFC CS3 */
330 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
331 FTIM0_GPCM_TEADC(0x0e) | \
332 FTIM0_GPCM_TEAHC(0x0e))
333 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
334 FTIM1_GPCM_TRAD(0x1f))
335 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
336 FTIM2_GPCM_TCH(0x8) | \
337 FTIM2_GPCM_TWP(0x1f))
338 #define CONFIG_SYS_CS3_FTIM3 0x0
340 /* NAND Flash on IFC */
341 #define CONFIG_NAND_FSL_IFC
342 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
343 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
344 #define CONFIG_SYS_NAND_BASE 0xff800000
345 #ifdef CONFIG_PHYS_64BIT
346 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
348 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
351 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
352 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
353 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
354 | CSPR_MSEL_NAND /* MSEL = NAND */ \
356 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
358 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
359 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
360 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
361 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
362 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
363 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
364 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
366 #define CONFIG_SYS_NAND_ONFI_DETECTION
368 /* ONFI NAND Flash mode0 Timing Params */
369 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
370 FTIM0_NAND_TWP(0x18) | \
371 FTIM0_NAND_TWCHT(0x07) | \
372 FTIM0_NAND_TWH(0x0a))
373 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
374 FTIM1_NAND_TWBE(0x39) | \
375 FTIM1_NAND_TRR(0x0e) | \
376 FTIM1_NAND_TRP(0x18))
377 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
378 FTIM2_NAND_TREH(0x0a) | \
379 FTIM2_NAND_TWHRE(0x1e))
380 #define CONFIG_SYS_NAND_FTIM3 0x0
382 #define CONFIG_SYS_NAND_DDR_LAW 11
384 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
385 #define CONFIG_SYS_MAX_NAND_DEVICE 1
386 #define CONFIG_CMD_NAND
388 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
390 #if defined(CONFIG_NAND)
391 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
392 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
393 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
394 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
395 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
396 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
397 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
398 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
399 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
400 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
401 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
402 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
403 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
404 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
405 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
406 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
408 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
409 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
410 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
411 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
412 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
413 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
414 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
415 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
416 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
417 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
418 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
419 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
420 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
421 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
422 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
423 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
425 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
426 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
427 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
428 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
429 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
430 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
431 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
432 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
434 #ifdef CONFIG_SPL_BUILD
435 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
437 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
440 #if defined(CONFIG_RAMBOOT_PBL)
441 #define CONFIG_SYS_RAMBOOT
444 #define CONFIG_BOARD_EARLY_INIT_R
445 #define CONFIG_MISC_INIT_R
447 #define CONFIG_HWCONFIG
449 /* define to use L1 as initial stack */
450 #define CONFIG_L1_INIT_RAM
451 #define CONFIG_SYS_INIT_RAM_LOCK
452 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
453 #ifdef CONFIG_PHYS_64BIT
454 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
455 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
456 /* The assembler doesn't like typecast */
457 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
458 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
459 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
461 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
462 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
463 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
465 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
467 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
468 GENERATED_GBL_DATA_SIZE)
469 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
471 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
472 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
474 /* Serial Port - controlled on board with jumper J8
478 #define CONFIG_CONS_INDEX 1
479 #define CONFIG_SYS_NS16550_SERIAL
480 #define CONFIG_SYS_NS16550_REG_SIZE 1
481 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
483 #define CONFIG_SYS_BAUDRATE_TABLE \
484 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
486 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
487 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
488 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
489 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
490 #ifndef CONFIG_SPL_BUILD
491 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
495 #define CONFIG_SYS_I2C
496 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
497 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
498 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
499 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
500 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
501 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
502 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
508 #define CONFIG_RTC_DS3231 1
509 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
514 #ifdef CONFIG_SYS_SRIO
516 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
517 #ifdef CONFIG_PHYS_64BIT
518 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
520 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
522 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
526 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
527 #ifdef CONFIG_PHYS_64BIT
528 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
530 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
532 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
537 * for slave u-boot IMAGE instored in master memory space,
538 * PHYS must be aligned based on the SIZE
540 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
541 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
542 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
543 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
545 * for slave UCODE and ENV instored in master memory space,
546 * PHYS must be aligned based on the SIZE
548 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
549 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
550 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
552 /* slave core release by master*/
553 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
554 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
557 * SRIO_PCIE_BOOT - SLAVE
559 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
560 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
561 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
562 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
566 * eSPI - Enhanced SPI
568 #define CONFIG_SF_DEFAULT_SPEED 10000000
569 #define CONFIG_SF_DEFAULT_MODE 0
574 #ifdef CONFIG_PHYS_64BIT
575 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull
577 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000
582 * Memory space is mapped 1-1, but I/O space must start from 0.
585 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
586 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
587 #ifdef CONFIG_PHYS_64BIT
588 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
589 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
591 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
592 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
594 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
595 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
596 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
597 #ifdef CONFIG_PHYS_64BIT
598 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
600 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
602 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
605 #ifndef CONFIG_NOBQFMAN
606 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
607 #define CONFIG_SYS_BMAN_NUM_PORTALS 25
608 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
609 #ifdef CONFIG_PHYS_64BIT
610 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
612 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
614 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
615 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
616 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
617 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
618 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
619 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
620 CONFIG_SYS_BMAN_CENA_SIZE)
621 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
622 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
623 #define CONFIG_SYS_QMAN_NUM_PORTALS 25
624 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
625 #ifdef CONFIG_PHYS_64BIT
626 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
628 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
630 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
631 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
632 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
633 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
634 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
635 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
636 CONFIG_SYS_QMAN_CENA_SIZE)
637 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
638 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
640 #define CONFIG_SYS_DPAA_FMAN
642 #define CONFIG_SYS_DPAA_RMAN
644 /* Default address of microcode for the Linux Fman driver */
645 #if defined(CONFIG_SPIFLASH)
647 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
648 * env, so we got 0x110000.
650 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
651 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
652 #elif defined(CONFIG_SDCARD)
654 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
655 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
656 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
658 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
659 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
660 #elif defined(CONFIG_NAND)
661 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
662 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
663 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
665 * Slave has no ucode locally, it can fetch this from remote. When implementing
666 * in two corenet boards, slave's ucode could be stored in master's memory
667 * space, the address can be mapped from slave TLB->slave LAW->
668 * slave SRIO or PCIE outbound window->master inbound window->
669 * master LAW->the ucode address in master's memory space.
671 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
672 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
674 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
675 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
677 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
678 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
679 #endif /* CONFIG_NOBQFMAN */
681 #ifdef CONFIG_SYS_DPAA_FMAN
682 #define CONFIG_FMAN_ENET
683 #define CONFIG_PHYLIB_10G
684 #define CONFIG_PHY_VITESSE
685 #define CONFIG_PHY_TERANETICS
686 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
687 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
688 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
689 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
693 #define CONFIG_PCI_INDIRECT_BRIDGE
694 #define CONFIG_PCI_PNP /* do pci plug-and-play */
696 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
697 #define CONFIG_DOS_PARTITION
698 #endif /* CONFIG_PCI */
700 #ifdef CONFIG_FMAN_ENET
701 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
702 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
704 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
705 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
706 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/
708 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
709 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
710 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
711 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
713 #define CONFIG_MII /* MII PHY management */
714 #define CONFIG_ETHPRIME "FM1@DTSEC1"
715 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
718 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
723 #define CONFIG_LOADS_ECHO /* echo on for serial download */
724 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
727 * Command line configuration.
729 #define CONFIG_CMD_DATE
730 #define CONFIG_CMD_EEPROM
731 #define CONFIG_CMD_ERRATA
732 #define CONFIG_CMD_IRQ
733 #define CONFIG_CMD_REGINFO
736 #define CONFIG_CMD_PCI
739 /* Hash command with SHA acceleration supported in hardware */
740 #ifdef CONFIG_FSL_CAAM
741 #define CONFIG_CMD_HASH
742 #define CONFIG_SHA_HW_ACCEL
748 #define CONFIG_HAS_FSL_DR_USB
750 #ifdef CONFIG_HAS_FSL_DR_USB
751 #define CONFIG_USB_EHCI
753 #ifdef CONFIG_USB_EHCI
754 #define CONFIG_USB_EHCI_FSL
755 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
760 * Miscellaneous configurable options
762 #define CONFIG_SYS_LONGHELP /* undef to save memory */
763 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
764 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
765 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
766 #ifdef CONFIG_CMD_KGDB
767 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
769 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
771 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
772 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
773 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
776 * For booting Linux, the board info and command line data
777 * have to be in the first 64 MB of memory, since this is
778 * the maximum mapped by the Linux kernel during initialization.
780 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
781 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
783 #ifdef CONFIG_CMD_KGDB
784 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
788 * Environment Configuration
790 #define CONFIG_ROOTPATH "/opt/nfsroot"
791 #define CONFIG_BOOTFILE "uImage"
792 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
794 /* default location for tftp and bootm */
795 #define CONFIG_LOADADDR 1000000
798 #define CONFIG_BAUDRATE 115200
800 #define __USB_PHY_TYPE ulpi
802 #ifdef CONFIG_PPC_B4860
803 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \
804 "bank_intlv=cs0_cs1;" \
807 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
810 #define CONFIG_EXTRA_ENV_SETTINGS \
812 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
814 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
815 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
816 "tftpflash=tftpboot $loadaddr $uboot && " \
817 "protect off $ubootaddr +$filesize && " \
818 "erase $ubootaddr +$filesize && " \
819 "cp.b $loadaddr $ubootaddr $filesize && " \
820 "protect on $ubootaddr +$filesize && " \
821 "cmp.b $loadaddr $ubootaddr $filesize\0" \
822 "consoledev=ttyS0\0" \
823 "ramdiskaddr=2000000\0" \
824 "ramdiskfile=b4860qds/ramdisk.uboot\0" \
825 "fdtaddr=1e00000\0" \
826 "fdtfile=b4860qds/b4860qds.dtb\0" \
829 /* For emulation this causes u-boot to jump to the start of the proof point
830 app code automatically */
831 #define CONFIG_PROOF_POINTS \
832 "setenv bootargs root=/dev/$bdev rw " \
833 "console=$consoledev,$baudrate $othbootargs;" \
834 "cpu 1 release 0x29000000 - - -;" \
835 "cpu 2 release 0x29000000 - - -;" \
836 "cpu 3 release 0x29000000 - - -;" \
837 "cpu 4 release 0x29000000 - - -;" \
838 "cpu 5 release 0x29000000 - - -;" \
839 "cpu 6 release 0x29000000 - - -;" \
840 "cpu 7 release 0x29000000 - - -;" \
843 #define CONFIG_HVBOOT \
844 "setenv bootargs config-addr=0x60000000; " \
845 "bootm 0x01000000 - 0x00f00000"
848 "setenv bootargs root=/dev/$bdev rw " \
849 "console=$consoledev,$baudrate $othbootargs;" \
850 "cpu 1 release 0x01000000 - - -;" \
851 "cpu 2 release 0x01000000 - - -;" \
852 "cpu 3 release 0x01000000 - - -;" \
853 "cpu 4 release 0x01000000 - - -;" \
854 "cpu 5 release 0x01000000 - - -;" \
855 "cpu 6 release 0x01000000 - - -;" \
856 "cpu 7 release 0x01000000 - - -;" \
859 #define CONFIG_LINUX \
860 "setenv bootargs root=/dev/ram rw " \
861 "console=$consoledev,$baudrate $othbootargs;" \
862 "setenv ramdiskaddr 0x02000000;" \
863 "setenv fdtaddr 0x01e00000;" \
864 "setenv loadaddr 0x1000000;" \
865 "bootm $loadaddr $ramdiskaddr $fdtaddr"
867 #define CONFIG_HDBOOT \
868 "setenv bootargs root=/dev/$bdev rw " \
869 "console=$consoledev,$baudrate $othbootargs;" \
870 "tftp $loadaddr $bootfile;" \
871 "tftp $fdtaddr $fdtfile;" \
872 "bootm $loadaddr - $fdtaddr"
874 #define CONFIG_NFSBOOTCOMMAND \
875 "setenv bootargs root=/dev/nfs rw " \
876 "nfsroot=$serverip:$rootpath " \
877 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
878 "console=$consoledev,$baudrate $othbootargs;" \
879 "tftp $loadaddr $bootfile;" \
880 "tftp $fdtaddr $fdtfile;" \
881 "bootm $loadaddr - $fdtaddr"
883 #define CONFIG_RAMBOOTCOMMAND \
884 "setenv bootargs root=/dev/ram rw " \
885 "console=$consoledev,$baudrate $othbootargs;" \
886 "tftp $ramdiskaddr $ramdiskfile;" \
887 "tftp $loadaddr $bootfile;" \
888 "tftp $fdtaddr $fdtfile;" \
889 "bootm $loadaddr $ramdiskaddr $fdtaddr"
891 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
893 #include <asm/fsl_secure_boot.h>
895 #endif /* __CONFIG_H */