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[u-boot] / include / configs / B4860QDS.h
1 /*
2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9
10 #define CONFIG_DISPLAY_BOARDINFO
11
12 /*
13  * B4860 QDS board configuration file
14  */
15 #define CONFIG_B4860QDS
16
17 #ifdef CONFIG_RAMBOOT_PBL
18 #define CONFIG_SYS_FSL_PBL_PBI  $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
19 #define CONFIG_SYS_FSL_PBL_RCW  $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
20 #ifndef CONFIG_NAND
21 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
22 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
23 #else
24 #define CONFIG_SPL_FLUSH_IMAGE
25 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
26 #define CONFIG_FSL_LAW                 /* Use common FSL init code */
27 #define CONFIG_SYS_TEXT_BASE            0x00201000
28 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
29 #define CONFIG_SPL_PAD_TO               0x40000
30 #define CONFIG_SPL_MAX_SIZE             0x28000
31 #define RESET_VECTOR_OFFSET             0x27FFC
32 #define BOOT_PAGE_OFFSET                0x27000
33 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
34 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
35 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
36 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
37 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
38 #define CONFIG_SPL_NAND_BOOT
39 #ifdef CONFIG_SPL_BUILD
40 #define CONFIG_SPL_SKIP_RELOCATE
41 #define CONFIG_SPL_COMMON_INIT_DDR
42 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
43 #define CONFIG_SYS_NO_FLASH
44 #endif
45 #endif
46 #endif
47
48 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
49 /* Set 1M boot space */
50 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
51 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
52                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
53 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
54 #define CONFIG_SYS_NO_FLASH
55 #endif
56
57 /* High Level Configuration Options */
58 #define CONFIG_BOOKE
59 #define CONFIG_E500                     /* BOOKE e500 family */
60 #define CONFIG_E500MC                   /* BOOKE e500mc family */
61 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
62 #define CONFIG_MP                       /* support multiple processors */
63
64 #ifndef CONFIG_SYS_TEXT_BASE
65 #define CONFIG_SYS_TEXT_BASE    0xeff40000
66 #endif
67
68 #ifndef CONFIG_RESET_VECTOR_ADDRESS
69 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
70 #endif
71
72 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
73 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
74 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
75 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
76 #define CONFIG_PCI                      /* Enable PCI/PCIE */
77 #define CONFIG_PCIE1                    /* PCIE controller 1 */
78 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
79 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
80
81 #ifndef CONFIG_PPC_B4420
82 #define CONFIG_SYS_SRIO
83 #define CONFIG_SRIO1                    /* SRIO port 1 */
84 #define CONFIG_SRIO2                    /* SRIO port 2 */
85 #define CONFIG_SRIO_PCIE_BOOT_MASTER
86 #endif
87
88 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
89
90 /* I2C bus multiplexer */
91 #define I2C_MUX_PCA_ADDR                0x77
92
93 /* VSC Crossbar switches */
94 #define CONFIG_VSC_CROSSBAR
95 #define I2C_CH_DEFAULT                  0x8
96 #define I2C_CH_VSC3316                  0xc
97 #define I2C_CH_VSC3308                  0xd
98
99 #define VSC3316_TX_ADDRESS              0x70
100 #define VSC3316_RX_ADDRESS              0x71
101 #define VSC3308_TX_ADDRESS              0x02
102 #define VSC3308_RX_ADDRESS              0x03
103
104 /* IDT clock synthesizers */
105 #define CONFIG_IDT8T49N222A
106 #define I2C_CH_IDT                     0x9
107
108 #define IDT_SERDES1_ADDRESS            0x6E
109 #define IDT_SERDES2_ADDRESS            0x6C
110
111 /* Voltage monitor on channel 2*/
112 #define I2C_MUX_CH_VOL_MONITOR          0xa
113 #define I2C_VOL_MONITOR_ADDR            0x40
114 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
115 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
116 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
117
118 #define CONFIG_ZM7300
119 #define I2C_MUX_CH_DPM                  0xa
120 #define I2C_DPM_ADDR                    0x28
121
122 #define CONFIG_ENV_OVERWRITE
123
124 #ifdef CONFIG_SYS_NO_FLASH
125 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
126 #define CONFIG_ENV_IS_NOWHERE
127 #endif
128 #else
129 #define CONFIG_FLASH_CFI_DRIVER
130 #define CONFIG_SYS_FLASH_CFI
131 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
132 #endif
133
134 #if defined(CONFIG_SPIFLASH)
135 #define CONFIG_SYS_EXTRA_ENV_RELOC
136 #define CONFIG_ENV_IS_IN_SPI_FLASH
137 #define CONFIG_ENV_SPI_BUS              0
138 #define CONFIG_ENV_SPI_CS               0
139 #define CONFIG_ENV_SPI_MAX_HZ           10000000
140 #define CONFIG_ENV_SPI_MODE             0
141 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
142 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
143 #define CONFIG_ENV_SECT_SIZE            0x10000
144 #elif defined(CONFIG_SDCARD)
145 #define CONFIG_SYS_EXTRA_ENV_RELOC
146 #define CONFIG_ENV_IS_IN_MMC
147 #define CONFIG_SYS_MMC_ENV_DEV          0
148 #define CONFIG_ENV_SIZE                 0x2000
149 #define CONFIG_ENV_OFFSET               (512 * 1097)
150 #elif defined(CONFIG_NAND)
151 #define CONFIG_SYS_EXTRA_ENV_RELOC
152 #define CONFIG_ENV_IS_IN_NAND
153 #define CONFIG_ENV_SIZE                 0x2000
154 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
155 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
156 #define CONFIG_ENV_IS_IN_REMOTE
157 #define CONFIG_ENV_ADDR         0xffe20000
158 #define CONFIG_ENV_SIZE         0x2000
159 #elif defined(CONFIG_ENV_IS_NOWHERE)
160 #define CONFIG_ENV_SIZE         0x2000
161 #else
162 #define CONFIG_ENV_IS_IN_FLASH
163 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
164 #define CONFIG_ENV_SIZE         0x2000
165 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
166 #endif
167
168 #ifndef __ASSEMBLY__
169 unsigned long get_board_sys_clk(void);
170 unsigned long get_board_ddr_clk(void);
171 #endif
172 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
173 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
174
175 /*
176  * These can be toggled for performance analysis, otherwise use default.
177  */
178 #define CONFIG_SYS_CACHE_STASHING
179 #define CONFIG_BTB                      /* toggle branch predition */
180 #define CONFIG_DDR_ECC
181 #ifdef CONFIG_DDR_ECC
182 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
183 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
184 #endif
185
186 #define CONFIG_ENABLE_36BIT_PHYS
187
188 #ifdef CONFIG_PHYS_64BIT
189 #define CONFIG_ADDR_MAP
190 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
191 #endif
192
193 #if 0
194 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
195 #endif
196 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
197 #define CONFIG_SYS_MEMTEST_END          0x00400000
198 #define CONFIG_SYS_ALT_MEMTEST
199 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
200
201 /*
202  *  Config the L3 Cache as L3 SRAM
203  */
204 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
205 #define CONFIG_SYS_L3_SIZE              256 << 10
206 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
207 #ifdef CONFIG_NAND
208 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
209 #endif
210 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
211 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
212 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
213 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
214
215 #ifdef CONFIG_PHYS_64BIT
216 #define CONFIG_SYS_DCSRBAR              0xf0000000
217 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
218 #endif
219
220 /* EEPROM */
221 #define CONFIG_ID_EEPROM
222 #define CONFIG_SYS_I2C_EEPROM_NXID
223 #define CONFIG_SYS_EEPROM_BUS_NUM       0
224 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
225 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
226 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
227 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
228
229 /*
230  * DDR Setup
231  */
232 #define CONFIG_VERY_BIG_RAM
233 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
234 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
235
236 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
237 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
238 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
239
240 #define CONFIG_DDR_SPD
241 #define CONFIG_SYS_DDR_RAW_TIMING
242 #define CONFIG_SYS_FSL_DDR3
243 #ifndef CONFIG_SPL_BUILD
244 #define CONFIG_FSL_DDR_INTERACTIVE
245 #endif
246
247 #define CONFIG_SYS_SPD_BUS_NUM  0
248 #define SPD_EEPROM_ADDRESS1     0x51
249 #define SPD_EEPROM_ADDRESS2     0x53
250
251 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
252 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
253
254 /*
255  * IFC Definitions
256  */
257 #define CONFIG_SYS_FLASH_BASE   0xe0000000
258 #ifdef CONFIG_PHYS_64BIT
259 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
260 #else
261 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
262 #endif
263
264 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
265 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
266                                 + 0x8000000) | \
267                                 CSPR_PORT_SIZE_16 | \
268                                 CSPR_MSEL_NOR | \
269                                 CSPR_V)
270 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
271 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
272                                 CSPR_PORT_SIZE_16 | \
273                                 CSPR_MSEL_NOR | \
274                                 CSPR_V)
275 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128 * 1024 * 1024)
276 /* NOR Flash Timing Params */
277 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(4)
278 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x01) | \
279                                 FTIM0_NOR_TEADC(0x04) | \
280                                 FTIM0_NOR_TEAHC(0x20))
281 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
282                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
283                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
284 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x01) | \
285                                 FTIM2_NOR_TCH(0x0E) | \
286                                 FTIM2_NOR_TWPH(0x0E) | \
287                                 FTIM2_NOR_TWP(0x1c))
288 #define CONFIG_SYS_NOR_FTIM3    0x0
289
290 #define CONFIG_SYS_FLASH_QUIET_TEST
291 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
292
293 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
294 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
295 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
296 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
297
298 #define CONFIG_SYS_FLASH_EMPTY_INFO
299 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
300                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
301
302 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
303 #define CONFIG_FSL_QIXIS_V2
304 #define QIXIS_BASE              0xffdf0000
305 #ifdef CONFIG_PHYS_64BIT
306 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
307 #else
308 #define QIXIS_BASE_PHYS         QIXIS_BASE
309 #endif
310 #define QIXIS_LBMAP_SWITCH              0x01
311 #define QIXIS_LBMAP_MASK                0x0f
312 #define QIXIS_LBMAP_SHIFT               0
313 #define QIXIS_LBMAP_DFLTBANK            0x00
314 #define QIXIS_LBMAP_ALTBANK             0x02
315 #define QIXIS_RST_CTL_RESET             0x31
316 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
317 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
318 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
319
320 #define CONFIG_SYS_CSPR3_EXT    (0xf)
321 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
322                                 | CSPR_PORT_SIZE_8 \
323                                 | CSPR_MSEL_GPCM \
324                                 | CSPR_V)
325 #define CONFIG_SYS_AMASK3       IFC_AMASK(4 * 1024)
326 #define CONFIG_SYS_CSOR3        0x0
327 /* QIXIS Timing parameters for IFC CS3 */
328 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
329                                         FTIM0_GPCM_TEADC(0x0e) | \
330                                         FTIM0_GPCM_TEAHC(0x0e))
331 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
332                                         FTIM1_GPCM_TRAD(0x1f))
333 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
334                                         FTIM2_GPCM_TCH(0x8) | \
335                                         FTIM2_GPCM_TWP(0x1f))
336 #define CONFIG_SYS_CS3_FTIM3            0x0
337
338 /* NAND Flash on IFC */
339 #define CONFIG_NAND_FSL_IFC
340 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
341 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
342 #define CONFIG_SYS_NAND_BASE            0xff800000
343 #ifdef CONFIG_PHYS_64BIT
344 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
345 #else
346 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
347 #endif
348
349 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
350 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
351                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
352                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
353                                 | CSPR_V)
354 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
355
356 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
357                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
358                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
359                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
360                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
361                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
362                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
363
364 #define CONFIG_SYS_NAND_ONFI_DETECTION
365
366 /* ONFI NAND Flash mode0 Timing Params */
367 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
368                                         FTIM0_NAND_TWP(0x18)   | \
369                                         FTIM0_NAND_TWCHT(0x07) | \
370                                         FTIM0_NAND_TWH(0x0a))
371 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
372                                         FTIM1_NAND_TWBE(0x39)  | \
373                                         FTIM1_NAND_TRR(0x0e)   | \
374                                         FTIM1_NAND_TRP(0x18))
375 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
376                                         FTIM2_NAND_TREH(0x0a) | \
377                                         FTIM2_NAND_TWHRE(0x1e))
378 #define CONFIG_SYS_NAND_FTIM3           0x0
379
380 #define CONFIG_SYS_NAND_DDR_LAW         11
381
382 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
383 #define CONFIG_SYS_MAX_NAND_DEVICE      1
384 #define CONFIG_CMD_NAND
385
386 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
387
388 #if defined(CONFIG_NAND)
389 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
390 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
391 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
392 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
393 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
394 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
395 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
396 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
397 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
398 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
399 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
400 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
401 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
402 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
403 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
404 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
405 #else
406 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
407 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
408 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
409 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
410 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
411 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
412 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
413 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
414 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
415 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
416 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
417 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
418 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
419 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
420 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
421 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
422 #endif
423 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
424 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
425 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
426 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
427 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
428 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
429 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
430 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
431
432 #ifdef CONFIG_SPL_BUILD
433 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
434 #else
435 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
436 #endif
437
438 #if defined(CONFIG_RAMBOOT_PBL)
439 #define CONFIG_SYS_RAMBOOT
440 #endif
441
442 #define CONFIG_BOARD_EARLY_INIT_R
443 #define CONFIG_MISC_INIT_R
444
445 #define CONFIG_HWCONFIG
446
447 /* define to use L1 as initial stack */
448 #define CONFIG_L1_INIT_RAM
449 #define CONFIG_SYS_INIT_RAM_LOCK
450 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
451 #ifdef CONFIG_PHYS_64BIT
452 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
453 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
454 /* The assembler doesn't like typecast */
455 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
456         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
457           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
458 #else
459 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
460 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
461 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
462 #endif
463 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
464
465 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
466                                         GENERATED_GBL_DATA_SIZE)
467 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
468
469 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
470 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
471
472 /* Serial Port - controlled on board with jumper J8
473  * open - index 2
474  * shorted - index 1
475  */
476 #define CONFIG_CONS_INDEX       1
477 #define CONFIG_SYS_NS16550_SERIAL
478 #define CONFIG_SYS_NS16550_REG_SIZE     1
479 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
480
481 #define CONFIG_SYS_BAUDRATE_TABLE       \
482         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
483
484 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
485 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
486 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
487 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
488 #ifndef CONFIG_SPL_BUILD
489 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
490 #endif
491
492 /* I2C */
493 #define CONFIG_SYS_I2C
494 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
495 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
496 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
497 #define CONFIG_SYS_FSL_I2C2_SPEED       400000  /* I2C speed in Hz */
498 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
499 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
500 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x119000
501
502 /*
503  * RTC configuration
504  */
505 #define RTC
506 #define CONFIG_RTC_DS3231               1
507 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
508
509 /*
510  * RapidIO
511  */
512 #ifdef CONFIG_SYS_SRIO
513 #ifdef CONFIG_SRIO1
514 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
515 #ifdef CONFIG_PHYS_64BIT
516 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
517 #else
518 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
519 #endif
520 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
521 #endif
522
523 #ifdef CONFIG_SRIO2
524 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
525 #ifdef CONFIG_PHYS_64BIT
526 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
527 #else
528 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
529 #endif
530 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
531 #endif
532 #endif
533
534 /*
535  * for slave u-boot IMAGE instored in master memory space,
536  * PHYS must be aligned based on the SIZE
537  */
538 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
539 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
540 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
541 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
542 /*
543  * for slave UCODE and ENV instored in master memory space,
544  * PHYS must be aligned based on the SIZE
545  */
546 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
547 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
548 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
549
550 /* slave core release by master*/
551 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
552 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
553
554 /*
555  * SRIO_PCIE_BOOT - SLAVE
556  */
557 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
558 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
559 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
560                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
561 #endif
562
563 /*
564  * eSPI - Enhanced SPI
565  */
566 #define CONFIG_SF_DEFAULT_SPEED         10000000
567 #define CONFIG_SF_DEFAULT_MODE          0
568
569 /*
570  * MAPLE
571  */
572 #ifdef CONFIG_PHYS_64BIT
573 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xFA0000000ull
574 #else
575 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xA0000000
576 #endif
577
578 /*
579  * General PCI
580  * Memory space is mapped 1-1, but I/O space must start from 0.
581  */
582
583 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
584 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
585 #ifdef CONFIG_PHYS_64BIT
586 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
587 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
588 #else
589 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
590 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
591 #endif
592 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
593 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
594 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
595 #ifdef CONFIG_PHYS_64BIT
596 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
597 #else
598 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
599 #endif
600 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
601
602 /* Qman/Bman */
603 #ifndef CONFIG_NOBQFMAN
604 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
605 #define CONFIG_SYS_BMAN_NUM_PORTALS     25
606 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
607 #ifdef CONFIG_PHYS_64BIT
608 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
609 #else
610 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
611 #endif
612 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
613 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
614 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
615 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
616 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
617 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
618                                         CONFIG_SYS_BMAN_CENA_SIZE)
619 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
620 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
621 #define CONFIG_SYS_QMAN_NUM_PORTALS     25
622 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
623 #ifdef CONFIG_PHYS_64BIT
624 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
625 #else
626 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
627 #endif
628 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
629 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
630 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
631 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
632 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
633 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
634                                         CONFIG_SYS_QMAN_CENA_SIZE)
635 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
636 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
637
638 #define CONFIG_SYS_DPAA_FMAN
639
640 #define CONFIG_SYS_DPAA_RMAN
641
642 /* Default address of microcode for the Linux Fman driver */
643 #if defined(CONFIG_SPIFLASH)
644 /*
645  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
646  * env, so we got 0x110000.
647  */
648 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
649 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
650 #elif defined(CONFIG_SDCARD)
651 /*
652  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
653  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
654  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
655  */
656 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
657 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
658 #elif defined(CONFIG_NAND)
659 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
660 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
661 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
662 /*
663  * Slave has no ucode locally, it can fetch this from remote. When implementing
664  * in two corenet boards, slave's ucode could be stored in master's memory
665  * space, the address can be mapped from slave TLB->slave LAW->
666  * slave SRIO or PCIE outbound window->master inbound window->
667  * master LAW->the ucode address in master's memory space.
668  */
669 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
670 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
671 #else
672 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
673 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
674 #endif
675 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
676 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
677 #endif /* CONFIG_NOBQFMAN */
678
679 #ifdef CONFIG_SYS_DPAA_FMAN
680 #define CONFIG_FMAN_ENET
681 #define CONFIG_PHYLIB_10G
682 #define CONFIG_PHY_VITESSE
683 #define CONFIG_PHY_TERANETICS
684 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
685 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
686 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
687 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
688 #endif
689
690 #ifdef CONFIG_PCI
691 #define CONFIG_PCI_INDIRECT_BRIDGE
692 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
693
694 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
695 #define CONFIG_DOS_PARTITION
696 #endif  /* CONFIG_PCI */
697
698 #ifdef CONFIG_FMAN_ENET
699 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
700 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
701
702 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
703 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7       /*SLOT 1*/
704 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6       /*SLOT 2*/
705
706 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
707 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
708 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
709 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
710
711 #define CONFIG_MII              /* MII PHY management */
712 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
713 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
714 #endif
715
716 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
717
718 /*
719  * Environment
720  */
721 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
722 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
723
724 /*
725  * Command line configuration.
726  */
727 #define CONFIG_CMD_DATE
728 #define CONFIG_CMD_EEPROM
729 #define CONFIG_CMD_ERRATA
730 #define CONFIG_CMD_IRQ
731 #define CONFIG_CMD_REGINFO
732
733 #ifdef CONFIG_PCI
734 #define CONFIG_CMD_PCI
735 #endif
736
737 /* Hash command with SHA acceleration supported in hardware */
738 #ifdef CONFIG_FSL_CAAM
739 #define CONFIG_CMD_HASH
740 #define CONFIG_SHA_HW_ACCEL
741 #endif
742
743 /*
744 * USB
745 */
746 #define CONFIG_HAS_FSL_DR_USB
747
748 #ifdef CONFIG_HAS_FSL_DR_USB
749 #define CONFIG_USB_EHCI
750
751 #ifdef CONFIG_USB_EHCI
752 #define CONFIG_USB_EHCI_FSL
753 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
754 #endif
755 #endif
756
757 /*
758  * Miscellaneous configurable options
759  */
760 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
761 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
762 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
763 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
764 #ifdef CONFIG_CMD_KGDB
765 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
766 #else
767 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
768 #endif
769 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
770 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
771 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
772
773 /*
774  * For booting Linux, the board info and command line data
775  * have to be in the first 64 MB of memory, since this is
776  * the maximum mapped by the Linux kernel during initialization.
777  */
778 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
779 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
780
781 #ifdef CONFIG_CMD_KGDB
782 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
783 #endif
784
785 /*
786  * Environment Configuration
787  */
788 #define CONFIG_ROOTPATH         "/opt/nfsroot"
789 #define CONFIG_BOOTFILE         "uImage"
790 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
791
792 /* default location for tftp and bootm */
793 #define CONFIG_LOADADDR         1000000
794
795
796 #define CONFIG_BAUDRATE 115200
797
798 #define __USB_PHY_TYPE  ulpi
799
800 #ifdef CONFIG_PPC_B4860
801 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,"     \
802                         "bank_intlv=cs0_cs1;"   \
803                         "en_cpc:cpc2;"
804 #else
805 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
806 #endif
807
808 #define CONFIG_EXTRA_ENV_SETTINGS                               \
809         HWCONFIG                                                \
810         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
811         "netdev=eth0\0"                                         \
812         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
813         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"                     \
814         "tftpflash=tftpboot $loadaddr $uboot && "               \
815         "protect off $ubootaddr +$filesize && "                 \
816         "erase $ubootaddr +$filesize && "                       \
817         "cp.b $loadaddr $ubootaddr $filesize && "               \
818         "protect on $ubootaddr +$filesize && "                  \
819         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
820         "consoledev=ttyS0\0"                                    \
821         "ramdiskaddr=2000000\0"                                 \
822         "ramdiskfile=b4860qds/ramdisk.uboot\0"                  \
823         "fdtaddr=1e00000\0"                                     \
824         "fdtfile=b4860qds/b4860qds.dtb\0"                               \
825         "bdev=sda3\0"
826
827 /* For emulation this causes u-boot to jump to the start of the proof point
828    app code automatically */
829 #define CONFIG_PROOF_POINTS                     \
830  "setenv bootargs root=/dev/$bdev rw "          \
831  "console=$consoledev,$baudrate $othbootargs;"  \
832  "cpu 1 release 0x29000000 - - -;"              \
833  "cpu 2 release 0x29000000 - - -;"              \
834  "cpu 3 release 0x29000000 - - -;"              \
835  "cpu 4 release 0x29000000 - - -;"              \
836  "cpu 5 release 0x29000000 - - -;"              \
837  "cpu 6 release 0x29000000 - - -;"              \
838  "cpu 7 release 0x29000000 - - -;"              \
839  "go 0x29000000"
840
841 #define CONFIG_HVBOOT   \
842  "setenv bootargs config-addr=0x60000000; "     \
843  "bootm 0x01000000 - 0x00f00000"
844
845 #define CONFIG_ALU                              \
846  "setenv bootargs root=/dev/$bdev rw "          \
847  "console=$consoledev,$baudrate $othbootargs;"  \
848  "cpu 1 release 0x01000000 - - -;"              \
849  "cpu 2 release 0x01000000 - - -;"              \
850  "cpu 3 release 0x01000000 - - -;"              \
851  "cpu 4 release 0x01000000 - - -;"              \
852  "cpu 5 release 0x01000000 - - -;"              \
853  "cpu 6 release 0x01000000 - - -;"              \
854  "cpu 7 release 0x01000000 - - -;"              \
855  "go 0x01000000"
856
857 #define CONFIG_LINUX                            \
858  "setenv bootargs root=/dev/ram rw "            \
859  "console=$consoledev,$baudrate $othbootargs;"  \
860  "setenv ramdiskaddr 0x02000000;"               \
861  "setenv fdtaddr 0x01e00000;"                   \
862  "setenv loadaddr 0x1000000;"                   \
863  "bootm $loadaddr $ramdiskaddr $fdtaddr"
864
865 #define CONFIG_HDBOOT                                   \
866         "setenv bootargs root=/dev/$bdev rw "           \
867         "console=$consoledev,$baudrate $othbootargs;"   \
868         "tftp $loadaddr $bootfile;"                     \
869         "tftp $fdtaddr $fdtfile;"                       \
870         "bootm $loadaddr - $fdtaddr"
871
872 #define CONFIG_NFSBOOTCOMMAND                   \
873         "setenv bootargs root=/dev/nfs rw "     \
874         "nfsroot=$serverip:$rootpath "          \
875         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
876         "console=$consoledev,$baudrate $othbootargs;"   \
877         "tftp $loadaddr $bootfile;"             \
878         "tftp $fdtaddr $fdtfile;"               \
879         "bootm $loadaddr - $fdtaddr"
880
881 #define CONFIG_RAMBOOTCOMMAND                           \
882         "setenv bootargs root=/dev/ram rw "             \
883         "console=$consoledev,$baudrate $othbootargs;"   \
884         "tftp $ramdiskaddr $ramdiskfile;"               \
885         "tftp $loadaddr $bootfile;"                     \
886         "tftp $fdtaddr $fdtfile;"                       \
887         "bootm $loadaddr $ramdiskaddr $fdtaddr"
888
889 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
890
891 #include <asm/fsl_secure_boot.h>
892
893 #endif  /* __CONFIG_H */