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Convert CONFIG_SPL_LIBGENERIC_SUPPORT to Kconfig
[u-boot] / include / configs / B4860QDS.h
1 /*
2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9
10 #define CONFIG_DISPLAY_BOARDINFO
11
12 /*
13  * B4860 QDS board configuration file
14  */
15 #define CONFIG_B4860QDS
16
17 #ifdef CONFIG_RAMBOOT_PBL
18 #define CONFIG_SYS_FSL_PBL_PBI  $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
19 #define CONFIG_SYS_FSL_PBL_RCW  $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
20 #ifndef CONFIG_NAND
21 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
22 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
23 #else
24 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
25 #define CONFIG_SPL_SERIAL_SUPPORT
26 #define CONFIG_SPL_FLUSH_IMAGE
27 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
28 #define CONFIG_FSL_LAW                 /* Use common FSL init code */
29 #define CONFIG_SYS_TEXT_BASE            0x00201000
30 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
31 #define CONFIG_SPL_PAD_TO               0x40000
32 #define CONFIG_SPL_MAX_SIZE             0x28000
33 #define RESET_VECTOR_OFFSET             0x27FFC
34 #define BOOT_PAGE_OFFSET                0x27000
35 #define CONFIG_SPL_NAND_SUPPORT
36 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
37 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
38 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
39 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
40 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
41 #define CONFIG_SPL_NAND_BOOT
42 #ifdef CONFIG_SPL_BUILD
43 #define CONFIG_SPL_SKIP_RELOCATE
44 #define CONFIG_SPL_COMMON_INIT_DDR
45 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
46 #define CONFIG_SYS_NO_FLASH
47 #endif
48 #endif
49 #endif
50
51 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
52 /* Set 1M boot space */
53 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
54 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
55                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
56 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
57 #define CONFIG_SYS_NO_FLASH
58 #endif
59
60 /* High Level Configuration Options */
61 #define CONFIG_BOOKE
62 #define CONFIG_E500                     /* BOOKE e500 family */
63 #define CONFIG_E500MC                   /* BOOKE e500mc family */
64 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
65 #define CONFIG_MP                       /* support multiple processors */
66
67 #ifndef CONFIG_SYS_TEXT_BASE
68 #define CONFIG_SYS_TEXT_BASE    0xeff40000
69 #endif
70
71 #ifndef CONFIG_RESET_VECTOR_ADDRESS
72 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
73 #endif
74
75 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
76 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
77 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
78 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
79 #define CONFIG_PCI                      /* Enable PCI/PCIE */
80 #define CONFIG_PCIE1                    /* PCIE controller 1 */
81 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
82 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
83
84 #ifndef CONFIG_PPC_B4420
85 #define CONFIG_SYS_SRIO
86 #define CONFIG_SRIO1                    /* SRIO port 1 */
87 #define CONFIG_SRIO2                    /* SRIO port 2 */
88 #define CONFIG_SRIO_PCIE_BOOT_MASTER
89 #endif
90
91 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
92
93 /* I2C bus multiplexer */
94 #define I2C_MUX_PCA_ADDR                0x77
95
96 /* VSC Crossbar switches */
97 #define CONFIG_VSC_CROSSBAR
98 #define I2C_CH_DEFAULT                  0x8
99 #define I2C_CH_VSC3316                  0xc
100 #define I2C_CH_VSC3308                  0xd
101
102 #define VSC3316_TX_ADDRESS              0x70
103 #define VSC3316_RX_ADDRESS              0x71
104 #define VSC3308_TX_ADDRESS              0x02
105 #define VSC3308_RX_ADDRESS              0x03
106
107 /* IDT clock synthesizers */
108 #define CONFIG_IDT8T49N222A
109 #define I2C_CH_IDT                     0x9
110
111 #define IDT_SERDES1_ADDRESS            0x6E
112 #define IDT_SERDES2_ADDRESS            0x6C
113
114 /* Voltage monitor on channel 2*/
115 #define I2C_MUX_CH_VOL_MONITOR          0xa
116 #define I2C_VOL_MONITOR_ADDR            0x40
117 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
118 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
119 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
120
121 #define CONFIG_ZM7300
122 #define I2C_MUX_CH_DPM                  0xa
123 #define I2C_DPM_ADDR                    0x28
124
125 #define CONFIG_ENV_OVERWRITE
126
127 #ifdef CONFIG_SYS_NO_FLASH
128 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
129 #define CONFIG_ENV_IS_NOWHERE
130 #endif
131 #else
132 #define CONFIG_FLASH_CFI_DRIVER
133 #define CONFIG_SYS_FLASH_CFI
134 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
135 #endif
136
137 #if defined(CONFIG_SPIFLASH)
138 #define CONFIG_SYS_EXTRA_ENV_RELOC
139 #define CONFIG_ENV_IS_IN_SPI_FLASH
140 #define CONFIG_ENV_SPI_BUS              0
141 #define CONFIG_ENV_SPI_CS               0
142 #define CONFIG_ENV_SPI_MAX_HZ           10000000
143 #define CONFIG_ENV_SPI_MODE             0
144 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
145 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
146 #define CONFIG_ENV_SECT_SIZE            0x10000
147 #elif defined(CONFIG_SDCARD)
148 #define CONFIG_SYS_EXTRA_ENV_RELOC
149 #define CONFIG_ENV_IS_IN_MMC
150 #define CONFIG_SYS_MMC_ENV_DEV          0
151 #define CONFIG_ENV_SIZE                 0x2000
152 #define CONFIG_ENV_OFFSET               (512 * 1097)
153 #elif defined(CONFIG_NAND)
154 #define CONFIG_SYS_EXTRA_ENV_RELOC
155 #define CONFIG_ENV_IS_IN_NAND
156 #define CONFIG_ENV_SIZE                 0x2000
157 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
158 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
159 #define CONFIG_ENV_IS_IN_REMOTE
160 #define CONFIG_ENV_ADDR         0xffe20000
161 #define CONFIG_ENV_SIZE         0x2000
162 #elif defined(CONFIG_ENV_IS_NOWHERE)
163 #define CONFIG_ENV_SIZE         0x2000
164 #else
165 #define CONFIG_ENV_IS_IN_FLASH
166 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
167 #define CONFIG_ENV_SIZE         0x2000
168 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
169 #endif
170
171 #ifndef __ASSEMBLY__
172 unsigned long get_board_sys_clk(void);
173 unsigned long get_board_ddr_clk(void);
174 #endif
175 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
176 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
177
178 /*
179  * These can be toggled for performance analysis, otherwise use default.
180  */
181 #define CONFIG_SYS_CACHE_STASHING
182 #define CONFIG_BTB                      /* toggle branch predition */
183 #define CONFIG_DDR_ECC
184 #ifdef CONFIG_DDR_ECC
185 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
186 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
187 #endif
188
189 #define CONFIG_ENABLE_36BIT_PHYS
190
191 #ifdef CONFIG_PHYS_64BIT
192 #define CONFIG_ADDR_MAP
193 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
194 #endif
195
196 #if 0
197 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
198 #endif
199 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
200 #define CONFIG_SYS_MEMTEST_END          0x00400000
201 #define CONFIG_SYS_ALT_MEMTEST
202 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
203
204 /*
205  *  Config the L3 Cache as L3 SRAM
206  */
207 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
208 #define CONFIG_SYS_L3_SIZE              256 << 10
209 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
210 #ifdef CONFIG_NAND
211 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
212 #endif
213 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
214 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
215 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
216 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
217
218 #ifdef CONFIG_PHYS_64BIT
219 #define CONFIG_SYS_DCSRBAR              0xf0000000
220 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
221 #endif
222
223 /* EEPROM */
224 #define CONFIG_ID_EEPROM
225 #define CONFIG_SYS_I2C_EEPROM_NXID
226 #define CONFIG_SYS_EEPROM_BUS_NUM       0
227 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
228 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
229 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
230 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
231
232 /*
233  * DDR Setup
234  */
235 #define CONFIG_VERY_BIG_RAM
236 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
237 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
238
239 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
240 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
241 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
242
243 #define CONFIG_DDR_SPD
244 #define CONFIG_SYS_DDR_RAW_TIMING
245 #define CONFIG_SYS_FSL_DDR3
246 #ifndef CONFIG_SPL_BUILD
247 #define CONFIG_FSL_DDR_INTERACTIVE
248 #endif
249
250 #define CONFIG_SYS_SPD_BUS_NUM  0
251 #define SPD_EEPROM_ADDRESS1     0x51
252 #define SPD_EEPROM_ADDRESS2     0x53
253
254 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
255 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
256
257 /*
258  * IFC Definitions
259  */
260 #define CONFIG_SYS_FLASH_BASE   0xe0000000
261 #ifdef CONFIG_PHYS_64BIT
262 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
263 #else
264 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
265 #endif
266
267 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
268 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
269                                 + 0x8000000) | \
270                                 CSPR_PORT_SIZE_16 | \
271                                 CSPR_MSEL_NOR | \
272                                 CSPR_V)
273 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
274 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
275                                 CSPR_PORT_SIZE_16 | \
276                                 CSPR_MSEL_NOR | \
277                                 CSPR_V)
278 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128 * 1024 * 1024)
279 /* NOR Flash Timing Params */
280 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(4)
281 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x01) | \
282                                 FTIM0_NOR_TEADC(0x04) | \
283                                 FTIM0_NOR_TEAHC(0x20))
284 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
285                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
286                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
287 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x01) | \
288                                 FTIM2_NOR_TCH(0x0E) | \
289                                 FTIM2_NOR_TWPH(0x0E) | \
290                                 FTIM2_NOR_TWP(0x1c))
291 #define CONFIG_SYS_NOR_FTIM3    0x0
292
293 #define CONFIG_SYS_FLASH_QUIET_TEST
294 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
295
296 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
297 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
298 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
299 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
300
301 #define CONFIG_SYS_FLASH_EMPTY_INFO
302 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
303                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
304
305 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
306 #define CONFIG_FSL_QIXIS_V2
307 #define QIXIS_BASE              0xffdf0000
308 #ifdef CONFIG_PHYS_64BIT
309 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
310 #else
311 #define QIXIS_BASE_PHYS         QIXIS_BASE
312 #endif
313 #define QIXIS_LBMAP_SWITCH              0x01
314 #define QIXIS_LBMAP_MASK                0x0f
315 #define QIXIS_LBMAP_SHIFT               0
316 #define QIXIS_LBMAP_DFLTBANK            0x00
317 #define QIXIS_LBMAP_ALTBANK             0x02
318 #define QIXIS_RST_CTL_RESET             0x31
319 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
320 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
321 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
322
323 #define CONFIG_SYS_CSPR3_EXT    (0xf)
324 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
325                                 | CSPR_PORT_SIZE_8 \
326                                 | CSPR_MSEL_GPCM \
327                                 | CSPR_V)
328 #define CONFIG_SYS_AMASK3       IFC_AMASK(4 * 1024)
329 #define CONFIG_SYS_CSOR3        0x0
330 /* QIXIS Timing parameters for IFC CS3 */
331 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
332                                         FTIM0_GPCM_TEADC(0x0e) | \
333                                         FTIM0_GPCM_TEAHC(0x0e))
334 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
335                                         FTIM1_GPCM_TRAD(0x1f))
336 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
337                                         FTIM2_GPCM_TCH(0x8) | \
338                                         FTIM2_GPCM_TWP(0x1f))
339 #define CONFIG_SYS_CS3_FTIM3            0x0
340
341 /* NAND Flash on IFC */
342 #define CONFIG_NAND_FSL_IFC
343 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
344 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
345 #define CONFIG_SYS_NAND_BASE            0xff800000
346 #ifdef CONFIG_PHYS_64BIT
347 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
348 #else
349 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
350 #endif
351
352 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
353 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
354                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
355                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
356                                 | CSPR_V)
357 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
358
359 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
360                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
361                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
362                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
363                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
364                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
365                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
366
367 #define CONFIG_SYS_NAND_ONFI_DETECTION
368
369 /* ONFI NAND Flash mode0 Timing Params */
370 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
371                                         FTIM0_NAND_TWP(0x18)   | \
372                                         FTIM0_NAND_TWCHT(0x07) | \
373                                         FTIM0_NAND_TWH(0x0a))
374 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
375                                         FTIM1_NAND_TWBE(0x39)  | \
376                                         FTIM1_NAND_TRR(0x0e)   | \
377                                         FTIM1_NAND_TRP(0x18))
378 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
379                                         FTIM2_NAND_TREH(0x0a) | \
380                                         FTIM2_NAND_TWHRE(0x1e))
381 #define CONFIG_SYS_NAND_FTIM3           0x0
382
383 #define CONFIG_SYS_NAND_DDR_LAW         11
384
385 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
386 #define CONFIG_SYS_MAX_NAND_DEVICE      1
387 #define CONFIG_CMD_NAND
388
389 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
390
391 #if defined(CONFIG_NAND)
392 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
393 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
394 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
395 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
396 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
397 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
398 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
399 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
400 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
401 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
402 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
403 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
404 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
405 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
406 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
407 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
408 #else
409 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
410 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
411 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
412 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
413 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
414 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
415 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
416 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
417 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
418 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
419 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
420 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
421 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
422 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
423 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
424 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
425 #endif
426 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
427 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
428 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
429 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
430 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
431 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
432 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
433 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
434
435 #ifdef CONFIG_SPL_BUILD
436 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
437 #else
438 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
439 #endif
440
441 #if defined(CONFIG_RAMBOOT_PBL)
442 #define CONFIG_SYS_RAMBOOT
443 #endif
444
445 #define CONFIG_BOARD_EARLY_INIT_R
446 #define CONFIG_MISC_INIT_R
447
448 #define CONFIG_HWCONFIG
449
450 /* define to use L1 as initial stack */
451 #define CONFIG_L1_INIT_RAM
452 #define CONFIG_SYS_INIT_RAM_LOCK
453 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
454 #ifdef CONFIG_PHYS_64BIT
455 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
456 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
457 /* The assembler doesn't like typecast */
458 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
459         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
460           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
461 #else
462 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
463 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
464 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
465 #endif
466 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
467
468 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
469                                         GENERATED_GBL_DATA_SIZE)
470 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
471
472 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
473 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
474
475 /* Serial Port - controlled on board with jumper J8
476  * open - index 2
477  * shorted - index 1
478  */
479 #define CONFIG_CONS_INDEX       1
480 #define CONFIG_SYS_NS16550_SERIAL
481 #define CONFIG_SYS_NS16550_REG_SIZE     1
482 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
483
484 #define CONFIG_SYS_BAUDRATE_TABLE       \
485         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
486
487 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
488 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
489 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
490 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
491 #ifndef CONFIG_SPL_BUILD
492 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
493 #endif
494
495 /* I2C */
496 #define CONFIG_SYS_I2C
497 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
498 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
499 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
500 #define CONFIG_SYS_FSL_I2C2_SPEED       400000  /* I2C speed in Hz */
501 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
502 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
503 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x119000
504
505 /*
506  * RTC configuration
507  */
508 #define RTC
509 #define CONFIG_RTC_DS3231               1
510 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
511
512 /*
513  * RapidIO
514  */
515 #ifdef CONFIG_SYS_SRIO
516 #ifdef CONFIG_SRIO1
517 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
518 #ifdef CONFIG_PHYS_64BIT
519 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
520 #else
521 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
522 #endif
523 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
524 #endif
525
526 #ifdef CONFIG_SRIO2
527 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
528 #ifdef CONFIG_PHYS_64BIT
529 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
530 #else
531 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
532 #endif
533 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
534 #endif
535 #endif
536
537 /*
538  * for slave u-boot IMAGE instored in master memory space,
539  * PHYS must be aligned based on the SIZE
540  */
541 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
542 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
543 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
544 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
545 /*
546  * for slave UCODE and ENV instored in master memory space,
547  * PHYS must be aligned based on the SIZE
548  */
549 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
550 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
551 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
552
553 /* slave core release by master*/
554 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
555 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
556
557 /*
558  * SRIO_PCIE_BOOT - SLAVE
559  */
560 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
561 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
562 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
563                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
564 #endif
565
566 /*
567  * eSPI - Enhanced SPI
568  */
569 #define CONFIG_SF_DEFAULT_SPEED         10000000
570 #define CONFIG_SF_DEFAULT_MODE          0
571
572 /*
573  * MAPLE
574  */
575 #ifdef CONFIG_PHYS_64BIT
576 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xFA0000000ull
577 #else
578 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xA0000000
579 #endif
580
581 /*
582  * General PCI
583  * Memory space is mapped 1-1, but I/O space must start from 0.
584  */
585
586 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
587 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
588 #ifdef CONFIG_PHYS_64BIT
589 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
590 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
591 #else
592 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
593 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
594 #endif
595 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
596 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
597 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
598 #ifdef CONFIG_PHYS_64BIT
599 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
600 #else
601 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
602 #endif
603 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
604
605 /* Qman/Bman */
606 #ifndef CONFIG_NOBQFMAN
607 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
608 #define CONFIG_SYS_BMAN_NUM_PORTALS     25
609 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
610 #ifdef CONFIG_PHYS_64BIT
611 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
612 #else
613 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
614 #endif
615 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
616 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
617 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
618 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
619 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
620 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
621                                         CONFIG_SYS_BMAN_CENA_SIZE)
622 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
623 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
624 #define CONFIG_SYS_QMAN_NUM_PORTALS     25
625 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
626 #ifdef CONFIG_PHYS_64BIT
627 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
628 #else
629 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
630 #endif
631 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
632 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
633 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
634 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
635 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
636 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
637                                         CONFIG_SYS_QMAN_CENA_SIZE)
638 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
639 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
640
641 #define CONFIG_SYS_DPAA_FMAN
642
643 #define CONFIG_SYS_DPAA_RMAN
644
645 /* Default address of microcode for the Linux Fman driver */
646 #if defined(CONFIG_SPIFLASH)
647 /*
648  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
649  * env, so we got 0x110000.
650  */
651 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
652 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
653 #elif defined(CONFIG_SDCARD)
654 /*
655  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
656  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
657  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
658  */
659 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
660 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
661 #elif defined(CONFIG_NAND)
662 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
663 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
664 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
665 /*
666  * Slave has no ucode locally, it can fetch this from remote. When implementing
667  * in two corenet boards, slave's ucode could be stored in master's memory
668  * space, the address can be mapped from slave TLB->slave LAW->
669  * slave SRIO or PCIE outbound window->master inbound window->
670  * master LAW->the ucode address in master's memory space.
671  */
672 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
673 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
674 #else
675 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
676 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
677 #endif
678 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
679 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
680 #endif /* CONFIG_NOBQFMAN */
681
682 #ifdef CONFIG_SYS_DPAA_FMAN
683 #define CONFIG_FMAN_ENET
684 #define CONFIG_PHYLIB_10G
685 #define CONFIG_PHY_VITESSE
686 #define CONFIG_PHY_TERANETICS
687 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
688 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
689 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
690 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
691 #endif
692
693 #ifdef CONFIG_PCI
694 #define CONFIG_PCI_INDIRECT_BRIDGE
695 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
696
697 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
698 #define CONFIG_DOS_PARTITION
699 #endif  /* CONFIG_PCI */
700
701 #ifdef CONFIG_FMAN_ENET
702 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
703 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
704
705 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
706 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7       /*SLOT 1*/
707 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6       /*SLOT 2*/
708
709 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
710 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
711 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
712 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
713
714 #define CONFIG_MII              /* MII PHY management */
715 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
716 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
717 #endif
718
719 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
720
721 /*
722  * Environment
723  */
724 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
725 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
726
727 /*
728  * Command line configuration.
729  */
730 #define CONFIG_CMD_DATE
731 #define CONFIG_CMD_EEPROM
732 #define CONFIG_CMD_ERRATA
733 #define CONFIG_CMD_IRQ
734 #define CONFIG_CMD_REGINFO
735
736 #ifdef CONFIG_PCI
737 #define CONFIG_CMD_PCI
738 #endif
739
740 /* Hash command with SHA acceleration supported in hardware */
741 #ifdef CONFIG_FSL_CAAM
742 #define CONFIG_CMD_HASH
743 #define CONFIG_SHA_HW_ACCEL
744 #endif
745
746 /*
747 * USB
748 */
749 #define CONFIG_HAS_FSL_DR_USB
750
751 #ifdef CONFIG_HAS_FSL_DR_USB
752 #define CONFIG_USB_EHCI
753
754 #ifdef CONFIG_USB_EHCI
755 #define CONFIG_USB_EHCI_FSL
756 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
757 #endif
758 #endif
759
760 /*
761  * Miscellaneous configurable options
762  */
763 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
764 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
765 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
766 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
767 #ifdef CONFIG_CMD_KGDB
768 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
769 #else
770 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
771 #endif
772 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
773 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
774 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
775
776 /*
777  * For booting Linux, the board info and command line data
778  * have to be in the first 64 MB of memory, since this is
779  * the maximum mapped by the Linux kernel during initialization.
780  */
781 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
782 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
783
784 #ifdef CONFIG_CMD_KGDB
785 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
786 #endif
787
788 /*
789  * Environment Configuration
790  */
791 #define CONFIG_ROOTPATH         "/opt/nfsroot"
792 #define CONFIG_BOOTFILE         "uImage"
793 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
794
795 /* default location for tftp and bootm */
796 #define CONFIG_LOADADDR         1000000
797
798
799 #define CONFIG_BAUDRATE 115200
800
801 #define __USB_PHY_TYPE  ulpi
802
803 #ifdef CONFIG_PPC_B4860
804 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,"     \
805                         "bank_intlv=cs0_cs1;"   \
806                         "en_cpc:cpc2;"
807 #else
808 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
809 #endif
810
811 #define CONFIG_EXTRA_ENV_SETTINGS                               \
812         HWCONFIG                                                \
813         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
814         "netdev=eth0\0"                                         \
815         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
816         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"                     \
817         "tftpflash=tftpboot $loadaddr $uboot && "               \
818         "protect off $ubootaddr +$filesize && "                 \
819         "erase $ubootaddr +$filesize && "                       \
820         "cp.b $loadaddr $ubootaddr $filesize && "               \
821         "protect on $ubootaddr +$filesize && "                  \
822         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
823         "consoledev=ttyS0\0"                                    \
824         "ramdiskaddr=2000000\0"                                 \
825         "ramdiskfile=b4860qds/ramdisk.uboot\0"                  \
826         "fdtaddr=1e00000\0"                                     \
827         "fdtfile=b4860qds/b4860qds.dtb\0"                               \
828         "bdev=sda3\0"
829
830 /* For emulation this causes u-boot to jump to the start of the proof point
831    app code automatically */
832 #define CONFIG_PROOF_POINTS                     \
833  "setenv bootargs root=/dev/$bdev rw "          \
834  "console=$consoledev,$baudrate $othbootargs;"  \
835  "cpu 1 release 0x29000000 - - -;"              \
836  "cpu 2 release 0x29000000 - - -;"              \
837  "cpu 3 release 0x29000000 - - -;"              \
838  "cpu 4 release 0x29000000 - - -;"              \
839  "cpu 5 release 0x29000000 - - -;"              \
840  "cpu 6 release 0x29000000 - - -;"              \
841  "cpu 7 release 0x29000000 - - -;"              \
842  "go 0x29000000"
843
844 #define CONFIG_HVBOOT   \
845  "setenv bootargs config-addr=0x60000000; "     \
846  "bootm 0x01000000 - 0x00f00000"
847
848 #define CONFIG_ALU                              \
849  "setenv bootargs root=/dev/$bdev rw "          \
850  "console=$consoledev,$baudrate $othbootargs;"  \
851  "cpu 1 release 0x01000000 - - -;"              \
852  "cpu 2 release 0x01000000 - - -;"              \
853  "cpu 3 release 0x01000000 - - -;"              \
854  "cpu 4 release 0x01000000 - - -;"              \
855  "cpu 5 release 0x01000000 - - -;"              \
856  "cpu 6 release 0x01000000 - - -;"              \
857  "cpu 7 release 0x01000000 - - -;"              \
858  "go 0x01000000"
859
860 #define CONFIG_LINUX                            \
861  "setenv bootargs root=/dev/ram rw "            \
862  "console=$consoledev,$baudrate $othbootargs;"  \
863  "setenv ramdiskaddr 0x02000000;"               \
864  "setenv fdtaddr 0x01e00000;"                   \
865  "setenv loadaddr 0x1000000;"                   \
866  "bootm $loadaddr $ramdiskaddr $fdtaddr"
867
868 #define CONFIG_HDBOOT                                   \
869         "setenv bootargs root=/dev/$bdev rw "           \
870         "console=$consoledev,$baudrate $othbootargs;"   \
871         "tftp $loadaddr $bootfile;"                     \
872         "tftp $fdtaddr $fdtfile;"                       \
873         "bootm $loadaddr - $fdtaddr"
874
875 #define CONFIG_NFSBOOTCOMMAND                   \
876         "setenv bootargs root=/dev/nfs rw "     \
877         "nfsroot=$serverip:$rootpath "          \
878         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
879         "console=$consoledev,$baudrate $othbootargs;"   \
880         "tftp $loadaddr $bootfile;"             \
881         "tftp $fdtaddr $fdtfile;"               \
882         "bootm $loadaddr - $fdtaddr"
883
884 #define CONFIG_RAMBOOTCOMMAND                           \
885         "setenv bootargs root=/dev/ram rw "             \
886         "console=$consoledev,$baudrate $othbootargs;"   \
887         "tftp $ramdiskaddr $ramdiskfile;"               \
888         "tftp $loadaddr $bootfile;"                     \
889         "tftp $fdtaddr $fdtfile;"                       \
890         "bootm $loadaddr $ramdiskaddr $fdtaddr"
891
892 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
893
894 #include <asm/fsl_secure_boot.h>
895
896 #endif  /* __CONFIG_H */