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fsl_ddr: Move DDR config options to driver Kconfig
[u-boot] / include / configs / B4860QDS.h
1 /*
2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9
10 /*
11  * B4860 QDS board configuration file
12  */
13 #ifdef CONFIG_RAMBOOT_PBL
14 #define CONFIG_SYS_FSL_PBL_PBI  $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
15 #define CONFIG_SYS_FSL_PBL_RCW  $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
16 #ifndef CONFIG_NAND
17 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
18 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
19 #else
20 #define CONFIG_SPL_FLUSH_IMAGE
21 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
22 #define CONFIG_SYS_TEXT_BASE            0x00201000
23 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
24 #define CONFIG_SPL_PAD_TO               0x40000
25 #define CONFIG_SPL_MAX_SIZE             0x28000
26 #define RESET_VECTOR_OFFSET             0x27FFC
27 #define BOOT_PAGE_OFFSET                0x27000
28 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
29 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
30 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
31 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
32 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
33 #define CONFIG_SPL_NAND_BOOT
34 #ifdef CONFIG_SPL_BUILD
35 #define CONFIG_SPL_SKIP_RELOCATE
36 #define CONFIG_SPL_COMMON_INIT_DDR
37 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
38 #define CONFIG_SYS_NO_FLASH
39 #endif
40 #endif
41 #endif
42
43 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
44 /* Set 1M boot space */
45 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
46 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
47                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
48 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
49 #define CONFIG_SYS_NO_FLASH
50 #endif
51
52 /* High Level Configuration Options */
53 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
54 #define CONFIG_MP                       /* support multiple processors */
55
56 #ifndef CONFIG_SYS_TEXT_BASE
57 #define CONFIG_SYS_TEXT_BASE    0xeff40000
58 #endif
59
60 #ifndef CONFIG_RESET_VECTOR_ADDRESS
61 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
62 #endif
63
64 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
65 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
66 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
67 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
68 #define CONFIG_PCIE1                    /* PCIE controller 1 */
69 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
70 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
71
72 #ifndef CONFIG_ARCH_B4420
73 #define CONFIG_SYS_SRIO
74 #define CONFIG_SRIO1                    /* SRIO port 1 */
75 #define CONFIG_SRIO2                    /* SRIO port 2 */
76 #define CONFIG_SRIO_PCIE_BOOT_MASTER
77 #endif
78
79 /* I2C bus multiplexer */
80 #define I2C_MUX_PCA_ADDR                0x77
81
82 /* VSC Crossbar switches */
83 #define CONFIG_VSC_CROSSBAR
84 #define I2C_CH_DEFAULT                  0x8
85 #define I2C_CH_VSC3316                  0xc
86 #define I2C_CH_VSC3308                  0xd
87
88 #define VSC3316_TX_ADDRESS              0x70
89 #define VSC3316_RX_ADDRESS              0x71
90 #define VSC3308_TX_ADDRESS              0x02
91 #define VSC3308_RX_ADDRESS              0x03
92
93 /* IDT clock synthesizers */
94 #define CONFIG_IDT8T49N222A
95 #define I2C_CH_IDT                     0x9
96
97 #define IDT_SERDES1_ADDRESS            0x6E
98 #define IDT_SERDES2_ADDRESS            0x6C
99
100 /* Voltage monitor on channel 2*/
101 #define I2C_MUX_CH_VOL_MONITOR          0xa
102 #define I2C_VOL_MONITOR_ADDR            0x40
103 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
104 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
105 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
106
107 #define CONFIG_ZM7300
108 #define I2C_MUX_CH_DPM                  0xa
109 #define I2C_DPM_ADDR                    0x28
110
111 #define CONFIG_ENV_OVERWRITE
112
113 #ifdef CONFIG_SYS_NO_FLASH
114 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
115 #define CONFIG_ENV_IS_NOWHERE
116 #endif
117 #else
118 #define CONFIG_FLASH_CFI_DRIVER
119 #define CONFIG_SYS_FLASH_CFI
120 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
121 #endif
122
123 #if defined(CONFIG_SPIFLASH)
124 #define CONFIG_SYS_EXTRA_ENV_RELOC
125 #define CONFIG_ENV_IS_IN_SPI_FLASH
126 #define CONFIG_ENV_SPI_BUS              0
127 #define CONFIG_ENV_SPI_CS               0
128 #define CONFIG_ENV_SPI_MAX_HZ           10000000
129 #define CONFIG_ENV_SPI_MODE             0
130 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
131 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
132 #define CONFIG_ENV_SECT_SIZE            0x10000
133 #elif defined(CONFIG_SDCARD)
134 #define CONFIG_SYS_EXTRA_ENV_RELOC
135 #define CONFIG_ENV_IS_IN_MMC
136 #define CONFIG_SYS_MMC_ENV_DEV          0
137 #define CONFIG_ENV_SIZE                 0x2000
138 #define CONFIG_ENV_OFFSET               (512 * 1097)
139 #elif defined(CONFIG_NAND)
140 #define CONFIG_SYS_EXTRA_ENV_RELOC
141 #define CONFIG_ENV_IS_IN_NAND
142 #define CONFIG_ENV_SIZE                 0x2000
143 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
144 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
145 #define CONFIG_ENV_IS_IN_REMOTE
146 #define CONFIG_ENV_ADDR         0xffe20000
147 #define CONFIG_ENV_SIZE         0x2000
148 #elif defined(CONFIG_ENV_IS_NOWHERE)
149 #define CONFIG_ENV_SIZE         0x2000
150 #else
151 #define CONFIG_ENV_IS_IN_FLASH
152 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
153 #define CONFIG_ENV_SIZE         0x2000
154 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
155 #endif
156
157 #ifndef __ASSEMBLY__
158 unsigned long get_board_sys_clk(void);
159 unsigned long get_board_ddr_clk(void);
160 #endif
161 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
162 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
163
164 /*
165  * These can be toggled for performance analysis, otherwise use default.
166  */
167 #define CONFIG_SYS_CACHE_STASHING
168 #define CONFIG_BTB                      /* toggle branch predition */
169 #define CONFIG_DDR_ECC
170 #ifdef CONFIG_DDR_ECC
171 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
172 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
173 #endif
174
175 #define CONFIG_ENABLE_36BIT_PHYS
176
177 #ifdef CONFIG_PHYS_64BIT
178 #define CONFIG_ADDR_MAP
179 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
180 #endif
181
182 #if 0
183 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
184 #endif
185 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
186 #define CONFIG_SYS_MEMTEST_END          0x00400000
187 #define CONFIG_SYS_ALT_MEMTEST
188 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
189
190 /*
191  *  Config the L3 Cache as L3 SRAM
192  */
193 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
194 #define CONFIG_SYS_L3_SIZE              256 << 10
195 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
196 #ifdef CONFIG_NAND
197 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
198 #endif
199 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
200 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
201 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
202 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
203
204 #ifdef CONFIG_PHYS_64BIT
205 #define CONFIG_SYS_DCSRBAR              0xf0000000
206 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
207 #endif
208
209 /* EEPROM */
210 #define CONFIG_ID_EEPROM
211 #define CONFIG_SYS_I2C_EEPROM_NXID
212 #define CONFIG_SYS_EEPROM_BUS_NUM       0
213 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
214 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
215 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
216 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
217
218 /*
219  * DDR Setup
220  */
221 #define CONFIG_VERY_BIG_RAM
222 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
223 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
224
225 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
226 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
227 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
228
229 #define CONFIG_DDR_SPD
230 #define CONFIG_SYS_DDR_RAW_TIMING
231 #ifndef CONFIG_SPL_BUILD
232 #define CONFIG_FSL_DDR_INTERACTIVE
233 #endif
234
235 #define CONFIG_SYS_SPD_BUS_NUM  0
236 #define SPD_EEPROM_ADDRESS1     0x51
237 #define SPD_EEPROM_ADDRESS2     0x53
238
239 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
240 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
241
242 /*
243  * IFC Definitions
244  */
245 #define CONFIG_SYS_FLASH_BASE   0xe0000000
246 #ifdef CONFIG_PHYS_64BIT
247 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
248 #else
249 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
250 #endif
251
252 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
253 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
254                                 + 0x8000000) | \
255                                 CSPR_PORT_SIZE_16 | \
256                                 CSPR_MSEL_NOR | \
257                                 CSPR_V)
258 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
259 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
260                                 CSPR_PORT_SIZE_16 | \
261                                 CSPR_MSEL_NOR | \
262                                 CSPR_V)
263 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128 * 1024 * 1024)
264 /* NOR Flash Timing Params */
265 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(4)
266 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x01) | \
267                                 FTIM0_NOR_TEADC(0x04) | \
268                                 FTIM0_NOR_TEAHC(0x20))
269 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
270                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
271                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
272 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x01) | \
273                                 FTIM2_NOR_TCH(0x0E) | \
274                                 FTIM2_NOR_TWPH(0x0E) | \
275                                 FTIM2_NOR_TWP(0x1c))
276 #define CONFIG_SYS_NOR_FTIM3    0x0
277
278 #define CONFIG_SYS_FLASH_QUIET_TEST
279 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
280
281 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
282 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
283 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
284 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
285
286 #define CONFIG_SYS_FLASH_EMPTY_INFO
287 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
288                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
289
290 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
291 #define CONFIG_FSL_QIXIS_V2
292 #define QIXIS_BASE              0xffdf0000
293 #ifdef CONFIG_PHYS_64BIT
294 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
295 #else
296 #define QIXIS_BASE_PHYS         QIXIS_BASE
297 #endif
298 #define QIXIS_LBMAP_SWITCH              0x01
299 #define QIXIS_LBMAP_MASK                0x0f
300 #define QIXIS_LBMAP_SHIFT               0
301 #define QIXIS_LBMAP_DFLTBANK            0x00
302 #define QIXIS_LBMAP_ALTBANK             0x02
303 #define QIXIS_RST_CTL_RESET             0x31
304 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
305 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
306 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
307
308 #define CONFIG_SYS_CSPR3_EXT    (0xf)
309 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
310                                 | CSPR_PORT_SIZE_8 \
311                                 | CSPR_MSEL_GPCM \
312                                 | CSPR_V)
313 #define CONFIG_SYS_AMASK3       IFC_AMASK(4 * 1024)
314 #define CONFIG_SYS_CSOR3        0x0
315 /* QIXIS Timing parameters for IFC CS3 */
316 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
317                                         FTIM0_GPCM_TEADC(0x0e) | \
318                                         FTIM0_GPCM_TEAHC(0x0e))
319 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
320                                         FTIM1_GPCM_TRAD(0x1f))
321 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
322                                         FTIM2_GPCM_TCH(0x8) | \
323                                         FTIM2_GPCM_TWP(0x1f))
324 #define CONFIG_SYS_CS3_FTIM3            0x0
325
326 /* NAND Flash on IFC */
327 #define CONFIG_NAND_FSL_IFC
328 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
329 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
330 #define CONFIG_SYS_NAND_BASE            0xff800000
331 #ifdef CONFIG_PHYS_64BIT
332 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
333 #else
334 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
335 #endif
336
337 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
338 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
339                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
340                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
341                                 | CSPR_V)
342 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
343
344 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
345                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
346                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
347                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
348                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
349                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
350                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
351
352 #define CONFIG_SYS_NAND_ONFI_DETECTION
353
354 /* ONFI NAND Flash mode0 Timing Params */
355 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
356                                         FTIM0_NAND_TWP(0x18)   | \
357                                         FTIM0_NAND_TWCHT(0x07) | \
358                                         FTIM0_NAND_TWH(0x0a))
359 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
360                                         FTIM1_NAND_TWBE(0x39)  | \
361                                         FTIM1_NAND_TRR(0x0e)   | \
362                                         FTIM1_NAND_TRP(0x18))
363 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
364                                         FTIM2_NAND_TREH(0x0a) | \
365                                         FTIM2_NAND_TWHRE(0x1e))
366 #define CONFIG_SYS_NAND_FTIM3           0x0
367
368 #define CONFIG_SYS_NAND_DDR_LAW         11
369
370 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
371 #define CONFIG_SYS_MAX_NAND_DEVICE      1
372 #define CONFIG_CMD_NAND
373
374 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
375
376 #if defined(CONFIG_NAND)
377 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
378 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
379 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
380 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
381 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
382 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
383 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
384 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
385 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
386 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
387 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
388 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
389 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
390 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
391 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
392 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
393 #else
394 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
395 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
396 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
397 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
398 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
399 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
400 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
401 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
402 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
403 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
404 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
405 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
406 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
407 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
408 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
409 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
410 #endif
411 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
412 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
413 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
414 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
415 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
416 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
417 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
418 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
419
420 #ifdef CONFIG_SPL_BUILD
421 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
422 #else
423 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
424 #endif
425
426 #if defined(CONFIG_RAMBOOT_PBL)
427 #define CONFIG_SYS_RAMBOOT
428 #endif
429
430 #define CONFIG_BOARD_EARLY_INIT_R
431 #define CONFIG_MISC_INIT_R
432
433 #define CONFIG_HWCONFIG
434
435 /* define to use L1 as initial stack */
436 #define CONFIG_L1_INIT_RAM
437 #define CONFIG_SYS_INIT_RAM_LOCK
438 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
439 #ifdef CONFIG_PHYS_64BIT
440 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
441 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
442 /* The assembler doesn't like typecast */
443 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
444         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
445           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
446 #else
447 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
448 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
449 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
450 #endif
451 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
452
453 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
454                                         GENERATED_GBL_DATA_SIZE)
455 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
456
457 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
458 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
459
460 /* Serial Port - controlled on board with jumper J8
461  * open - index 2
462  * shorted - index 1
463  */
464 #define CONFIG_CONS_INDEX       1
465 #define CONFIG_SYS_NS16550_SERIAL
466 #define CONFIG_SYS_NS16550_REG_SIZE     1
467 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
468
469 #define CONFIG_SYS_BAUDRATE_TABLE       \
470         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
471
472 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
473 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
474 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
475 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
476
477 /* I2C */
478 #define CONFIG_SYS_I2C
479 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
480 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
481 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
482 #define CONFIG_SYS_FSL_I2C2_SPEED       400000  /* I2C speed in Hz */
483 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
484 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
485 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x119000
486
487 /*
488  * RTC configuration
489  */
490 #define RTC
491 #define CONFIG_RTC_DS3231               1
492 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
493
494 /*
495  * RapidIO
496  */
497 #ifdef CONFIG_SYS_SRIO
498 #ifdef CONFIG_SRIO1
499 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
500 #ifdef CONFIG_PHYS_64BIT
501 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
502 #else
503 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
504 #endif
505 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
506 #endif
507
508 #ifdef CONFIG_SRIO2
509 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
510 #ifdef CONFIG_PHYS_64BIT
511 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
512 #else
513 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
514 #endif
515 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
516 #endif
517 #endif
518
519 /*
520  * for slave u-boot IMAGE instored in master memory space,
521  * PHYS must be aligned based on the SIZE
522  */
523 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
524 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
525 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
526 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
527 /*
528  * for slave UCODE and ENV instored in master memory space,
529  * PHYS must be aligned based on the SIZE
530  */
531 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
532 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
533 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
534
535 /* slave core release by master*/
536 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
537 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
538
539 /*
540  * SRIO_PCIE_BOOT - SLAVE
541  */
542 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
543 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
544 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
545                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
546 #endif
547
548 /*
549  * eSPI - Enhanced SPI
550  */
551 #define CONFIG_SF_DEFAULT_SPEED         10000000
552 #define CONFIG_SF_DEFAULT_MODE          0
553
554 /*
555  * MAPLE
556  */
557 #ifdef CONFIG_PHYS_64BIT
558 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xFA0000000ull
559 #else
560 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xA0000000
561 #endif
562
563 /*
564  * General PCI
565  * Memory space is mapped 1-1, but I/O space must start from 0.
566  */
567
568 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
569 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
570 #ifdef CONFIG_PHYS_64BIT
571 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
572 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
573 #else
574 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
575 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
576 #endif
577 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
578 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
579 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
580 #ifdef CONFIG_PHYS_64BIT
581 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
582 #else
583 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
584 #endif
585 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
586
587 /* Qman/Bman */
588 #ifndef CONFIG_NOBQFMAN
589 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
590 #define CONFIG_SYS_BMAN_NUM_PORTALS     25
591 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
592 #ifdef CONFIG_PHYS_64BIT
593 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
594 #else
595 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
596 #endif
597 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
598 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
599 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
600 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
601 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
602 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
603                                         CONFIG_SYS_BMAN_CENA_SIZE)
604 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
605 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
606 #define CONFIG_SYS_QMAN_NUM_PORTALS     25
607 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
608 #ifdef CONFIG_PHYS_64BIT
609 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
610 #else
611 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
612 #endif
613 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
614 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
615 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
616 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
617 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
618 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
619                                         CONFIG_SYS_QMAN_CENA_SIZE)
620 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
621 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
622
623 #define CONFIG_SYS_DPAA_FMAN
624
625 #define CONFIG_SYS_DPAA_RMAN
626
627 /* Default address of microcode for the Linux Fman driver */
628 #if defined(CONFIG_SPIFLASH)
629 /*
630  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
631  * env, so we got 0x110000.
632  */
633 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
634 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
635 #elif defined(CONFIG_SDCARD)
636 /*
637  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
638  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
639  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
640  */
641 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
642 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
643 #elif defined(CONFIG_NAND)
644 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
645 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
646 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
647 /*
648  * Slave has no ucode locally, it can fetch this from remote. When implementing
649  * in two corenet boards, slave's ucode could be stored in master's memory
650  * space, the address can be mapped from slave TLB->slave LAW->
651  * slave SRIO or PCIE outbound window->master inbound window->
652  * master LAW->the ucode address in master's memory space.
653  */
654 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
655 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
656 #else
657 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
658 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
659 #endif
660 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
661 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
662 #endif /* CONFIG_NOBQFMAN */
663
664 #ifdef CONFIG_SYS_DPAA_FMAN
665 #define CONFIG_FMAN_ENET
666 #define CONFIG_PHYLIB_10G
667 #define CONFIG_PHY_VITESSE
668 #define CONFIG_PHY_TERANETICS
669 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
670 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
671 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
672 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
673 #endif
674
675 #ifdef CONFIG_PCI
676 #define CONFIG_PCI_INDIRECT_BRIDGE
677
678 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
679 #define CONFIG_DOS_PARTITION
680 #endif  /* CONFIG_PCI */
681
682 #ifdef CONFIG_FMAN_ENET
683 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
684 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
685
686 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
687 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7       /*SLOT 1*/
688 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6       /*SLOT 2*/
689
690 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
691 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
692 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
693 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
694
695 #define CONFIG_MII              /* MII PHY management */
696 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
697 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
698 #endif
699
700 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
701
702 /*
703  * Environment
704  */
705 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
706 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
707
708 /*
709  * Command line configuration.
710  */
711 #define CONFIG_CMD_DATE
712 #define CONFIG_CMD_EEPROM
713 #define CONFIG_CMD_ERRATA
714 #define CONFIG_CMD_IRQ
715 #define CONFIG_CMD_REGINFO
716
717 #ifdef CONFIG_PCI
718 #define CONFIG_CMD_PCI
719 #endif
720
721 /* Hash command with SHA acceleration supported in hardware */
722 #ifdef CONFIG_FSL_CAAM
723 #define CONFIG_CMD_HASH
724 #define CONFIG_SHA_HW_ACCEL
725 #endif
726
727 /*
728 * USB
729 */
730 #define CONFIG_HAS_FSL_DR_USB
731
732 #ifdef CONFIG_HAS_FSL_DR_USB
733 #define CONFIG_USB_EHCI
734
735 #ifdef CONFIG_USB_EHCI
736 #define CONFIG_USB_EHCI_FSL
737 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
738 #endif
739 #endif
740
741 /*
742  * Miscellaneous configurable options
743  */
744 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
745 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
746 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
747 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
748 #ifdef CONFIG_CMD_KGDB
749 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
750 #else
751 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
752 #endif
753 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
754 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
755 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
756
757 /*
758  * For booting Linux, the board info and command line data
759  * have to be in the first 64 MB of memory, since this is
760  * the maximum mapped by the Linux kernel during initialization.
761  */
762 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
763 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
764
765 #ifdef CONFIG_CMD_KGDB
766 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
767 #endif
768
769 /*
770  * Environment Configuration
771  */
772 #define CONFIG_ROOTPATH         "/opt/nfsroot"
773 #define CONFIG_BOOTFILE         "uImage"
774 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
775
776 /* default location for tftp and bootm */
777 #define CONFIG_LOADADDR         1000000
778
779
780 #define CONFIG_BAUDRATE 115200
781
782 #define __USB_PHY_TYPE  ulpi
783
784 #ifdef CONFIG_ARCH_B4860
785 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,"     \
786                         "bank_intlv=cs0_cs1;"   \
787                         "en_cpc:cpc2;"
788 #else
789 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
790 #endif
791
792 #define CONFIG_EXTRA_ENV_SETTINGS                               \
793         HWCONFIG                                                \
794         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
795         "netdev=eth0\0"                                         \
796         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
797         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"                     \
798         "tftpflash=tftpboot $loadaddr $uboot && "               \
799         "protect off $ubootaddr +$filesize && "                 \
800         "erase $ubootaddr +$filesize && "                       \
801         "cp.b $loadaddr $ubootaddr $filesize && "               \
802         "protect on $ubootaddr +$filesize && "                  \
803         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
804         "consoledev=ttyS0\0"                                    \
805         "ramdiskaddr=2000000\0"                                 \
806         "ramdiskfile=b4860qds/ramdisk.uboot\0"                  \
807         "fdtaddr=1e00000\0"                                     \
808         "fdtfile=b4860qds/b4860qds.dtb\0"                               \
809         "bdev=sda3\0"
810
811 /* For emulation this causes u-boot to jump to the start of the proof point
812    app code automatically */
813 #define CONFIG_PROOF_POINTS                     \
814  "setenv bootargs root=/dev/$bdev rw "          \
815  "console=$consoledev,$baudrate $othbootargs;"  \
816  "cpu 1 release 0x29000000 - - -;"              \
817  "cpu 2 release 0x29000000 - - -;"              \
818  "cpu 3 release 0x29000000 - - -;"              \
819  "cpu 4 release 0x29000000 - - -;"              \
820  "cpu 5 release 0x29000000 - - -;"              \
821  "cpu 6 release 0x29000000 - - -;"              \
822  "cpu 7 release 0x29000000 - - -;"              \
823  "go 0x29000000"
824
825 #define CONFIG_HVBOOT   \
826  "setenv bootargs config-addr=0x60000000; "     \
827  "bootm 0x01000000 - 0x00f00000"
828
829 #define CONFIG_ALU                              \
830  "setenv bootargs root=/dev/$bdev rw "          \
831  "console=$consoledev,$baudrate $othbootargs;"  \
832  "cpu 1 release 0x01000000 - - -;"              \
833  "cpu 2 release 0x01000000 - - -;"              \
834  "cpu 3 release 0x01000000 - - -;"              \
835  "cpu 4 release 0x01000000 - - -;"              \
836  "cpu 5 release 0x01000000 - - -;"              \
837  "cpu 6 release 0x01000000 - - -;"              \
838  "cpu 7 release 0x01000000 - - -;"              \
839  "go 0x01000000"
840
841 #define CONFIG_LINUX                            \
842  "setenv bootargs root=/dev/ram rw "            \
843  "console=$consoledev,$baudrate $othbootargs;"  \
844  "setenv ramdiskaddr 0x02000000;"               \
845  "setenv fdtaddr 0x01e00000;"                   \
846  "setenv loadaddr 0x1000000;"                   \
847  "bootm $loadaddr $ramdiskaddr $fdtaddr"
848
849 #define CONFIG_HDBOOT                                   \
850         "setenv bootargs root=/dev/$bdev rw "           \
851         "console=$consoledev,$baudrate $othbootargs;"   \
852         "tftp $loadaddr $bootfile;"                     \
853         "tftp $fdtaddr $fdtfile;"                       \
854         "bootm $loadaddr - $fdtaddr"
855
856 #define CONFIG_NFSBOOTCOMMAND                   \
857         "setenv bootargs root=/dev/nfs rw "     \
858         "nfsroot=$serverip:$rootpath "          \
859         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
860         "console=$consoledev,$baudrate $othbootargs;"   \
861         "tftp $loadaddr $bootfile;"             \
862         "tftp $fdtaddr $fdtfile;"               \
863         "bootm $loadaddr - $fdtaddr"
864
865 #define CONFIG_RAMBOOTCOMMAND                           \
866         "setenv bootargs root=/dev/ram rw "             \
867         "console=$consoledev,$baudrate $othbootargs;"   \
868         "tftp $ramdiskaddr $ramdiskfile;"               \
869         "tftp $loadaddr $bootfile;"                     \
870         "tftp $fdtaddr $fdtfile;"                       \
871         "bootm $loadaddr $ramdiskaddr $fdtaddr"
872
873 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
874
875 #include <asm/fsl_secure_boot.h>
876
877 #endif  /* __CONFIG_H */