2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 * B4860 QDS board configuration file
13 #ifdef CONFIG_RAMBOOT_PBL
14 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
15 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
20 #define CONFIG_SPL_FLUSH_IMAGE
21 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
22 #define CONFIG_SYS_TEXT_BASE 0x00201000
23 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
24 #define CONFIG_SPL_PAD_TO 0x40000
25 #define CONFIG_SPL_MAX_SIZE 0x28000
26 #define RESET_VECTOR_OFFSET 0x27FFC
27 #define BOOT_PAGE_OFFSET 0x27000
28 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
29 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
30 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
31 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
32 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
33 #define CONFIG_SPL_NAND_BOOT
34 #ifdef CONFIG_SPL_BUILD
35 #define CONFIG_SPL_SKIP_RELOCATE
36 #define CONFIG_SPL_COMMON_INIT_DDR
37 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
38 #define CONFIG_SYS_NO_FLASH
43 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
44 /* Set 1M boot space */
45 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
46 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
47 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
48 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
49 #define CONFIG_SYS_NO_FLASH
52 /* High Level Configuration Options */
53 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
54 #define CONFIG_MP /* support multiple processors */
56 #ifndef CONFIG_SYS_TEXT_BASE
57 #define CONFIG_SYS_TEXT_BASE 0xeff40000
60 #ifndef CONFIG_RESET_VECTOR_ADDRESS
61 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
64 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
65 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
66 #define CONFIG_FSL_IFC /* Enable IFC Support */
67 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
68 #define CONFIG_PCIE1 /* PCIE controller 1 */
69 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
70 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
72 #ifndef CONFIG_ARCH_B4420
73 #define CONFIG_SYS_SRIO
74 #define CONFIG_SRIO1 /* SRIO port 1 */
75 #define CONFIG_SRIO2 /* SRIO port 2 */
76 #define CONFIG_SRIO_PCIE_BOOT_MASTER
79 /* I2C bus multiplexer */
80 #define I2C_MUX_PCA_ADDR 0x77
82 /* VSC Crossbar switches */
83 #define CONFIG_VSC_CROSSBAR
84 #define I2C_CH_DEFAULT 0x8
85 #define I2C_CH_VSC3316 0xc
86 #define I2C_CH_VSC3308 0xd
88 #define VSC3316_TX_ADDRESS 0x70
89 #define VSC3316_RX_ADDRESS 0x71
90 #define VSC3308_TX_ADDRESS 0x02
91 #define VSC3308_RX_ADDRESS 0x03
93 /* IDT clock synthesizers */
94 #define CONFIG_IDT8T49N222A
95 #define I2C_CH_IDT 0x9
97 #define IDT_SERDES1_ADDRESS 0x6E
98 #define IDT_SERDES2_ADDRESS 0x6C
100 /* Voltage monitor on channel 2*/
101 #define I2C_MUX_CH_VOL_MONITOR 0xa
102 #define I2C_VOL_MONITOR_ADDR 0x40
103 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
104 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
105 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
107 #define CONFIG_ZM7300
108 #define I2C_MUX_CH_DPM 0xa
109 #define I2C_DPM_ADDR 0x28
111 #define CONFIG_ENV_OVERWRITE
113 #ifdef CONFIG_SYS_NO_FLASH
114 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
115 #define CONFIG_ENV_IS_NOWHERE
118 #define CONFIG_FLASH_CFI_DRIVER
119 #define CONFIG_SYS_FLASH_CFI
120 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
123 #if defined(CONFIG_SPIFLASH)
124 #define CONFIG_SYS_EXTRA_ENV_RELOC
125 #define CONFIG_ENV_IS_IN_SPI_FLASH
126 #define CONFIG_ENV_SPI_BUS 0
127 #define CONFIG_ENV_SPI_CS 0
128 #define CONFIG_ENV_SPI_MAX_HZ 10000000
129 #define CONFIG_ENV_SPI_MODE 0
130 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
131 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
132 #define CONFIG_ENV_SECT_SIZE 0x10000
133 #elif defined(CONFIG_SDCARD)
134 #define CONFIG_SYS_EXTRA_ENV_RELOC
135 #define CONFIG_ENV_IS_IN_MMC
136 #define CONFIG_SYS_MMC_ENV_DEV 0
137 #define CONFIG_ENV_SIZE 0x2000
138 #define CONFIG_ENV_OFFSET (512 * 1097)
139 #elif defined(CONFIG_NAND)
140 #define CONFIG_SYS_EXTRA_ENV_RELOC
141 #define CONFIG_ENV_IS_IN_NAND
142 #define CONFIG_ENV_SIZE 0x2000
143 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
144 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
145 #define CONFIG_ENV_IS_IN_REMOTE
146 #define CONFIG_ENV_ADDR 0xffe20000
147 #define CONFIG_ENV_SIZE 0x2000
148 #elif defined(CONFIG_ENV_IS_NOWHERE)
149 #define CONFIG_ENV_SIZE 0x2000
151 #define CONFIG_ENV_IS_IN_FLASH
152 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
153 #define CONFIG_ENV_SIZE 0x2000
154 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
158 unsigned long get_board_sys_clk(void);
159 unsigned long get_board_ddr_clk(void);
161 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
162 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
165 * These can be toggled for performance analysis, otherwise use default.
167 #define CONFIG_SYS_CACHE_STASHING
168 #define CONFIG_BTB /* toggle branch predition */
169 #define CONFIG_DDR_ECC
170 #ifdef CONFIG_DDR_ECC
171 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
172 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
175 #define CONFIG_ENABLE_36BIT_PHYS
177 #ifdef CONFIG_PHYS_64BIT
178 #define CONFIG_ADDR_MAP
179 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
183 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
185 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
186 #define CONFIG_SYS_MEMTEST_END 0x00400000
187 #define CONFIG_SYS_ALT_MEMTEST
188 #define CONFIG_PANIC_HANG /* do not reset board on panic */
191 * Config the L3 Cache as L3 SRAM
193 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
194 #define CONFIG_SYS_L3_SIZE 256 << 10
195 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
197 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
199 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
200 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
201 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
202 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
204 #ifdef CONFIG_PHYS_64BIT
205 #define CONFIG_SYS_DCSRBAR 0xf0000000
206 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
210 #define CONFIG_ID_EEPROM
211 #define CONFIG_SYS_I2C_EEPROM_NXID
212 #define CONFIG_SYS_EEPROM_BUS_NUM 0
213 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
214 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
215 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
216 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
221 #define CONFIG_VERY_BIG_RAM
222 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
223 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
225 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
226 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
227 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
229 #define CONFIG_DDR_SPD
230 #define CONFIG_SYS_DDR_RAW_TIMING
231 #define CONFIG_SYS_FSL_DDR3
232 #ifndef CONFIG_SPL_BUILD
233 #define CONFIG_FSL_DDR_INTERACTIVE
236 #define CONFIG_SYS_SPD_BUS_NUM 0
237 #define SPD_EEPROM_ADDRESS1 0x51
238 #define SPD_EEPROM_ADDRESS2 0x53
240 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
241 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
246 #define CONFIG_SYS_FLASH_BASE 0xe0000000
247 #ifdef CONFIG_PHYS_64BIT
248 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
250 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
253 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
254 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
256 CSPR_PORT_SIZE_16 | \
259 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
260 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
261 CSPR_PORT_SIZE_16 | \
264 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
265 /* NOR Flash Timing Params */
266 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
267 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
268 FTIM0_NOR_TEADC(0x04) | \
269 FTIM0_NOR_TEAHC(0x20))
270 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
271 FTIM1_NOR_TRAD_NOR(0x1A) |\
272 FTIM1_NOR_TSEQRAD_NOR(0x13))
273 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
274 FTIM2_NOR_TCH(0x0E) | \
275 FTIM2_NOR_TWPH(0x0E) | \
277 #define CONFIG_SYS_NOR_FTIM3 0x0
279 #define CONFIG_SYS_FLASH_QUIET_TEST
280 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
282 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
283 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
284 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
285 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
287 #define CONFIG_SYS_FLASH_EMPTY_INFO
288 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
289 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
291 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
292 #define CONFIG_FSL_QIXIS_V2
293 #define QIXIS_BASE 0xffdf0000
294 #ifdef CONFIG_PHYS_64BIT
295 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
297 #define QIXIS_BASE_PHYS QIXIS_BASE
299 #define QIXIS_LBMAP_SWITCH 0x01
300 #define QIXIS_LBMAP_MASK 0x0f
301 #define QIXIS_LBMAP_SHIFT 0
302 #define QIXIS_LBMAP_DFLTBANK 0x00
303 #define QIXIS_LBMAP_ALTBANK 0x02
304 #define QIXIS_RST_CTL_RESET 0x31
305 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
306 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
307 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
309 #define CONFIG_SYS_CSPR3_EXT (0xf)
310 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
314 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024)
315 #define CONFIG_SYS_CSOR3 0x0
316 /* QIXIS Timing parameters for IFC CS3 */
317 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
318 FTIM0_GPCM_TEADC(0x0e) | \
319 FTIM0_GPCM_TEAHC(0x0e))
320 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
321 FTIM1_GPCM_TRAD(0x1f))
322 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
323 FTIM2_GPCM_TCH(0x8) | \
324 FTIM2_GPCM_TWP(0x1f))
325 #define CONFIG_SYS_CS3_FTIM3 0x0
327 /* NAND Flash on IFC */
328 #define CONFIG_NAND_FSL_IFC
329 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
330 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
331 #define CONFIG_SYS_NAND_BASE 0xff800000
332 #ifdef CONFIG_PHYS_64BIT
333 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
335 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
338 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
339 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
340 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
341 | CSPR_MSEL_NAND /* MSEL = NAND */ \
343 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
345 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
346 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
347 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
348 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
349 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
350 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
351 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
353 #define CONFIG_SYS_NAND_ONFI_DETECTION
355 /* ONFI NAND Flash mode0 Timing Params */
356 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
357 FTIM0_NAND_TWP(0x18) | \
358 FTIM0_NAND_TWCHT(0x07) | \
359 FTIM0_NAND_TWH(0x0a))
360 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
361 FTIM1_NAND_TWBE(0x39) | \
362 FTIM1_NAND_TRR(0x0e) | \
363 FTIM1_NAND_TRP(0x18))
364 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
365 FTIM2_NAND_TREH(0x0a) | \
366 FTIM2_NAND_TWHRE(0x1e))
367 #define CONFIG_SYS_NAND_FTIM3 0x0
369 #define CONFIG_SYS_NAND_DDR_LAW 11
371 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
372 #define CONFIG_SYS_MAX_NAND_DEVICE 1
373 #define CONFIG_CMD_NAND
375 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
377 #if defined(CONFIG_NAND)
378 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
379 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
380 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
381 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
382 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
383 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
384 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
385 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
386 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
387 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
388 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
389 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
390 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
391 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
392 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
393 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
395 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
396 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
397 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
398 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
399 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
400 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
401 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
402 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
403 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
404 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
405 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
406 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
407 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
408 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
409 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
410 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
412 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
413 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
414 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
415 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
416 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
417 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
418 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
419 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
421 #ifdef CONFIG_SPL_BUILD
422 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
424 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
427 #if defined(CONFIG_RAMBOOT_PBL)
428 #define CONFIG_SYS_RAMBOOT
431 #define CONFIG_BOARD_EARLY_INIT_R
432 #define CONFIG_MISC_INIT_R
434 #define CONFIG_HWCONFIG
436 /* define to use L1 as initial stack */
437 #define CONFIG_L1_INIT_RAM
438 #define CONFIG_SYS_INIT_RAM_LOCK
439 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
440 #ifdef CONFIG_PHYS_64BIT
441 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
442 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
443 /* The assembler doesn't like typecast */
444 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
445 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
446 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
448 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
449 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
450 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
452 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
454 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
455 GENERATED_GBL_DATA_SIZE)
456 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
458 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
459 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
461 /* Serial Port - controlled on board with jumper J8
465 #define CONFIG_CONS_INDEX 1
466 #define CONFIG_SYS_NS16550_SERIAL
467 #define CONFIG_SYS_NS16550_REG_SIZE 1
468 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
470 #define CONFIG_SYS_BAUDRATE_TABLE \
471 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
473 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
474 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
475 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
476 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
479 #define CONFIG_SYS_I2C
480 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
481 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
482 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
483 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
484 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
485 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
486 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
492 #define CONFIG_RTC_DS3231 1
493 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
498 #ifdef CONFIG_SYS_SRIO
500 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
501 #ifdef CONFIG_PHYS_64BIT
502 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
504 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
506 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
510 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
511 #ifdef CONFIG_PHYS_64BIT
512 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
514 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
516 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
521 * for slave u-boot IMAGE instored in master memory space,
522 * PHYS must be aligned based on the SIZE
524 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
525 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
526 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
527 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
529 * for slave UCODE and ENV instored in master memory space,
530 * PHYS must be aligned based on the SIZE
532 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
533 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
534 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
536 /* slave core release by master*/
537 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
538 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
541 * SRIO_PCIE_BOOT - SLAVE
543 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
544 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
545 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
546 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
550 * eSPI - Enhanced SPI
552 #define CONFIG_SF_DEFAULT_SPEED 10000000
553 #define CONFIG_SF_DEFAULT_MODE 0
558 #ifdef CONFIG_PHYS_64BIT
559 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull
561 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000
566 * Memory space is mapped 1-1, but I/O space must start from 0.
569 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
570 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
571 #ifdef CONFIG_PHYS_64BIT
572 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
573 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
575 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
576 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
578 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
579 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
580 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
581 #ifdef CONFIG_PHYS_64BIT
582 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
584 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
586 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
589 #ifndef CONFIG_NOBQFMAN
590 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
591 #define CONFIG_SYS_BMAN_NUM_PORTALS 25
592 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
593 #ifdef CONFIG_PHYS_64BIT
594 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
596 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
598 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
599 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
600 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
601 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
602 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
603 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
604 CONFIG_SYS_BMAN_CENA_SIZE)
605 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
606 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
607 #define CONFIG_SYS_QMAN_NUM_PORTALS 25
608 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
609 #ifdef CONFIG_PHYS_64BIT
610 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
612 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
614 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
615 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
616 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
617 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
618 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
619 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
620 CONFIG_SYS_QMAN_CENA_SIZE)
621 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
622 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
624 #define CONFIG_SYS_DPAA_FMAN
626 #define CONFIG_SYS_DPAA_RMAN
628 /* Default address of microcode for the Linux Fman driver */
629 #if defined(CONFIG_SPIFLASH)
631 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
632 * env, so we got 0x110000.
634 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
635 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
636 #elif defined(CONFIG_SDCARD)
638 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
639 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
640 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
642 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
643 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
644 #elif defined(CONFIG_NAND)
645 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
646 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
647 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
649 * Slave has no ucode locally, it can fetch this from remote. When implementing
650 * in two corenet boards, slave's ucode could be stored in master's memory
651 * space, the address can be mapped from slave TLB->slave LAW->
652 * slave SRIO or PCIE outbound window->master inbound window->
653 * master LAW->the ucode address in master's memory space.
655 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
656 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
658 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
659 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
661 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
662 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
663 #endif /* CONFIG_NOBQFMAN */
665 #ifdef CONFIG_SYS_DPAA_FMAN
666 #define CONFIG_FMAN_ENET
667 #define CONFIG_PHYLIB_10G
668 #define CONFIG_PHY_VITESSE
669 #define CONFIG_PHY_TERANETICS
670 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
671 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
672 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
673 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
677 #define CONFIG_PCI_INDIRECT_BRIDGE
679 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
680 #define CONFIG_DOS_PARTITION
681 #endif /* CONFIG_PCI */
683 #ifdef CONFIG_FMAN_ENET
684 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
685 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
687 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
688 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
689 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/
691 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
692 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
693 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
694 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
696 #define CONFIG_MII /* MII PHY management */
697 #define CONFIG_ETHPRIME "FM1@DTSEC1"
698 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
701 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
706 #define CONFIG_LOADS_ECHO /* echo on for serial download */
707 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
710 * Command line configuration.
712 #define CONFIG_CMD_DATE
713 #define CONFIG_CMD_EEPROM
714 #define CONFIG_CMD_ERRATA
715 #define CONFIG_CMD_IRQ
716 #define CONFIG_CMD_REGINFO
719 #define CONFIG_CMD_PCI
722 /* Hash command with SHA acceleration supported in hardware */
723 #ifdef CONFIG_FSL_CAAM
724 #define CONFIG_CMD_HASH
725 #define CONFIG_SHA_HW_ACCEL
731 #define CONFIG_HAS_FSL_DR_USB
733 #ifdef CONFIG_HAS_FSL_DR_USB
734 #define CONFIG_USB_EHCI
736 #ifdef CONFIG_USB_EHCI
737 #define CONFIG_USB_EHCI_FSL
738 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
743 * Miscellaneous configurable options
745 #define CONFIG_SYS_LONGHELP /* undef to save memory */
746 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
747 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
748 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
749 #ifdef CONFIG_CMD_KGDB
750 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
752 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
754 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
755 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
756 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
759 * For booting Linux, the board info and command line data
760 * have to be in the first 64 MB of memory, since this is
761 * the maximum mapped by the Linux kernel during initialization.
763 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
764 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
766 #ifdef CONFIG_CMD_KGDB
767 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
771 * Environment Configuration
773 #define CONFIG_ROOTPATH "/opt/nfsroot"
774 #define CONFIG_BOOTFILE "uImage"
775 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
777 /* default location for tftp and bootm */
778 #define CONFIG_LOADADDR 1000000
781 #define CONFIG_BAUDRATE 115200
783 #define __USB_PHY_TYPE ulpi
785 #ifdef CONFIG_ARCH_B4860
786 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \
787 "bank_intlv=cs0_cs1;" \
790 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
793 #define CONFIG_EXTRA_ENV_SETTINGS \
795 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
797 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
798 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
799 "tftpflash=tftpboot $loadaddr $uboot && " \
800 "protect off $ubootaddr +$filesize && " \
801 "erase $ubootaddr +$filesize && " \
802 "cp.b $loadaddr $ubootaddr $filesize && " \
803 "protect on $ubootaddr +$filesize && " \
804 "cmp.b $loadaddr $ubootaddr $filesize\0" \
805 "consoledev=ttyS0\0" \
806 "ramdiskaddr=2000000\0" \
807 "ramdiskfile=b4860qds/ramdisk.uboot\0" \
808 "fdtaddr=1e00000\0" \
809 "fdtfile=b4860qds/b4860qds.dtb\0" \
812 /* For emulation this causes u-boot to jump to the start of the proof point
813 app code automatically */
814 #define CONFIG_PROOF_POINTS \
815 "setenv bootargs root=/dev/$bdev rw " \
816 "console=$consoledev,$baudrate $othbootargs;" \
817 "cpu 1 release 0x29000000 - - -;" \
818 "cpu 2 release 0x29000000 - - -;" \
819 "cpu 3 release 0x29000000 - - -;" \
820 "cpu 4 release 0x29000000 - - -;" \
821 "cpu 5 release 0x29000000 - - -;" \
822 "cpu 6 release 0x29000000 - - -;" \
823 "cpu 7 release 0x29000000 - - -;" \
826 #define CONFIG_HVBOOT \
827 "setenv bootargs config-addr=0x60000000; " \
828 "bootm 0x01000000 - 0x00f00000"
831 "setenv bootargs root=/dev/$bdev rw " \
832 "console=$consoledev,$baudrate $othbootargs;" \
833 "cpu 1 release 0x01000000 - - -;" \
834 "cpu 2 release 0x01000000 - - -;" \
835 "cpu 3 release 0x01000000 - - -;" \
836 "cpu 4 release 0x01000000 - - -;" \
837 "cpu 5 release 0x01000000 - - -;" \
838 "cpu 6 release 0x01000000 - - -;" \
839 "cpu 7 release 0x01000000 - - -;" \
842 #define CONFIG_LINUX \
843 "setenv bootargs root=/dev/ram rw " \
844 "console=$consoledev,$baudrate $othbootargs;" \
845 "setenv ramdiskaddr 0x02000000;" \
846 "setenv fdtaddr 0x01e00000;" \
847 "setenv loadaddr 0x1000000;" \
848 "bootm $loadaddr $ramdiskaddr $fdtaddr"
850 #define CONFIG_HDBOOT \
851 "setenv bootargs root=/dev/$bdev rw " \
852 "console=$consoledev,$baudrate $othbootargs;" \
853 "tftp $loadaddr $bootfile;" \
854 "tftp $fdtaddr $fdtfile;" \
855 "bootm $loadaddr - $fdtaddr"
857 #define CONFIG_NFSBOOTCOMMAND \
858 "setenv bootargs root=/dev/nfs rw " \
859 "nfsroot=$serverip:$rootpath " \
860 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
861 "console=$consoledev,$baudrate $othbootargs;" \
862 "tftp $loadaddr $bootfile;" \
863 "tftp $fdtaddr $fdtfile;" \
864 "bootm $loadaddr - $fdtaddr"
866 #define CONFIG_RAMBOOTCOMMAND \
867 "setenv bootargs root=/dev/ram rw " \
868 "console=$consoledev,$baudrate $othbootargs;" \
869 "tftp $ramdiskaddr $ramdiskfile;" \
870 "tftp $loadaddr $bootfile;" \
871 "tftp $fdtaddr $fdtfile;" \
872 "bootm $loadaddr $ramdiskaddr $fdtaddr"
874 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
876 #include <asm/fsl_secure_boot.h>
878 #endif /* __CONFIG_H */