4 * (C) Copyright 2003-2005
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * (C) Copyright 2004-2005
8 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
11 * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de.
14 * 1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
16 * See file CREDITS for list of people who contributed to this
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
39 * High Level Configuration Options
41 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
42 #define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
43 #define CONFIG_TQM5200 1 /* ... on a TQM5200 module */
45 #define CONFIG_BC3450 1 /* ... on a BC3450 mainboard */
46 #define CONFIG_BC3450_PS2 1 /* + a PS/2 converter onboard */
47 #define CONFIG_BC3450_IDE 1 /* + IDE drives (Compact Flash) */
48 #define CONFIG_BC3450_USB 1 /* + USB support */
49 # define CONFIG_FAT 1 /* + FAT support */
50 # define CONFIG_EXT2 1 /* + EXT2 support */
51 #undef CONFIG_BC3450_BUZZER /* + Buzzer onboard */
52 #undef CONFIG_BC3450_CAN /* + CAN transceiver */
53 #undef CONFIG_BC3450_DS1340 /* + a RTC DS1340 onboard */
54 #undef CONFIG_BC3450_DS3231 /* + a RTC DS3231 onboard tbd */
55 #undef CONFIG_BC3450_AC97 /* + AC97 on PSC2, tbd */
56 #define CONFIG_BC3450_FP 1 /* + enable FP O/P */
57 #undef CONFIG_BC3450_CRT /* + enable CRT O/P (Debug only!) */
59 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
61 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
62 #define BOOTFLAG_WARM 0x02 /* Software reboot */
65 * Serial console configuration
67 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
68 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
69 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
74 #ifdef CONFIG_BC3450_PS2
75 # define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
76 # define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
77 # define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
78 # define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
79 # define CONFIG_BOARD_EARLY_INIT_R
80 #endif /* CONFIG_BC3450_PS2 */
84 * 0x40000000 - 0x4fffffff - PCI Memory
85 * 0x50000000 - 0x50ffffff - PCI IO Space
88 # define CONFIG_PCI_PNP 1
89 /* #define CONFIG_PCI_SCAN_SHOW 1 */
91 #define CONFIG_PCI_MEM_BUS 0x40000000
92 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
93 #define CONFIG_PCI_MEM_SIZE 0x10000000
95 #define CONFIG_PCI_IO_BUS 0x50000000
96 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
97 #define CONFIG_PCI_IO_SIZE 0x01000000
99 #define CONFIG_NET_MULTI 1
100 /*#define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled */
101 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
102 #define CONFIG_NS8382X 1
107 # define CONFIG_VIDEO
108 # define CONFIG_VIDEO_SM501
109 # define CONFIG_VIDEO_SM501_32BPP
110 # define CONFIG_CFB_CONSOLE
111 # define CONFIG_VIDEO_LOGO
112 # define CONFIG_VGA_AS_SINGLE_DEVICE
113 # define CONFIG_CONSOLE_EXTRA_INFO /* display Board/Device-Infos */
114 # define CONFIG_VIDEO_SW_CURSOR
115 # define CONFIG_SPLASH_SCREEN
116 # define CFG_CONSOLE_IS_IN_ENV
121 #define CONFIG_MAC_PARTITION
122 #define CONFIG_DOS_PARTITION
123 #define CONFIG_ISO_PARTITION
128 #ifdef CONFIG_BC3450_USB
129 # define CONFIG_USB_OHCI
130 # define CONFIG_USB_STORAGE
131 #endif /* CONFIG_BC3450_USB */
136 #define CONFIG_POST (CFG_POST_MEMORY | \
141 /* preserve space for the post_word at end of on-chip SRAM */
142 # define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
143 #endif /* CONFIG_POST */
147 * Command line configuration.
149 #include <config_cmd_default.h>
151 #define CONFIG_CMD_ASKENV
152 #define CONFIG_CMD_DATE
153 #define CONFIG_CMD_DHCP
154 #define CONFIG_CMD_ECHO
155 #define CONFIG_CMD_EEPROM
156 #define CONFIG_CMD_I2C
157 #define CONFIG_CMD_JFFS2
158 #define CONFIG_CMD_MII
159 #define CONFIG_CMD_NFS
160 #define CONFIG_CMD_PING
161 #define CONFIG_CMD_REGINFO
162 #define CONFIG_CMD_SNTP
163 #define CONFIG_CMD_BSP
166 #define CONFIG_CMD_BMP
169 #ifdef CONFIG_BC3450_IDE
170 #define CONFIG_CMD_IDE
173 #if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB)
175 #define CONFIG_CMD_FAT
179 #define CONFIG_CMD_EXT2
183 #ifdef CONFIG_BC3450_USB
184 #define CONFIG_CMD_USB
188 #define CONFIG_CMD_PCI
192 #define CONFIG_CMD_DIAG
196 #define CONFIG_TIMESTAMP /* display image timestamps */
198 #if (TEXT_BASE == 0xFC000000) /* Boot low */
199 # define CFG_LOWBOOT 1
205 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
206 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
208 #define CONFIG_PREBOOT "echo;" \
209 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
212 #undef CONFIG_BOOTARGS
214 #define CONFIG_EXTRA_ENV_SETTINGS \
216 "ipaddr=192.168.1.10\0" \
217 "serverip=192.168.1.3\0" \
218 "netmask=255.255.255.0\0" \
219 "hostname=bc3450\0" \
220 "rootpath=/opt/eldk/ppc_6xx\0" \
221 "kernel_addr=fc0a0000\0" \
222 "ramdisk_addr=fc1c0000\0" \
223 "ramargs=setenv bootargs root=/dev/ram rw\0" \
224 "nfsargs=setenv bootargs root=/dev/nfs rw " \
225 "nfsroot=$(serverip):$(rootpath)\0" \
226 "ideargs=setenv bootargs root=/dev/hda2 ro\0" \
227 "addip=setenv bootargs $(bootargs) " \
228 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
229 ":$(hostname):$(netdev):off panic=1\0" \
230 "addcons=setenv bootargs $(bootargs) " \
231 "console=ttyS0,$(baudrate) console=tty0\0" \
232 "flash_self=run ramargs addip addcons;" \
233 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
234 "flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0" \
235 "net_nfs=tftp 200000 $(bootfile); " \
236 "run nfsargs addip addcons; bootm\0" \
237 "ide_nfs=run nfsargs addip addcons; " \
238 "disk 200000 0:1; bootm\0" \
239 "ide_ide=run ideargs addip addcons; " \
240 "disk 200000 0:1; bootm\0" \
241 "usb_self=run usbload; run ramargs addip addcons; " \
242 "bootm 200000 400000\0" \
243 "usbload=usb reset; usb scan; usbboot 200000 0:1; " \
244 "usbboot 400000 0:2\0" \
245 "bootfile=uImage\0" \
246 "load=tftp 200000 $(u-boot)\0" \
247 "u-boot=u-boot.bin\0" \
248 "update=protect off FC000000 FC05FFFF;" \
249 "erase FC000000 FC05FFFF;" \
250 "cp.b 200000 FC000000 $(filesize);" \
251 "protect on FC000000 FC05FFFF\0" \
254 #define CONFIG_BOOTCOMMAND "run flash_self"
257 * IPB Bus clocking configuration.
259 #define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
262 * PCI Bus clocking configuration
264 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
265 * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
266 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
268 #if defined(CFG_IPBCLK_EQUALS_XLBCLK)
269 # define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
275 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
276 #define CFG_I2C_MODULE 2 /* Select I2C module #2 */
279 * I2C clock frequency
281 * Please notice, that the resulting clock frequency could differ from the
282 * configured value. This is because the I2C clock is derived from system
283 * clock over a frequency divider with only a few divider values. U-boot
284 * calculates the best approximation for CFG_I2C_SPEED. However the calculated
285 * approximation allways lies below the configured value, never above.
287 #define CFG_I2C_SPEED 100000 /* 100 kHz */
288 #define CFG_I2C_SLAVE 0x7F
291 * EEPROM configuration for I²C EEPROM M24C32
292 * M24C64 should work also. For other EEPROMs config should be verified.
294 * The TQM5200 module may hold an EEPROM at address 0x50.
296 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x (TQM) */
297 #define CFG_I2C_EEPROM_ADDR_LEN 2
298 #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
299 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
304 #if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
305 # define CONFIG_RTC_M41T11 1
306 # define CFG_I2C_RTC_ADDR 0x68
308 # define CONFIG_RTC_MPC5200 1 /* use MPC5200 internal RTC */
309 # define CONFIG_BOARD_EARLY_INIT_R
313 * Flash configuration
315 #define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
317 /* use CFI flash driver if no module variant is spezified */
318 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
319 #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
320 #define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
321 #define CFG_FLASH_EMPTY_INFO
322 #define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
323 #define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
324 #undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
326 #if !defined(CFG_LOWBOOT)
327 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
328 #else /* CFG_LOWBOOT */
329 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
330 #endif /* CFG_LOWBOOT */
331 #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
333 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
334 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
336 /* Dynamic MTD partition support */
337 #define CONFIG_JFFS2_CMDLINE
338 #define MTDIDS_DEFAULT "nor0=TQM5200-0"
339 #define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
347 * Environment settings
349 #define CFG_ENV_IS_IN_FLASH 1
350 #define CFG_ENV_SIZE 0x10000
351 #define CFG_ENV_SECT_SIZE 0x20000
352 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
353 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
358 #define CFG_MBAR 0xF0000000
359 #define CFG_SDRAM_BASE 0x00000000
360 #define CFG_DEFAULT_MBAR 0x80000000
362 /* Use ON-Chip SRAM until RAM will be available */
363 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
365 /* preserve space for the post_word at end of on-chip SRAM */
366 # define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
368 # define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
369 #endif /*CONFIG_POST*/
371 #define CFG_GBL_DATA_SIZE 128 /* Bytes reserved for initial data */
372 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
373 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
375 #define CFG_MONITOR_BASE TEXT_BASE
376 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
377 # define CFG_RAMBOOT 1
380 #define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
381 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
382 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
385 * Ethernet configuration
387 * Define CONFIG_FEC10MBIT to force FEC at 10MBIT
389 #define CONFIG_MPC5xxx_FEC 1
390 #undef CONFIG_FEC_10MBIT
391 #define CONFIG_PHY_ADDR 0x00
394 * GPIO configuration on BC3450
396 * PSC1: UART1 (Service-UART) [0x xxxxxxx4]
397 * PSC2: UART2 [0x xxxxxx4x]
398 * or: AC/97 if CONFIG_BC3450_AC97 [0x xxxxxx2x]
399 * PSC3: USB2 [0x xxxxx1xx]
400 * USB: UART4(ext.)/UART5(int.) [0x xxxx2xxx]
402 * CONFIG_USB_CONFIG which is
403 * used by usb_ohci.c to set
405 * Eth: 10/100Mbit Ethernet [0x xxx0xxxx]
406 * (this is reset to '5'
407 * in FEC driver: fec.c)
408 * PSC6: UART6 (int. to PS/2 contr.) [0x xx5xxxxx]
409 * ATA/CS: ??? [0x x1xxxxxx]
410 * FIXME! UM Fig 2-10 suggests [0x x0xxxxxx]
411 * CS1: Use Pin gpio_wkup_6 as second
412 * SDRAM chip select (mem_cs1)
414 * I2C: CAN1 / I²C2 [0x bxxxxxxx]
416 #ifdef CONFIG_BC3450_AC97
417 # define CFG_GPS_PORT_CONFIG 0xb1502124
418 #else /* PSC2=UART2 */
419 # define CFG_GPS_PORT_CONFIG 0xb1502144
423 * Miscellaneous configurable options
425 #define CFG_LONGHELP /* undef to save memory */
426 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
427 #if defined(CONFIG_CMD_KGDB)
428 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
430 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
432 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
433 #define CFG_MAXARGS 16 /* max no of command args */
434 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Arg. Buffer Size */
436 #define CFG_ALT_MEMTEST /* Enable an alternative, */
437 /* more extensive mem test */
439 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
440 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
442 #define CFG_LOAD_ADDR 0x100000 /* default load address */
444 #define CFG_HZ 1000 /* dec freq: 1ms ticks */
446 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
447 #if defined(CONFIG_CMD_KGDB)
448 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
452 * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
453 * which is normally part of the default commands (CFV_CMD_DFL)
458 * Various low-level settings
460 #if defined(CONFIG_MPC5200)
461 # define CFG_HID0_INIT HID0_ICE | HID0_ICFI
462 # define CFG_HID0_FINAL HID0_ICE
464 # define CFG_HID0_INIT 0
465 # define CFG_HID0_FINAL 0
468 #define CFG_BOOTCS_START CFG_FLASH_BASE
469 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
470 #ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
471 # define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
473 # define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
475 #define CFG_CS0_START CFG_FLASH_BASE
476 #define CFG_CS0_SIZE CFG_FLASH_SIZE
478 /* automatic configuration of chip selects */
479 #ifdef CONFIG_TQM5200
480 # define CONFIG_LAST_STAGE_INIT
481 #endif /* CONFIG_TQM5200 */
484 * SRAM - Do not map below 2 GB in address space, because this area is used
485 * for SDRAM autosizing.
487 #ifdef CONFIG_TQM5200
488 # define CFG_CS2_START 0xE5000000
489 # define CFG_CS2_SIZE 0x100000 /* 1 MByte */
490 # define CFG_CS2_CFG 0x0004D930
491 #endif /* CONFIG_TQM5200 */
494 * Grafic controller - Do not map below 2 GB in address space, because this
495 * area is used for SDRAM autosizing.
497 #ifdef CONFIG_TQM5200
498 # define SM501_FB_BASE 0xE0000000
499 # define CFG_CS1_START (SM501_FB_BASE)
500 # define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
501 # define CFG_CS1_CFG 0x8F48FF70
502 # define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
503 #endif /* CONFIG_TQM5200 */
505 #define CFG_CS_BURST 0x00000000
506 #define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for */
507 /* flash and SM501 */
509 #define CFG_RESET_ADDRESS 0xff000000
514 #define CONFIG_USB_CLOCK 0x0001BBBB
515 #define CONFIG_USB_CONFIG 0x00002000 /* we're using Port 2 */
518 * IDE/ATA stuff Supports IDE harddisk
520 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
522 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
523 #undef CONFIG_IDE_LED /* LED for ide not supported */
525 #define CONFIG_IDE_RESET /* reset for ide supported */
526 #define CONFIG_IDE_PREINIT
528 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
529 #define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
531 #define CFG_ATA_IDE0_OFFSET 0x0000
533 #define CFG_ATA_BASE_ADDR MPC5XXX_ATA
535 /* Offset for data I/O */
536 #define CFG_ATA_DATA_OFFSET (0x0060)
538 /* Offset for normal register accesses */
539 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
541 /* Offset for alternate registers */
542 #define CFG_ATA_ALT_OFFSET (0x005C)
544 /* Interval between registers */
545 #define CFG_ATA_STRIDE 4
547 #endif /* __CONFIG_H */