2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * BSC9131 RDB board configuration file
14 #define CONFIG_NAND_FSL_IFC
16 #ifdef CONFIG_SPIFLASH
17 #define CONFIG_RAMBOOT_SPIFLASH
18 #define CONFIG_SYS_RAMBOOT
19 #define CONFIG_SYS_EXTRA_ENV_RELOC
20 #define CONFIG_SYS_TEXT_BASE 0x11000000
21 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
25 #define CONFIG_SPL_INIT_MINIMAL
26 #define CONFIG_SPL_NAND_BOOT
27 #define CONFIG_SPL_FLUSH_IMAGE
28 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
30 #define CONFIG_SYS_TEXT_BASE 0x00201000
31 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000
32 #define CONFIG_SPL_MAX_SIZE 8192
33 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
34 #define CONFIG_SPL_RELOC_STACK 0x00100000
35 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
36 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
37 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
38 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
39 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
42 #ifdef CONFIG_SPL_BUILD
43 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
45 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
48 /* High Level Configuration Options */
50 #define CONFIG_TSEC_ENET
51 #define CONFIG_ENV_OVERWRITE
53 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */
54 #if defined(CONFIG_SYS_CLK_100)
55 #define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */
57 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */
60 #define CONFIG_HWCONFIG
62 * These can be toggled for performance analysis, otherwise use default.
64 #define CONFIG_L2_CACHE /* toggle L2 cache */
65 #define CONFIG_BTB /* enable branch predition */
67 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
68 #define CONFIG_SYS_MEMTEST_END 0x01ffffff
71 #undef CONFIG_SYS_DDR_RAW_TIMING
73 #define CONFIG_SYS_SPD_BUS_NUM 0
74 #define SPD_EEPROM_ADDRESS 0x52 /* I2C access */
76 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
79 extern unsigned long get_sdram_size(void);
81 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
82 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
83 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
85 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
86 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
88 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
89 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
90 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
92 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
93 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
94 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
95 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
97 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
98 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
99 #define CONFIG_SYS_DDR_RCW_1 0x00000000
100 #define CONFIG_SYS_DDR_RCW_2 0x00000000
101 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
102 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
103 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
104 #define CONFIG_SYS_DDR_TIMING_5 0x02401400
106 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
107 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
108 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
109 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf
110 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
111 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
112 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
113 #define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
114 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
117 * Base addresses -- Note these are effective addresses where the
118 * actual resources get mapped (not physical addresses)
120 /* relocated CCSRBAR */
121 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
122 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
124 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
125 /* CONFIG_SYS_IMMR */
127 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
128 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
133 * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable
134 * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M
135 * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M
136 * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
137 * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K
138 * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K
139 * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
140 * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
141 * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
142 * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M
150 /* NAND Flash on IFC */
151 #define CONFIG_SYS_NAND_BASE 0xff800000
152 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
154 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
155 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \
156 | CSPR_MSEL_NAND /* MSEL = NAND */ \
158 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
160 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
161 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
162 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
163 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
164 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
165 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
166 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
168 /* NAND Flash Timing Params */
169 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
170 | FTIM0_NAND_TWP(0x05) \
171 | FTIM0_NAND_TWCHT(0x02) \
172 | FTIM0_NAND_TWH(0x04))
173 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \
174 | FTIM1_NAND_TWBE(0x1E) \
175 | FTIM1_NAND_TRR(0x07) \
176 | FTIM1_NAND_TRP(0x05))
177 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
178 | FTIM2_NAND_TREH(0x04) \
179 | FTIM2_NAND_TWHRE(0x11))
180 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
182 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
183 #define CONFIG_SYS_MAX_NAND_DEVICE 1
184 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
186 #define CONFIG_SYS_NAND_DDR_LAW 11
188 /* Set up IFC registers for boot location NAND */
189 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
190 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
191 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
192 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
193 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
194 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
195 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
197 #define CONFIG_SYS_INIT_RAM_LOCK
198 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
199 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* End of used area in RAM */
201 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
202 - GENERATED_GBL_DATA_SIZE)
203 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
205 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
206 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
209 #define CONFIG_CONS_INDEX 1
210 #undef CONFIG_SERIAL_SOFTWARE_FIFO
211 #define CONFIG_SYS_NS16550_SERIAL
212 #define CONFIG_SYS_NS16550_REG_SIZE 1
213 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
214 #ifdef CONFIG_SPL_BUILD
215 #define CONFIG_NS16550_MIN_FUNCTIONS
218 #define CONFIG_SYS_BAUDRATE_TABLE \
219 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
221 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
223 #define CONFIG_SYS_I2C
224 #define CONFIG_SYS_I2C_FSL
225 #define CONFIG_SYS_FSL_I2C_SPEED 400000
226 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
227 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
230 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
231 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
232 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
234 /* eSPI - Enhanced SPI */
235 #ifdef CONFIG_FSL_ESPI
236 #define CONFIG_SF_DEFAULT_SPEED 10000000
237 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
240 #if defined(CONFIG_TSEC_ENET)
242 #define CONFIG_MII /* MII PHY management */
243 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
244 #define CONFIG_TSEC1 1
245 #define CONFIG_TSEC1_NAME "eTSEC1"
246 #define CONFIG_TSEC2 1
247 #define CONFIG_TSEC2_NAME "eTSEC2"
249 #define TSEC1_PHY_ADDR 0
250 #define TSEC2_PHY_ADDR 3
252 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
253 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
255 #define TSEC1_PHYIDX 0
257 #define TSEC2_PHYIDX 0
259 #define CONFIG_ETHPRIME "eTSEC1"
261 #endif /* CONFIG_TSEC_ENET */
266 #if defined(CONFIG_RAMBOOT_SPIFLASH)
267 #define CONFIG_ENV_SPI_BUS 0
268 #define CONFIG_ENV_SPI_CS 0
269 #define CONFIG_ENV_SPI_MAX_HZ 10000000
270 #define CONFIG_ENV_SPI_MODE 0
271 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
272 #define CONFIG_ENV_SECT_SIZE 0x10000
273 #define CONFIG_ENV_SIZE 0x2000
274 #elif defined(CONFIG_NAND)
275 #define CONFIG_SYS_EXTRA_ENV_RELOC
276 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
277 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
278 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
279 #elif defined(CONFIG_SYS_RAMBOOT)
280 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
281 #define CONFIG_ENV_SIZE 0x2000
284 #define CONFIG_LOADS_ECHO /* echo on for serial download */
285 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
288 * Miscellaneous configurable options
290 #define CONFIG_SYS_LONGHELP /* undef to save memory */
291 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
292 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
293 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
295 #if defined(CONFIG_CMD_KGDB)
296 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
298 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
300 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
301 /* Print Buffer Size */
302 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
303 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
306 * For booting Linux, the board info and command line data
307 * have to be in the first 64 MB of memory, since this is
308 * the maximum mapped by the Linux kernel during initialization.
310 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
311 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
313 #if defined(CONFIG_CMD_KGDB)
314 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
317 #ifdef CONFIG_USB_EHCI_HCD
318 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
319 #define CONFIG_USB_EHCI_FSL
320 #define CONFIG_HAS_FSL_DR_USB
324 * Dynamic MTD Partition support with mtdparts
326 #define CONFIG_MTD_DEVICE
327 #define CONFIG_MTD_PARTITIONS
328 #define MTDIDS_DEFAULT "nand0=ff800000.flash,"
329 #define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:1m(uboot)," \
330 "8m(kernel),512k(dtb),-(fs)"
333 * Environment Configuration
336 #if defined(CONFIG_TSEC_ENET)
337 #define CONFIG_HAS_ETH0
340 #define CONFIG_HOSTNAME BSC9131rdb
341 #define CONFIG_ROOTPATH "/opt/nfsroot"
342 #define CONFIG_BOOTFILE "uImage"
343 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
345 #define CONFIG_EXTRA_ENV_SETTINGS \
347 "uboot=" CONFIG_UBOOTPATH "\0" \
348 "loadaddr=1000000\0" \
349 "bootfile=uImage\0" \
350 "consoledev=ttyS0\0" \
351 "ramdiskaddr=2000000\0" \
352 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
353 "fdtaddr=1e00000\0" \
354 "fdtfile=bsc9131rdb.dtb\0" \
356 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
357 "bootm_size=0x37000000\0" \
358 "othbootargs=ramdisk_size=600000 " \
359 "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
360 "usbext2boot=setenv bootargs root=/dev/ram rw " \
361 "console=$consoledev,$baudrate $othbootargs; " \
363 "ext2load usb 0:4 $loadaddr $bootfile;" \
364 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
365 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
366 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
368 #define CONFIG_RAMBOOTCOMMAND \
369 "setenv bootargs root=/dev/ram rw " \
370 "console=$consoledev,$baudrate $othbootargs; " \
371 "tftp $ramdiskaddr $ramdiskfile;" \
372 "tftp $loadaddr $bootfile;" \
373 "tftp $fdtaddr $fdtfile;" \
374 "bootm $loadaddr $ramdiskaddr $fdtaddr"
376 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
378 #endif /* __CONFIG_H */