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[u-boot] / include / configs / BSC9131RDB.h
1 /*
2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 /*
8  * BSC9131 RDB board configuration file
9  */
10
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 #define CONFIG_DISPLAY_BOARDINFO
15
16 #ifdef CONFIG_BSC9131RDB
17 #define CONFIG_BSC9131
18 #define CONFIG_NAND_FSL_IFC
19 #endif
20
21 #ifdef CONFIG_SPIFLASH
22 #define CONFIG_RAMBOOT_SPIFLASH
23 #define CONFIG_SYS_RAMBOOT
24 #define CONFIG_SYS_EXTRA_ENV_RELOC
25 #define CONFIG_SYS_TEXT_BASE            0x11000000
26 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
27 #endif
28
29 #ifdef CONFIG_NAND
30 #define CONFIG_SPL_INIT_MINIMAL
31 #define CONFIG_SPL_SERIAL_SUPPORT
32 #define CONFIG_SPL_NAND_SUPPORT
33 #define CONFIG_SPL_NAND_BOOT
34 #define CONFIG_SPL_FLUSH_IMAGE
35 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
36
37 #define CONFIG_SYS_TEXT_BASE            0x00201000
38 #define CONFIG_SPL_TEXT_BASE            0xFFFFE000
39 #define CONFIG_SPL_MAX_SIZE             8192
40 #define CONFIG_SPL_RELOC_TEXT_BASE      0x00100000
41 #define CONFIG_SPL_RELOC_STACK          0x00100000
42 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
43 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
44 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
45 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0
46 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
47 #endif
48
49 #ifdef CONFIG_SPL_BUILD
50 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
51 #else
52 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
53 #endif
54
55 /* High Level Configuration Options */
56 #define CONFIG_BOOKE                    /* BOOKE */
57 #define CONFIG_E500                     /* BOOKE e500 family */
58 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
59 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
60
61 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
62 #define CONFIG_TSEC_ENET
63 #define CONFIG_ENV_OVERWRITE
64
65 #define CONFIG_DDR_CLK_FREQ     66666666 /* DDRCLK on 9131 RDB */
66 #if defined(CONFIG_SYS_CLK_100)
67 #define CONFIG_SYS_CLK_FREQ    100000000 /* SYSCLK for 9131 RDB */
68 #else
69 #define CONFIG_SYS_CLK_FREQ     66666666 /* SYSCLK for 9131 RDB */
70 #endif
71
72 #define CONFIG_HWCONFIG
73 /*
74  * These can be toggled for performance analysis, otherwise use default.
75  */
76 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
77 #define CONFIG_BTB                      /* enable branch predition */
78
79 #define CONFIG_SYS_MEMTEST_START        0x01000000      /* memtest works on */
80 #define CONFIG_SYS_MEMTEST_END          0x01ffffff
81
82 /* DDR Setup */
83 #define CONFIG_SYS_FSL_DDR3
84 #undef CONFIG_SYS_DDR_RAW_TIMING
85 #undef CONFIG_DDR_SPD
86 #define CONFIG_SYS_SPD_BUS_NUM          0
87 #define SPD_EEPROM_ADDRESS              0x52 /* I2C access */
88
89 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
90
91 #ifndef __ASSEMBLY__
92 extern unsigned long get_sdram_size(void);
93 #endif
94 #define CONFIG_SYS_SDRAM_SIZE           get_sdram_size() /* DDR size */
95 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
96 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
97
98 #define CONFIG_NUM_DDR_CONTROLLERS      1
99 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
100 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
101
102 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
103 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
104 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
105
106 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
107 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
108 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
109 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
110
111 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
112 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
113 #define CONFIG_SYS_DDR_RCW_1            0x00000000
114 #define CONFIG_SYS_DDR_RCW_2            0x00000000
115 #define CONFIG_SYS_DDR_CONTROL          0xC70C0000      /* Type = DDR3  */
116 #define CONFIG_SYS_DDR_CONTROL_2        0x24401000
117 #define CONFIG_SYS_DDR_TIMING_4         0x00000001
118 #define CONFIG_SYS_DDR_TIMING_5         0x02401400
119
120 #define CONFIG_SYS_DDR_TIMING_3_800             0x00030000
121 #define CONFIG_SYS_DDR_TIMING_0_800             0x00110104
122 #define CONFIG_SYS_DDR_TIMING_1_800             0x6f6b8644
123 #define CONFIG_SYS_DDR_TIMING_2_800             0x0fa888cf
124 #define CONFIG_SYS_DDR_CLK_CTRL_800             0x03000000
125 #define CONFIG_SYS_DDR_MODE_1_800               0x00441420
126 #define CONFIG_SYS_DDR_MODE_2_800               0x8000c000
127 #define CONFIG_SYS_DDR_INTERVAL_800             0x0c300100
128 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800        0x8675f608
129
130 /*
131  * Base addresses -- Note these are effective addresses where the
132  * actual resources get mapped (not physical addresses)
133  */
134 /* relocated CCSRBAR */
135 #define CONFIG_SYS_CCSRBAR      CONFIG_SYS_CCSRBAR_DEFAULT
136 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR_DEFAULT
137
138 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses */
139                                                         /* CONFIG_SYS_IMMR */
140 /* DSP CCSRBAR */
141 #define CONFIG_SYS_FSL_DSP_CCSRBAR      CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
142 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
143
144 /*
145  * Memory map
146  *
147  * 0x0000_0000  0x3FFF_FFFF     DDR                     1G cacheable
148  * 0x8800_0000  0x8810_0000     IFC internal SRAM               1M
149  * 0xB000_0000  0xB0FF_FFFF     DSP core M2 memory      16M
150  * 0xC100_0000  0xC13F_FFFF     MAPLE-2F                4M
151  * 0xC1F0_0000  0xC1F3_FFFF     PA L2 SRAM Region 0     256K
152  * 0xC1F8_0000  0xC1F9_FFFF     PA L2 SRAM Region 1     128K
153  * 0xFED0_0000  0xFED0_3FFF     SEC Secured RAM         16K
154  * 0xFF60_0000  0xFF6F_FFFF     DSP CCSR                1M
155  * 0xFF70_0000  0xFF7F_FFFF     PA CCSR                 1M
156  * 0xFF80_0000  0xFFFF_FFFF     Boot Page & NAND flash buffer   8M
157  *
158  */
159
160 /*
161  * IFC Definitions
162  */
163 #define CONFIG_SYS_NO_FLASH
164
165 /* NAND Flash on IFC */
166 #define CONFIG_SYS_NAND_BASE            0xff800000
167 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
168
169 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
170                                 | CSPR_PORT_SIZE_8      /* Port Size = 8 bit*/ \
171                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
172                                 | CSPR_V)
173 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
174
175 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
176                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
177                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
178                                 | CSOR_NAND_RAL_2       /* RAL = 2Byes */ \
179                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
180                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
181                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
182
183 /* NAND Flash Timing Params */
184 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x03)  \
185                                         | FTIM0_NAND_TWP(0x05)   \
186                                         | FTIM0_NAND_TWCHT(0x02) \
187                                         | FTIM0_NAND_TWH(0x04))
188 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x1C) \
189                                         | FTIM1_NAND_TWBE(0x1E) \
190                                         | FTIM1_NAND_TRR(0x07)  \
191                                         | FTIM1_NAND_TRP(0x05))
192 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x08)  \
193                                         | FTIM2_NAND_TREH(0x04) \
194                                         | FTIM2_NAND_TWHRE(0x11))
195 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
196
197 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
198 #define CONFIG_SYS_MAX_NAND_DEVICE      1
199 #define CONFIG_CMD_NAND
200 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
201
202 #define CONFIG_SYS_NAND_DDR_LAW         11
203
204 /* Set up IFC registers for boot location NAND */
205 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
206 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
207 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
208 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
209 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
210 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
211 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
212
213 #define CONFIG_BOARD_EARLY_INIT_F       /* Call board_pre_init */
214
215 #define CONFIG_SYS_INIT_RAM_LOCK
216 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* stack in RAM */
217 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000/* End of used area in RAM */
218
219 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
220                                                 - GENERATED_GBL_DATA_SIZE)
221 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
222
223 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
224 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc*/
225
226 /* Serial Port */
227 #define CONFIG_CONS_INDEX       1
228 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
229 #define CONFIG_SYS_NS16550_SERIAL
230 #define CONFIG_SYS_NS16550_REG_SIZE     1
231 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
232 #ifdef CONFIG_SPL_BUILD
233 #define CONFIG_NS16550_MIN_FUNCTIONS
234 #endif
235
236 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
237
238 #define CONFIG_SYS_BAUDRATE_TABLE       \
239         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
240
241 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
242
243 #define CONFIG_SYS_I2C
244 #define CONFIG_SYS_I2C_FSL
245 #define CONFIG_SYS_FSL_I2C_SPEED        400000
246 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
247 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
248
249 /* I2C EEPROM */
250 #define CONFIG_CMD_EEPROM
251 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
252 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
253 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
254
255 /* eSPI - Enhanced SPI */
256 #ifdef CONFIG_FSL_ESPI
257 #define CONFIG_SF_DEFAULT_SPEED         10000000
258 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
259 #endif
260
261 #if defined(CONFIG_TSEC_ENET)
262
263 #define CONFIG_MII                      /* MII PHY management */
264 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
265 #define CONFIG_TSEC1    1
266 #define CONFIG_TSEC1_NAME       "eTSEC1"
267 #define CONFIG_TSEC2    1
268 #define CONFIG_TSEC2_NAME       "eTSEC2"
269
270 #define TSEC1_PHY_ADDR          0
271 #define TSEC2_PHY_ADDR          3
272
273 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
274 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
275
276 #define TSEC1_PHYIDX            0
277
278 #define TSEC2_PHYIDX            0
279
280 #define CONFIG_ETHPRIME         "eTSEC1"
281
282 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
283
284 #endif  /* CONFIG_TSEC_ENET */
285
286 /*
287  * Environment
288  */
289 #if defined(CONFIG_RAMBOOT_SPIFLASH)
290 #define CONFIG_ENV_IS_IN_SPI_FLASH
291 #define CONFIG_ENV_SPI_BUS      0
292 #define CONFIG_ENV_SPI_CS       0
293 #define CONFIG_ENV_SPI_MAX_HZ   10000000
294 #define CONFIG_ENV_SPI_MODE     0
295 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
296 #define CONFIG_ENV_SECT_SIZE    0x10000
297 #define CONFIG_ENV_SIZE         0x2000
298 #elif defined(CONFIG_NAND)
299 #define CONFIG_ENV_IS_IN_NAND
300 #define CONFIG_SYS_EXTRA_ENV_RELOC
301 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
302 #define CONFIG_ENV_OFFSET       ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
303 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE)
304 #elif defined(CONFIG_SYS_RAMBOOT)
305 #define CONFIG_ENV_IS_NOWHERE   /* Store ENV in memory only */
306 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
307 #define CONFIG_ENV_SIZE         0x2000
308 #endif
309
310 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
311 #define CONFIG_SYS_LOADS_BAUD_CHANGE            /* allow baudrate change */
312
313 /*
314  * Command line configuration.
315  */
316 #define CONFIG_CMD_ERRATA
317 #define CONFIG_CMD_IRQ
318 #define CONFIG_DOS_PARTITION
319 #define CONFIG_CMD_REGINFO
320
321 /*
322  * Miscellaneous configurable options
323  */
324 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
325 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
326 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
327 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
328
329 #if defined(CONFIG_CMD_KGDB)
330 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
331 #else
332 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
333 #endif
334 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
335                                                 /* Print Buffer Size */
336 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
337 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
338
339 /*
340  * For booting Linux, the board info and command line data
341  * have to be in the first 64 MB of memory, since this is
342  * the maximum mapped by the Linux kernel during initialization.
343  */
344 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
345 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
346
347 #if defined(CONFIG_CMD_KGDB)
348 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
349 #endif
350
351 /* Hash command with SHA acceleration supported in hardware */
352 #ifdef CONFIG_FSL_CAAM
353 #define CONFIG_CMD_HASH
354 #define CONFIG_SHA_HW_ACCEL
355 #endif
356
357 #define CONFIG_USB_EHCI
358
359 #ifdef CONFIG_USB_EHCI
360 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
361 #define CONFIG_USB_EHCI_FSL
362 #define CONFIG_USB_STORAGE
363 #define CONFIG_HAS_FSL_DR_USB
364 #endif
365
366 /*
367  * Dynamic MTD Partition support with mtdparts
368  */
369 #define CONFIG_MTD_DEVICE
370 #define CONFIG_MTD_PARTITIONS
371 #define CONFIG_CMD_MTDPARTS
372 #define MTDIDS_DEFAULT "nand0=ff800000.flash,"
373 #define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:1m(uboot)," \
374                         "8m(kernel),512k(dtb),-(fs)"
375 /*
376  * Override partitions in device tree using info
377  * in "mtdparts" environment variable
378  */
379 #ifdef CONFIG_CMD_MTDPARTS
380 #define CONFIG_FDT_FIXUP_PARTITIONS
381 #endif
382
383 /*
384  * Environment Configuration
385  */
386
387 #if defined(CONFIG_TSEC_ENET)
388 #define CONFIG_HAS_ETH0
389 #endif
390
391 #define CONFIG_HOSTNAME         BSC9131rdb
392 #define CONFIG_ROOTPATH         "/opt/nfsroot"
393 #define CONFIG_BOOTFILE         "uImage"
394 #define CONFIG_UBOOTPATH        "u-boot.bin" /* U-Boot image on TFTP server */
395
396 #define CONFIG_BAUDRATE         115200
397
398 #define CONFIG_EXTRA_ENV_SETTINGS                               \
399         "netdev=eth0\0"                                         \
400         "uboot=" CONFIG_UBOOTPATH "\0"                          \
401         "loadaddr=1000000\0"                    \
402         "bootfile=uImage\0"     \
403         "consoledev=ttyS0\0"                            \
404         "ramdiskaddr=2000000\0"                 \
405         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
406         "fdtaddr=c00000\0"                              \
407         "fdtfile=bsc9131rdb.dtb\0"              \
408         "bdev=sda1\0"   \
409         "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"    \
410         "bootm_size=0x37000000\0"       \
411         "othbootargs=ramdisk_size=600000 " \
412         "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
413         "usbext2boot=setenv bootargs root=/dev/ram rw " \
414         "console=$consoledev,$baudrate $othbootargs; "  \
415         "usb start;"                    \
416         "ext2load usb 0:4 $loadaddr $bootfile;"         \
417         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
418         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
419         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
420
421 #define CONFIG_RAMBOOTCOMMAND           \
422         "setenv bootargs root=/dev/ram rw "     \
423         "console=$consoledev,$baudrate $othbootargs; "  \
424         "tftp $ramdiskaddr $ramdiskfile;"       \
425         "tftp $loadaddr $bootfile;"             \
426         "tftp $fdtaddr $fdtfile;"               \
427         "bootm $loadaddr $ramdiskaddr $fdtaddr"
428
429 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
430
431 #endif  /* __CONFIG_H */