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fsl_ddr: Move DDR config options to driver Kconfig
[u-boot] / include / configs / BSC9131RDB.h
1 /*
2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 /*
8  * BSC9131 RDB board configuration file
9  */
10
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 #define CONFIG_NAND_FSL_IFC
15
16 #ifdef CONFIG_SPIFLASH
17 #define CONFIG_RAMBOOT_SPIFLASH
18 #define CONFIG_SYS_RAMBOOT
19 #define CONFIG_SYS_EXTRA_ENV_RELOC
20 #define CONFIG_SYS_TEXT_BASE            0x11000000
21 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
22 #endif
23
24 #ifdef CONFIG_NAND
25 #define CONFIG_SPL_INIT_MINIMAL
26 #define CONFIG_SPL_NAND_BOOT
27 #define CONFIG_SPL_FLUSH_IMAGE
28 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
29
30 #define CONFIG_SYS_TEXT_BASE            0x00201000
31 #define CONFIG_SPL_TEXT_BASE            0xFFFFE000
32 #define CONFIG_SPL_MAX_SIZE             8192
33 #define CONFIG_SPL_RELOC_TEXT_BASE      0x00100000
34 #define CONFIG_SPL_RELOC_STACK          0x00100000
35 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
36 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
37 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
38 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0
39 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
40 #endif
41
42 #ifdef CONFIG_SPL_BUILD
43 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
44 #else
45 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
46 #endif
47
48 /* High Level Configuration Options */
49 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
50 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
51
52 #define CONFIG_TSEC_ENET
53 #define CONFIG_ENV_OVERWRITE
54
55 #define CONFIG_DDR_CLK_FREQ     66666666 /* DDRCLK on 9131 RDB */
56 #if defined(CONFIG_SYS_CLK_100)
57 #define CONFIG_SYS_CLK_FREQ    100000000 /* SYSCLK for 9131 RDB */
58 #else
59 #define CONFIG_SYS_CLK_FREQ     66666666 /* SYSCLK for 9131 RDB */
60 #endif
61
62 #define CONFIG_HWCONFIG
63 /*
64  * These can be toggled for performance analysis, otherwise use default.
65  */
66 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
67 #define CONFIG_BTB                      /* enable branch predition */
68
69 #define CONFIG_SYS_MEMTEST_START        0x01000000      /* memtest works on */
70 #define CONFIG_SYS_MEMTEST_END          0x01ffffff
71
72 /* DDR Setup */
73 #undef CONFIG_SYS_DDR_RAW_TIMING
74 #undef CONFIG_DDR_SPD
75 #define CONFIG_SYS_SPD_BUS_NUM          0
76 #define SPD_EEPROM_ADDRESS              0x52 /* I2C access */
77
78 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
79
80 #ifndef __ASSEMBLY__
81 extern unsigned long get_sdram_size(void);
82 #endif
83 #define CONFIG_SYS_SDRAM_SIZE           get_sdram_size() /* DDR size */
84 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
85 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
86
87 #define CONFIG_NUM_DDR_CONTROLLERS      1
88 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
89 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
90
91 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
92 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
93 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
94
95 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
96 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
97 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
98 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
99
100 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
101 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
102 #define CONFIG_SYS_DDR_RCW_1            0x00000000
103 #define CONFIG_SYS_DDR_RCW_2            0x00000000
104 #define CONFIG_SYS_DDR_CONTROL          0xC70C0000      /* Type = DDR3  */
105 #define CONFIG_SYS_DDR_CONTROL_2        0x24401000
106 #define CONFIG_SYS_DDR_TIMING_4         0x00000001
107 #define CONFIG_SYS_DDR_TIMING_5         0x02401400
108
109 #define CONFIG_SYS_DDR_TIMING_3_800             0x00030000
110 #define CONFIG_SYS_DDR_TIMING_0_800             0x00110104
111 #define CONFIG_SYS_DDR_TIMING_1_800             0x6f6b8644
112 #define CONFIG_SYS_DDR_TIMING_2_800             0x0fa888cf
113 #define CONFIG_SYS_DDR_CLK_CTRL_800             0x03000000
114 #define CONFIG_SYS_DDR_MODE_1_800               0x00441420
115 #define CONFIG_SYS_DDR_MODE_2_800               0x8000c000
116 #define CONFIG_SYS_DDR_INTERVAL_800             0x0c300100
117 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800        0x8675f608
118
119 /*
120  * Base addresses -- Note these are effective addresses where the
121  * actual resources get mapped (not physical addresses)
122  */
123 /* relocated CCSRBAR */
124 #define CONFIG_SYS_CCSRBAR      CONFIG_SYS_CCSRBAR_DEFAULT
125 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR_DEFAULT
126
127 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses */
128                                                         /* CONFIG_SYS_IMMR */
129 /* DSP CCSRBAR */
130 #define CONFIG_SYS_FSL_DSP_CCSRBAR      CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
131 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
132
133 /*
134  * Memory map
135  *
136  * 0x0000_0000  0x3FFF_FFFF     DDR                     1G cacheable
137  * 0x8800_0000  0x8810_0000     IFC internal SRAM               1M
138  * 0xB000_0000  0xB0FF_FFFF     DSP core M2 memory      16M
139  * 0xC100_0000  0xC13F_FFFF     MAPLE-2F                4M
140  * 0xC1F0_0000  0xC1F3_FFFF     PA L2 SRAM Region 0     256K
141  * 0xC1F8_0000  0xC1F9_FFFF     PA L2 SRAM Region 1     128K
142  * 0xFED0_0000  0xFED0_3FFF     SEC Secured RAM         16K
143  * 0xFF60_0000  0xFF6F_FFFF     DSP CCSR                1M
144  * 0xFF70_0000  0xFF7F_FFFF     PA CCSR                 1M
145  * 0xFF80_0000  0xFFFF_FFFF     Boot Page & NAND flash buffer   8M
146  *
147  */
148
149 /*
150  * IFC Definitions
151  */
152 #define CONFIG_SYS_NO_FLASH
153
154 /* NAND Flash on IFC */
155 #define CONFIG_SYS_NAND_BASE            0xff800000
156 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
157
158 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
159                                 | CSPR_PORT_SIZE_8      /* Port Size = 8 bit*/ \
160                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
161                                 | CSPR_V)
162 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
163
164 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
165                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
166                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
167                                 | CSOR_NAND_RAL_2       /* RAL = 2Byes */ \
168                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
169                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
170                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
171
172 /* NAND Flash Timing Params */
173 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x03)  \
174                                         | FTIM0_NAND_TWP(0x05)   \
175                                         | FTIM0_NAND_TWCHT(0x02) \
176                                         | FTIM0_NAND_TWH(0x04))
177 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x1C) \
178                                         | FTIM1_NAND_TWBE(0x1E) \
179                                         | FTIM1_NAND_TRR(0x07)  \
180                                         | FTIM1_NAND_TRP(0x05))
181 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x08)  \
182                                         | FTIM2_NAND_TREH(0x04) \
183                                         | FTIM2_NAND_TWHRE(0x11))
184 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
185
186 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
187 #define CONFIG_SYS_MAX_NAND_DEVICE      1
188 #define CONFIG_CMD_NAND
189 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
190
191 #define CONFIG_SYS_NAND_DDR_LAW         11
192
193 /* Set up IFC registers for boot location NAND */
194 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
195 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
196 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
197 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
198 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
199 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
200 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
201
202 #define CONFIG_BOARD_EARLY_INIT_F       /* Call board_pre_init */
203
204 #define CONFIG_SYS_INIT_RAM_LOCK
205 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* stack in RAM */
206 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000/* End of used area in RAM */
207
208 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
209                                                 - GENERATED_GBL_DATA_SIZE)
210 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
211
212 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
213 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc*/
214
215 /* Serial Port */
216 #define CONFIG_CONS_INDEX       1
217 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
218 #define CONFIG_SYS_NS16550_SERIAL
219 #define CONFIG_SYS_NS16550_REG_SIZE     1
220 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
221 #ifdef CONFIG_SPL_BUILD
222 #define CONFIG_NS16550_MIN_FUNCTIONS
223 #endif
224
225 #define CONFIG_SYS_BAUDRATE_TABLE       \
226         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
227
228 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
229
230 #define CONFIG_SYS_I2C
231 #define CONFIG_SYS_I2C_FSL
232 #define CONFIG_SYS_FSL_I2C_SPEED        400000
233 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
234 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
235
236 /* I2C EEPROM */
237 #define CONFIG_CMD_EEPROM
238 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
239 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
240 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
241
242 /* eSPI - Enhanced SPI */
243 #ifdef CONFIG_FSL_ESPI
244 #define CONFIG_SF_DEFAULT_SPEED         10000000
245 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
246 #endif
247
248 #if defined(CONFIG_TSEC_ENET)
249
250 #define CONFIG_MII                      /* MII PHY management */
251 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
252 #define CONFIG_TSEC1    1
253 #define CONFIG_TSEC1_NAME       "eTSEC1"
254 #define CONFIG_TSEC2    1
255 #define CONFIG_TSEC2_NAME       "eTSEC2"
256
257 #define TSEC1_PHY_ADDR          0
258 #define TSEC2_PHY_ADDR          3
259
260 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
261 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
262
263 #define TSEC1_PHYIDX            0
264
265 #define TSEC2_PHYIDX            0
266
267 #define CONFIG_ETHPRIME         "eTSEC1"
268
269 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
270
271 #endif  /* CONFIG_TSEC_ENET */
272
273 /*
274  * Environment
275  */
276 #if defined(CONFIG_RAMBOOT_SPIFLASH)
277 #define CONFIG_ENV_IS_IN_SPI_FLASH
278 #define CONFIG_ENV_SPI_BUS      0
279 #define CONFIG_ENV_SPI_CS       0
280 #define CONFIG_ENV_SPI_MAX_HZ   10000000
281 #define CONFIG_ENV_SPI_MODE     0
282 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
283 #define CONFIG_ENV_SECT_SIZE    0x10000
284 #define CONFIG_ENV_SIZE         0x2000
285 #elif defined(CONFIG_NAND)
286 #define CONFIG_ENV_IS_IN_NAND
287 #define CONFIG_SYS_EXTRA_ENV_RELOC
288 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
289 #define CONFIG_ENV_OFFSET       ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
290 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE)
291 #elif defined(CONFIG_SYS_RAMBOOT)
292 #define CONFIG_ENV_IS_NOWHERE   /* Store ENV in memory only */
293 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
294 #define CONFIG_ENV_SIZE         0x2000
295 #endif
296
297 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
298 #define CONFIG_SYS_LOADS_BAUD_CHANGE            /* allow baudrate change */
299
300 /*
301  * Command line configuration.
302  */
303 #define CONFIG_CMD_ERRATA
304 #define CONFIG_CMD_IRQ
305 #define CONFIG_DOS_PARTITION
306 #define CONFIG_CMD_REGINFO
307
308 /*
309  * Miscellaneous configurable options
310  */
311 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
312 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
313 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
314 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
315
316 #if defined(CONFIG_CMD_KGDB)
317 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
318 #else
319 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
320 #endif
321 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
322                                                 /* Print Buffer Size */
323 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
324 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
325
326 /*
327  * For booting Linux, the board info and command line data
328  * have to be in the first 64 MB of memory, since this is
329  * the maximum mapped by the Linux kernel during initialization.
330  */
331 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
332 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
333
334 #if defined(CONFIG_CMD_KGDB)
335 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
336 #endif
337
338 /* Hash command with SHA acceleration supported in hardware */
339 #ifdef CONFIG_FSL_CAAM
340 #define CONFIG_CMD_HASH
341 #define CONFIG_SHA_HW_ACCEL
342 #endif
343
344 #define CONFIG_USB_EHCI
345
346 #ifdef CONFIG_USB_EHCI
347 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
348 #define CONFIG_USB_EHCI_FSL
349 #define CONFIG_HAS_FSL_DR_USB
350 #endif
351
352 /*
353  * Dynamic MTD Partition support with mtdparts
354  */
355 #define CONFIG_MTD_DEVICE
356 #define CONFIG_MTD_PARTITIONS
357 #define CONFIG_CMD_MTDPARTS
358 #define MTDIDS_DEFAULT "nand0=ff800000.flash,"
359 #define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:1m(uboot)," \
360                         "8m(kernel),512k(dtb),-(fs)"
361
362 /*
363  * Environment Configuration
364  */
365
366 #if defined(CONFIG_TSEC_ENET)
367 #define CONFIG_HAS_ETH0
368 #endif
369
370 #define CONFIG_HOSTNAME         BSC9131rdb
371 #define CONFIG_ROOTPATH         "/opt/nfsroot"
372 #define CONFIG_BOOTFILE         "uImage"
373 #define CONFIG_UBOOTPATH        "u-boot.bin" /* U-Boot image on TFTP server */
374
375 #define CONFIG_BAUDRATE         115200
376
377 #define CONFIG_EXTRA_ENV_SETTINGS                               \
378         "netdev=eth0\0"                                         \
379         "uboot=" CONFIG_UBOOTPATH "\0"                          \
380         "loadaddr=1000000\0"                    \
381         "bootfile=uImage\0"     \
382         "consoledev=ttyS0\0"                            \
383         "ramdiskaddr=2000000\0"                 \
384         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
385         "fdtaddr=1e00000\0"                             \
386         "fdtfile=bsc9131rdb.dtb\0"              \
387         "bdev=sda1\0"   \
388         "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"    \
389         "bootm_size=0x37000000\0"       \
390         "othbootargs=ramdisk_size=600000 " \
391         "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
392         "usbext2boot=setenv bootargs root=/dev/ram rw " \
393         "console=$consoledev,$baudrate $othbootargs; "  \
394         "usb start;"                    \
395         "ext2load usb 0:4 $loadaddr $bootfile;"         \
396         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
397         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
398         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
399
400 #define CONFIG_RAMBOOTCOMMAND           \
401         "setenv bootargs root=/dev/ram rw "     \
402         "console=$consoledev,$baudrate $othbootargs; "  \
403         "tftp $ramdiskaddr $ramdiskfile;"       \
404         "tftp $loadaddr $bootfile;"             \
405         "tftp $fdtaddr $fdtfile;"               \
406         "bootm $loadaddr $ramdiskaddr $fdtaddr"
407
408 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
409
410 #endif  /* __CONFIG_H */