git.sur5r.net Git - u-boot/blob - include/configs/C29XPCIE.h

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * C29XPCIE board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #ifdef CONFIG_SPIFLASH
  15 #define CONFIG_RAMBOOT_SPIFLASH
  16 #define CONFIG_SYS_TEXT_BASE            0x11000000
  17 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  18 #endif
  19
  20 #ifdef CONFIG_NAND
  21 #ifdef CONFIG_TPL_BUILD
  22 #define CONFIG_SPL_NAND_BOOT
  23 #define CONFIG_SPL_FLUSH_IMAGE
  24 #define CONFIG_SPL_NAND_INIT
  25 #define CONFIG_TPL_DRIVERS_MISC_SUPPORT
  26 #define CONFIG_SPL_COMMON_INIT_DDR
  27 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
  28 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
  29 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  30 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (832 << 10)
  31 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
  32 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
  33 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
  34 #elif defined(CONFIG_SPL_BUILD)
  35 #define CONFIG_SPL_INIT_MINIMAL
  36 #define CONFIG_SPL_NAND_MINIMAL
  37 #define CONFIG_SPL_FLUSH_IMAGE
  38 #define CONFIG_SPL_TEXT_BASE            0xff800000
  39 #define CONFIG_SPL_MAX_SIZE             8192
  40 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
  41 #define CONFIG_SYS_NAND_U_BOOT_DST      0xf8f80000
  42 #define CONFIG_SYS_NAND_U_BOOT_START    0xf8f80000
  43 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
  44 #endif
  45 #define CONFIG_SPL_PAD_TO               0x20000
  46 #define CONFIG_TPL_PAD_TO               0x20000
  47 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  48 #define CONFIG_SYS_TEXT_BASE            0x11001000
  49 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  50 #endif
  51
  52 #ifndef CONFIG_SYS_TEXT_BASE
  53 #define CONFIG_SYS_TEXT_BASE            0xeff40000
  54 #endif
  55
  56 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  57 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  58 #endif
  59
  60 #ifdef CONFIG_SPL_BUILD
  61 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  62 #else
  63 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  64 #endif
  65
  66 #ifdef CONFIG_SPL_BUILD
  67 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  68 #endif
  69
  70 /* High Level Configuration Options */
  71 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
  72 #define CONFIG_SYS_HAS_SERDES           /* common SERDES init code */
  73
  74 #ifdef CONFIG_PCI
  75 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
  76 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  77 #define CONFIG_PCI_INDIRECT_BRIDGE
  78 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
  79 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  80
  81 #define CONFIG_CMD_PCI
  82
  83 /*
  84  * PCI Windows
  85  * Memory space is mapped 1-1, but I/O space must start from 0.
  86  */
  87 /* controller 1, Slot 1, tgtid 1, Base address a000 */
  88 #define CONFIG_SYS_PCIE1_NAME           "Slot 1"
  89 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
  90 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
  91 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
  92 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
  93 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
  94 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
  95 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
  96 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
  97
  98 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
  99 #endif
 100
 101 #define CONFIG_TSEC_ENET
 102 #define CONFIG_ENV_OVERWRITE
 103
 104 #define CONFIG_DDR_CLK_FREQ     100000000
 105 #define CONFIG_SYS_CLK_FREQ     66666666
 106
 107 #define CONFIG_HWCONFIG
 108
 109 /*
 110  * These can be toggled for performance analysis, otherwise use default.
 111  */
 112 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 113 #define CONFIG_BTB                      /* toggle branch predition */
 114
 115 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
 116
 117 #define CONFIG_ENABLE_36BIT_PHYS
 118
 119 #define CONFIG_ADDR_MAP                 1
 120 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 121
 122 #define CONFIG_SYS_MEMTEST_START        0x00200000
 123 #define CONFIG_SYS_MEMTEST_END          0x00400000
 124 #define CONFIG_PANIC_HANG
 125
 126 /* DDR Setup */
 127 #define CONFIG_DDR_SPD
 128 #define CONFIG_SYS_SPD_BUS_NUM          0
 129 #define SPD_EEPROM_ADDRESS              0x50
 130 #define CONFIG_SYS_DDR_RAW_TIMING
 131
 132 /* DDR ECC Setup*/
 133 #define CONFIG_DDR_ECC
 134 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 135 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 136
 137 #define CONFIG_SYS_SDRAM_SIZE           512
 138 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 139 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 140
 141 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 142 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 143
 144 #define CONFIG_SYS_CCSRBAR              0xffe00000
 145 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 146
 147 /* Platform SRAM setting  */
 148 #define CONFIG_SYS_PLATFORM_SRAM_BASE   0xffb00000
 149 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
 150                         (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
 151 #define CONFIG_SYS_PLATFORM_SRAM_SIZE   (512 << 10)
 152
 153 /*
 154  * IFC Definitions
 155  */
 156 /* NOR Flash on IFC */
 157 #define CONFIG_SYS_FLASH_BASE           0xec000000
 158 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* 64M */
 159
 160 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 161
 162 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
 163 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 164
 165 #define CONFIG_SYS_FLASH_QUIET_TEST
 166 #define CONFIG_FLASH_SHOW_PROGRESS      45
 167 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* in ms */
 168 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* in ms */
 169
 170 /* 16Bit NOR Flash - S29GL512S10TFI01 */
 171 #define CONFIG_SYS_NOR_CSPR     (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 172                                 CSPR_PORT_SIZE_16 | \
 173                                 CSPR_MSEL_NOR | \
 174                                 CSPR_V)
 175 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(64*1024*1024)
 176 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(4)
 177
 178 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 179                                 FTIM0_NOR_TEADC(0x5) | \
 180                                 FTIM0_NOR_TEAHC(0x5))
 181 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 182                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 183                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 184 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 185                                 FTIM2_NOR_TCH(0x4) | \
 186                                 FTIM2_NOR_TWPH(0x0E) | \
 187                                 FTIM2_NOR_TWP(0x1c))
 188 #define CONFIG_SYS_NOR_FTIM3    0x0
 189
 190 /* CFI for NOR Flash */
 191 #define CONFIG_FLASH_CFI_DRIVER
 192 #define CONFIG_SYS_FLASH_CFI
 193 #define CONFIG_SYS_FLASH_EMPTY_INFO
 194 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 195
 196 /* NAND Flash on IFC */
 197 #define CONFIG_NAND_FSL_IFC
 198 #define CONFIG_SYS_NAND_BASE            0xff800000
 199 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 200
 201 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 202
 203 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 204 #define CONFIG_CMD_NAND
 205 #define CONFIG_SYS_NAND_BLOCK_SIZE      (1024 * 1024)
 206
 207 /* 8Bit NAND Flash - K9F1G08U0B */
 208 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 209                                 | CSPR_PORT_SIZE_8 \
 210                                 | CSPR_MSEL_NAND \
 211                                 | CSPR_V)
 212 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 213 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280      /* 640b */
 214 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 215                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 216                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 217                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 218                                 | CSOR_NAND_PGS_8K      /* Page Size = 8K */ \
 219                                 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
 220                                 | CSOR_NAND_PB(128))    /*128 Pages Per Block*/
 221 #define CONFIG_SYS_NAND_FTIM0   (FTIM0_NAND_TCCST(0x01) | \
 222                                 FTIM0_NAND_TWP(0x0c)   | \
 223                                 FTIM0_NAND_TWCHT(0x08) | \
 224                                 FTIM0_NAND_TWH(0x06))
 225 #define CONFIG_SYS_NAND_FTIM1   (FTIM1_NAND_TADLE(0x28) | \
 226                                 FTIM1_NAND_TWBE(0x1d)  | \
 227                                 FTIM1_NAND_TRR(0x08)   | \
 228                                 FTIM1_NAND_TRP(0x0c))
 229 #define CONFIG_SYS_NAND_FTIM2   (FTIM2_NAND_TRAD(0x0c) | \
 230                                 FTIM2_NAND_TREH(0x0a) | \
 231                                 FTIM2_NAND_TWHRE(0x18))
 232 #define CONFIG_SYS_NAND_FTIM3   (FTIM3_NAND_TWW(0x04))
 233
 234 #define CONFIG_SYS_NAND_DDR_LAW         11
 235
 236 /* Set up IFC registers for boot location NOR/NAND */
 237 #ifdef CONFIG_NAND
 238 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 239 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 240 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 241 #define CONFIG_SYS_CSOR0_EXT            CONFIG_SYS_NAND_OOBSIZE
 242 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 243 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 244 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 245 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 246 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 247 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 248 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 249 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 250 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 251 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 252 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 253 #else
 254 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 255 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 256 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 257 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 258 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 259 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 260 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 261 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 262 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 263 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 264 #define CONFIG_SYS_CSOR1_EXT            CONFIG_SYS_NAND_OOBSIZE
 265 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 266 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 267 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 268 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 269 #endif
 270
 271 /* CPLD on IFC, selected by CS2 */
 272 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
 273 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull \
 274                                         | CONFIG_SYS_CPLD_BASE)
 275
 276 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 277                                 | CSPR_PORT_SIZE_8 \
 278                                 | CSPR_MSEL_GPCM \
 279                                 | CSPR_V)
 280 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 281 #define CONFIG_SYS_CSOR2        0x0
 282 /* CPLD Timing parameters for IFC CS2 */
 283 #define CONFIG_SYS_CS2_FTIM0    (FTIM0_GPCM_TACSE(0x0e) | \
 284                                 FTIM0_GPCM_TEADC(0x0e) | \
 285                                 FTIM0_GPCM_TEAHC(0x0e))
 286 #define CONFIG_SYS_CS2_FTIM1    (FTIM1_GPCM_TACO(0x0e) | \
 287                                 FTIM1_GPCM_TRAD(0x1f))
 288 #define CONFIG_SYS_CS2_FTIM2    (FTIM2_GPCM_TCS(0x0e) | \
 289                                 FTIM2_GPCM_TCH(0x8) | \
 290                                 FTIM2_GPCM_TWP(0x1f))
 291 #define CONFIG_SYS_CS2_FTIM3    0x0
 292
 293 #if defined(CONFIG_RAMBOOT_SPIFLASH)
 294 #define CONFIG_SYS_RAMBOOT
 295 #define CONFIG_SYS_EXTRA_ENV_RELOC
 296 #endif
 297
 298 #define CONFIG_BOARD_EARLY_INIT_R
 299
 300 #define CONFIG_SYS_INIT_RAM_LOCK
 301 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000
 302 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 303
 304 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
 305                                                 - GENERATED_GBL_DATA_SIZE)
 306 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 307
 308 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 309 #define CONFIG_SYS_MALLOC_LEN           (2 * 1024 * 1024)
 310
 311 /*
 312  * Config the L2 Cache as L2 SRAM
 313  */
 314 #if defined(CONFIG_SPL_BUILD)
 315 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 316 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 317 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 318 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 319 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 320 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 321 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
 322 #define CONFIG_SPL_RELOC_STACK_SIZE     (32 << 10)
 323 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
 324 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (96 << 10)
 325 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 326 #elif defined(CONFIG_NAND)
 327 #ifdef CONFIG_TPL_BUILD
 328 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 329 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 330 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 331 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 332 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 333 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 334 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 335 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 336 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 337 #else
 338 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 339 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 340 #define CONFIG_SYS_L2_SIZE              (256 << 10)
 341 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 342 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x3000)
 343 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 344 #endif
 345 #endif
 346 #endif
 347
 348 /* Serial Port */
 349 #define CONFIG_CONS_INDEX       1
 350 #define CONFIG_SYS_NS16550_SERIAL
 351 #define CONFIG_SYS_NS16550_REG_SIZE     1
 352 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 353
 354 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 355 #define CONFIG_NS16550_MIN_FUNCTIONS
 356 #endif
 357
 358 #define CONFIG_SYS_BAUDRATE_TABLE       \
 359         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 360
 361 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 362 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 363
 364 #define CONFIG_SYS_I2C
 365 #define CONFIG_SYS_I2C_FSL
 366 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 367 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 368 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 369 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 370 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 371 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 372
 373 /* I2C EEPROM */
 374 /* enable read and write access to EEPROM */
 375 #define CONFIG_CMD_EEPROM
 376 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 377 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 378 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 379
 380 /* eSPI - Enhanced SPI */
 381 #define CONFIG_SF_DEFAULT_SPEED         10000000
 382 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
 383
 384 #ifdef CONFIG_TSEC_ENET
 385 #define CONFIG_MII                      /* MII PHY management */
 386 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 387 #define CONFIG_TSEC1            1
 388 #define CONFIG_TSEC1_NAME       "eTSEC1"
 389 #define CONFIG_TSEC2            1
 390 #define CONFIG_TSEC2_NAME       "eTSEC2"
 391
 392 /* Default mode is RGMII mode */
 393 #define TSEC1_PHY_ADDR          0
 394 #define TSEC2_PHY_ADDR          2
 395
 396 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 397 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 398
 399 #define CONFIG_ETHPRIME         "eTSEC1"
 400
 401 #define CONFIG_PHY_GIGE
 402 #endif  /* CONFIG_TSEC_ENET */
 403
 404 /*
 405  * Environment
 406  */
 407 #if defined(CONFIG_SYS_RAMBOOT)
 408 #if defined(CONFIG_RAMBOOT_SPIFLASH)
 409 #define CONFIG_ENV_IS_IN_SPI_FLASH
 410 #define CONFIG_ENV_SPI_BUS      0
 411 #define CONFIG_ENV_SPI_CS       0
 412 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 413 #define CONFIG_ENV_SPI_MODE     0
 414 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 415 #define CONFIG_ENV_SECT_SIZE    0x10000
 416 #define CONFIG_ENV_SIZE         0x2000
 417 #endif
 418 #elif defined(CONFIG_NAND)
 419 #define CONFIG_ENV_IS_IN_NAND
 420 #ifdef CONFIG_TPL_BUILD
 421 #define CONFIG_ENV_SIZE         0x2000
 422 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 423 #else
 424 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 425 #define CONFIG_ENV_RANGE        CONFIG_ENV_SIZE
 426 #endif
 427 #define CONFIG_ENV_OFFSET       CONFIG_SYS_NAND_BLOCK_SIZE
 428 #else
 429 #define CONFIG_ENV_IS_IN_FLASH
 430 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 431 #define CONFIG_ENV_SIZE         0x2000
 432 #define CONFIG_ENV_SECT_SIZE    0x20000
 433 #endif
 434
 435 #define CONFIG_LOADS_ECHO
 436 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 437
 438 /*
 439  * Command line configuration.
 440  */
 441 #define CONFIG_CMD_ERRATA
 442 #define CONFIG_CMD_IRQ
 443 #define CONFIG_CMD_REGINFO
 444
 445 /* Hash command with SHA acceleration supported in hardware */
 446 #ifdef CONFIG_FSL_CAAM
 447 #define CONFIG_CMD_HASH
 448 #define CONFIG_SHA_HW_ACCEL
 449 #endif
 450
 451 /*
 452  * Miscellaneous configurable options
 453  */
 454 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 455 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 456 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 457 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 458
 459 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 460 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 461                                                 /* Print Buffer Size */
 462 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 463 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 464
 465 /*
 466  * For booting Linux, the board info and command line data
 467  * have to be in the first 64 MB of memory, since this is
 468  * the maximum mapped by the Linux kernel during initialization.
 469  */
 470 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 471 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 472
 473 /*
 474  * Environment Configuration
 475  */
 476
 477 #ifdef CONFIG_TSEC_ENET
 478 #define CONFIG_HAS_ETH0
 479 #define CONFIG_HAS_ETH1
 480 #endif
 481
 482 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 483 #define CONFIG_BOOTFILE         "uImage"
 484 #define CONFIG_UBOOTPATH        u-boot.bin/* U-Boot image on TFTP server */
 485
 486 /* default location for tftp and bootm */
 487 #define CONFIG_LOADADDR         1000000
 488
 489
 490 #define CONFIG_BAUDRATE         115200
 491
 492 #define CONFIG_DEF_HWCONFIG     fsl_ddr:ecc=on
 493
 494 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 495         "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"      \
 496         "netdev=eth0\0"                                         \
 497         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 498         "loadaddr=1000000\0"                            \
 499         "consoledev=ttyS0\0"                            \
 500         "ramdiskaddr=2000000\0"                         \
 501         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 502         "fdtaddr=1e00000\0"                             \
 503         "fdtfile=name/of/device-tree.dtb\0"                     \
 504         "othbootargs=ramdisk_size=600000\0"             \
 505
 506 #define CONFIG_RAMBOOTCOMMAND                   \
 507         "setenv bootargs root=/dev/ram rw "     \
 508         "console=$consoledev,$baudrate $othbootargs; "  \
 509         "tftp $ramdiskaddr $ramdiskfile;"       \
 510         "tftp $loadaddr $bootfile;"             \
 511         "tftp $fdtaddr $fdtfile;"               \
 512         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 513
 514 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
 515
 516 #include <asm/fsl_secure_boot.h>
 517
 518 #endif  /* __CONFIG_H */