3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * Configuration settings for the CU824 board.
30 /* ------------------------------------------------------------------------- */
33 * board/config.h - configuration options, board specific
40 * High Level Configuration Options
44 #define CONFIG_MPC824X 1
45 #define CONFIG_MPC8240 1
46 #define CONFIG_CU824 1
49 #define CONFIG_CONS_INDEX 1
50 #define CONFIG_BAUDRATE 9600
51 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
53 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
55 #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
57 #define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */
58 #define CONFIG_BOOTDELAY 5
60 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
62 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
67 /* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
69 #include <cmd_confdefs.h>
73 * Miscellaneous configurable options
75 #define CFG_LONGHELP /* undef to save memory */
76 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
77 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
80 #define CFG_HUSH_PARSER 1 /* use "hush" command parser */
82 #ifdef CFG_HUSH_PARSER
83 #define CFG_PROMPT_HUSH_PS2 "> "
88 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
90 #define CFG_MAXARGS 16 /* max number of command args */
91 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
92 #define CFG_LOAD_ADDR 0x00100000 /* Default load address */
94 /*-----------------------------------------------------------------------
95 * Start addresses for the final memory configuration
96 * (Set up by the startup code)
97 * Please note that CFG_SDRAM_BASE _must_ start at 0
99 #define CFG_SDRAM_BASE 0x00000000
100 #define CFG_FLASH_BASE 0xFF000000
102 #define CFG_RESET_ADDRESS 0xFFF00100
104 #define CFG_EUMB_ADDR 0xFCE00000
106 #define CFG_MONITOR_BASE TEXT_BASE
108 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
109 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
111 #define CFG_MEMTEST_START 0x00004000 /* memtest works on */
112 #define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
114 /* Maximum amount of RAM.
116 #define CFG_MAX_RAM_SIZE 0x10000000
119 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
126 /*-----------------------------------------------------------------------
127 * Definitions for initial stack pointer and data area
130 /* Size in bytes reserved for initial data
132 #define CFG_GBL_DATA_SIZE 128
134 #define CFG_INIT_RAM_ADDR 0x40000000
135 #define CFG_INIT_RAM_END 0x1000
136 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
139 * NS16550 Configuration
142 #define CFG_NS16550_SERIAL
144 #define CFG_NS16550_REG_SIZE 4
146 #define CFG_NS16550_CLK (14745600 / 2)
148 #define CFG_NS16550_COM1 0xFE800080
149 #define CFG_NS16550_COM2 0xFE8000C0
152 * Low Level Configuration Settings
153 * (address mappings, register initial values, etc.)
154 * You should know what you are doing if you make changes here.
155 * For the detail description refer to the MPC8240 user's manual.
158 #define CONFIG_SYS_CLK_FREQ 33000000
161 /* Bit-field values for MCCR1.
166 /* Bit-field values for MCCR2.
168 #define CFG_REFINT 430 /* Refresh interval */
170 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
172 #define CFG_BSTOPRE 192
174 /* Bit-field values for MCCR3.
176 #define CFG_REFREC 2 /* Refresh to activate interval */
177 #define CFG_RDLAT 3 /* Data latancy from read command */
179 /* Bit-field values for MCCR4.
181 #define CFG_PRETOACT 2 /* Precharge to activate interval */
182 #define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
183 #define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
184 #define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
185 #define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
187 #define CFG_REGISTERD_TYPE_BUFFER 1
189 /* Memory bank settings.
190 * Only bits 20-29 are actually used from these vales to set the
191 * start/end addresses. The upper two bits will always be 0, and the lower
192 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
193 * address. Refer to the MPC8240 book.
196 #define CFG_BANK0_START 0x00000000
197 #define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
198 #define CFG_BANK0_ENABLE 1
199 #define CFG_BANK1_START 0x3ff00000
200 #define CFG_BANK1_END 0x3fffffff
201 #define CFG_BANK1_ENABLE 0
202 #define CFG_BANK2_START 0x3ff00000
203 #define CFG_BANK2_END 0x3fffffff
204 #define CFG_BANK2_ENABLE 0
205 #define CFG_BANK3_START 0x3ff00000
206 #define CFG_BANK3_END 0x3fffffff
207 #define CFG_BANK3_ENABLE 0
208 #define CFG_BANK4_START 0x3ff00000
209 #define CFG_BANK4_END 0x3fffffff
210 #define CFG_BANK4_ENABLE 0
211 #define CFG_BANK5_START 0x3ff00000
212 #define CFG_BANK5_END 0x3fffffff
213 #define CFG_BANK5_ENABLE 0
214 #define CFG_BANK6_START 0x3ff00000
215 #define CFG_BANK6_END 0x3fffffff
216 #define CFG_BANK6_ENABLE 0
217 #define CFG_BANK7_START 0x3ff00000
218 #define CFG_BANK7_END 0x3fffffff
219 #define CFG_BANK7_ENABLE 0
221 #define CFG_ODCR 0xff
223 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
224 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
226 #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
227 #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
229 #define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
230 #define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
232 #define CFG_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
233 #define CFG_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
235 #define CFG_DBAT0L CFG_IBAT0L
236 #define CFG_DBAT0U CFG_IBAT0U
237 #define CFG_DBAT1L CFG_IBAT1L
238 #define CFG_DBAT1U CFG_IBAT1U
239 #define CFG_DBAT2L CFG_IBAT2L
240 #define CFG_DBAT2U CFG_IBAT2U
241 #define CFG_DBAT3L CFG_IBAT3L
242 #define CFG_DBAT3U CFG_IBAT3U
245 * For booting Linux, the board info and command line data
246 * have to be in the first 8 MB of memory, since this is
247 * the maximum mapped by the Linux kernel during initialization.
249 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
251 /*-----------------------------------------------------------------------
254 #define CFG_MAX_FLASH_BANKS 2 /* Max number of flash banks */
255 #define CFG_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */
257 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
258 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
260 /* Warining: environment is not EMBEDDED in the U-Boot code.
261 * It's stored in flash separately.
263 #define CFG_ENV_IS_IN_FLASH 1
265 #define CFG_ENV_ADDR 0xFF008000
266 #define CFG_ENV_SIZE 0x8000 /* Size of the Environment Sector */
268 #define CFG_ENV_ADDR 0xFFFC0000
269 #define CFG_ENV_SIZE 0x4000 /* Size of the Environment */
270 #define CFG_ENV_OFFSET 0 /* starting right at the beginning */
271 #define CFG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */
274 /*-----------------------------------------------------------------------
275 * Cache Configuration
277 #define CFG_CACHELINE_SIZE 32
278 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
279 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
283 * Internal Definitions
287 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
288 #define BOOTFLAG_WARM 0x02 /* Software reboot */
290 /*-----------------------------------------------------------------------
292 *-----------------------------------------------------------------------
294 #define CONFIG_PCI /* include pci support */
295 #undef CONFIG_PCI_PNP
297 #define CONFIG_NET_MULTI /* Multi ethernet cards support */
300 #define CONFIG_TULIP_USE_IO
302 #define CFG_ETH_DEV_FN 0x7800
303 #define CFG_ETH_IOBASE 0x00104000
305 #endif /* __CONFIG_H */