2 * Configuation settings for the BuS EB+MCF-EV123 boards.
4 * (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #ifndef _CONFIG_EB_MCF_EV123_H_
26 #define _CONFIG_EB_MCF_EV123_H_
28 #define CONFIG_EB_MCF_EV123
31 #undef CFG_HALT_BEFOR_RAM_JUMP
35 * High Level Configuration Options (easy to change)
38 #define CONFIG_MCF52x2 /* define processor family */
39 #define CONFIG_M5282 /* define processor type */
41 #define CONFIG_MISC_INIT_R
44 #define CONFIG_ETHADDR 00:CF:52:82:EB:01
46 #define CONFIG_BAUDRATE 9600
47 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
49 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
51 #define CONFIG_BOOTCOMMAND "printenv"
53 /* Configuration for environment
54 * Environment is embedded in u-boot in the second sector of the flash
56 #ifndef CONFIG_MONITOR_IS_IN_RAM
57 #define CFG_ENV_ADDR 0xF003C000 /* End of 256K */
58 #define CFG_ENV_SECT_SIZE 0x4000
59 #define CFG_ENV_IS_IN_FLASH 1
61 #define CFG_ENV_IS_EMBEDDED 1
62 #define CFG_ENV_ADDR_REDUND 0xF0018000
63 #define CFG_ENV_SECT_SIZE_REDUND 0x4000
66 #define CFG_ENV_ADDR 0xFFE04000
67 #define CFG_ENV_SECT_SIZE 0x2000
68 #define CFG_ENV_IS_IN_FLASH 1
73 * Command line configuration.
75 #include <config_cmd_default.h>
77 #undef CONFIG_CMD_LOADB
80 #define CONFIG_BOOTDELAY 5
81 #define CFG_PROMPT "\nEV123 U-Boot> "
82 #define CFG_LONGHELP /* undef to save memory */
84 #if defined(CONFIG_CMD_KGDB)
85 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
87 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
89 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
90 #define CFG_MAXARGS 16 /* max number of command args */
91 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
93 #define CFG_LOAD_ADDR 0x20000
95 #define CFG_MEMTEST_START 0x100000
96 #define CFG_MEMTEST_END 0x400000
97 /*#define CFG_DRAM_TEST 1 */
100 /* Clock and PLL Configuration */
101 #define CFG_HZ 10000000
102 #define CFG_CLK 58982400 /* 9,8304MHz * 6 */
104 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
106 #define CFG_MFD 0x01 /* PLL Multiplication Factor Devider */
107 #define CFG_RFD 0x00 /* PLL Reduce Frecuency Devider */
110 * Low Level Configuration Settings
111 * (address mappings, register initial values, etc.)
112 * You should know what you are doing if you make changes here.
114 #define CFG_MBAR 0x40000000
116 #define CFG_DISCOVER_PHY
117 /* #define CFG_ENET_BD_BASE 0x380000 */
119 /*-----------------------------------------------------------------------
120 * Definitions for initial stack pointer and data area (in DPRAM)
122 #define CFG_INIT_RAM_ADDR 0x20000000
123 #define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
124 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
125 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
126 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
128 /*-----------------------------------------------------------------------
129 * Start addresses for the final memory configuration
130 * (Set up by the startup code)
131 * Please note that CFG_SDRAM_BASE _must_ start at 0
133 #define CFG_SDRAM_BASE1 0x00000000
134 #define CFG_SDRAM_SIZE1 16 /* SDRAM size in MB */
137 #define CFG_SDRAM_BASE0 CFG_SDRAM_BASE1+CFG_SDRAM_SIZE1*1024*1024
138 #define CFG_SDRAM_SIZE0 16 */ /* SDRAM size in MB */
140 #define CFG_SDRAM_BASE CFG_SDRAM_BASE1
141 #define CFG_SDRAM_SIZE CFG_SDRAM_SIZE1
143 #define CFG_FLASH_BASE 0xFFE00000
144 #define CFG_INT_FLASH_BASE 0xF0000000
146 /* If M5282 port is fully implemented the monitor base will be behind
147 * the vector table. */
148 #if (TEXT_BASE != CFG_INT_FLASH_BASE)
149 #define CFG_MONITOR_BASE (TEXT_BASE + 0x400)
151 #define CFG_MONITOR_BASE (TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
154 #define CFG_MONITOR_LEN 0x20000
155 #define CFG_MALLOC_LEN (256 << 10)
156 #define CFG_BOOTPARAMS_LEN 64*1024
159 * For booting Linux, the board info and command line data
160 * have to be in the first 8 MB of memory, since this is
161 * the maximum mapped by the Linux kernel during initialization ??
163 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
165 /*-----------------------------------------------------------------------
168 #define CFG_MAX_FLASH_SECT 35
169 #define CFG_MAX_FLASH_BANKS 2
170 #define CFG_FLASH_ERASE_TOUT 10000000
171 #define CFG_FLASH_PROTECTION
173 /*-----------------------------------------------------------------------
174 * Cache Configuration
176 #define CFG_CACHELINE_SIZE 16
178 /*-----------------------------------------------------------------------
179 * Memory bank definitions
182 #define CFG_CS0_BASE CFG_FLASH_BASE
183 #define CFG_CS0_SIZE 2*1024*1024
184 #define CFG_CS0_WIDTH 16
188 #define CFG_CS3_BASE 0xE0000000
189 #define CFG_CS3_SIZE 1*1024*1024
190 #define CFG_CS3_WIDTH 16
194 /*-----------------------------------------------------------------------
197 #define CFG_PACNT 0x0000000 /* Port A D[31:24] */
198 #define CFG_PADDR 0x0000000
199 #define CFG_PADAT 0x0000000
201 #define CFG_PBCNT 0x0000000 /* Port B D[23:16] */
202 #define CFG_PBDDR 0x0000000
203 #define CFG_PBDAT 0x0000000
205 #define CFG_PCCNT 0x0000000 /* Port C D[15:08] */
206 #define CFG_PCDDR 0x0000000
207 #define CFG_PCDAT 0x0000000
209 #define CFG_PDCNT 0x0000000 /* Port D D[07:00] */
210 #define CFG_PCDDR 0x0000000
211 #define CFG_PCDAT 0x0000000
213 #define CFG_PEHLPAR 0xC0
214 #define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
215 #define CFG_DDRUA 0x05
216 #define CFG_PJPAR 0xFF;
218 /*-----------------------------------------------------------------------
222 #define CFG_CCM_SIZ 0
224 /*---------------------------------------------------------------------*/
225 #endif /* _CONFIG_M5282EVB_H */
226 /*---------------------------------------------------------------------*/