2 * (C) Copyright 2002 ELTEC Elektronik AG
3 * Frank Gottschling <fgottschling@eltec.de>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 #define GTREGREAD(x) 0xffffffff /* needed for debug */
35 * High Level Configuration Options
39 /* these hardware addresses are pretty bogus, please change them to
43 #define CONFIG_ETHADDR 00:00:5b:ee:de:ad
45 #define CONFIG_IPADDR 192.168.0.105
46 #define CONFIG_SERVERIP 192.168.0.100
48 #define CONFIG_ELPPC 1 /* this is an BAB740/BAB750 board */
50 #define CONFIG_BAUDRATE 9600 /* console baudrate */
52 #undef CONFIG_WATCHDOG
54 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
56 #define CONFIG_ZERO_BOOTDELAY_CHECK
58 #undef CONFIG_BOOTARGS
59 #define CONFIG_BOOTCOMMAND \
61 "setenv bootargs root=ramfs console=ttyS00,9600 " \
62 "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:" \
63 "${netmask}:${hostname}:eth0:none; " \
66 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
67 #define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
69 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
73 * Command line configuration.
75 #include <config_cmd_default.h>
77 #define CONFIG_CMD_PCI
78 #define CONFIG_CMD_JFFS2
82 * Miscellaneous configurable options
84 #define CFG_LONGHELP /* undef to save memory */
85 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
88 * choose between COM1 and COM2 as serial console
90 #define CONFIG_CONS_INDEX 1
92 #if defined(CONFIG_CMD_KGDB)
93 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
95 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
97 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
98 #define CFG_MAXARGS 16 /* max number of command args */
99 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
101 #define CFG_MEMTEST_START 0x00000000 /* memtest works on */
102 #define CFG_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */
104 #define CFG_LOAD_ADDR 0x1000000 /* default load address */
106 #define CFG_HZ 1000 /* dec. freq: 1 ms ticks */
108 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
111 * Low Level Configuration Settings
112 * (address mappings, register initial values, etc.)
113 * You should know what you are doing if you make changes here.
115 #define CFG_BOARD_ASM_INIT
116 #define CONFIG_MISC_INIT_R
119 * Address mapping scheme for the MPC107 mem controller is mapping B (CHRP)
121 #undef CFG_ADDRESS_MAP_A
123 #define CFG_PCI_MEMORY_BUS 0x00000000
124 #define CFG_PCI_MEMORY_PHYS 0x00000000
125 #define CFG_PCI_MEMORY_SIZE 0x40000000
127 #define CFG_PCI_MEM_BUS 0x80000000
128 #define CFG_PCI_MEM_PHYS 0x80000000
129 #define CFG_PCI_MEM_SIZE 0x7d000000
131 #define CFG_ISA_MEM_BUS 0x00000000
132 #define CFG_ISA_MEM_PHYS 0xfd000000
133 #define CFG_ISA_MEM_SIZE 0x01000000
135 #define CFG_PCI_IO_BUS 0x00800000
136 #define CFG_PCI_IO_PHYS 0xfe800000
137 #define CFG_PCI_IO_SIZE 0x00400000
139 #define CFG_ISA_IO_BUS 0x00000000
140 #define CFG_ISA_IO_PHYS 0xfe000000
141 #define CFG_ISA_IO_SIZE 0x00800000
143 /* driver defines FDC,IDE,... */
144 #define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
145 #define CFG_ISA_IO CFG_ISA_IO_PHYS
146 #define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS
149 * Start addresses for the final memory configuration
150 * (Set up by the startup code)
151 * Please note that CFG_SDRAM_BASE _must_ start at 0
153 #define CFG_SDRAM_BASE 0x00000000
155 #define CFG_USR_LED_BASE 0x78000000
156 #define CFG_NVRAM_BASE 0xff000000
157 #define CFG_UART_BASE 0xff400000
158 #define CFG_FLASH_BASE 0xfff00000
160 #define MPC107_EUMB_ADDR 0xfce00000
161 #define MPC107_EUMB_PI 0xfce41090
162 #define MPC107_EUMB_GCR 0xfce41020
163 #define MPC107_EUMB_IACKR 0xfce600a0
164 #define MPC107_I2C_ADDR 0xfce03000
167 * Definitions for initial stack pointer and data area
169 #define CFG_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */
170 #define CFG_INIT_RAM_END 0x4000
171 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for init data */
172 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
173 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
176 * Flash mapping/organization on the MPC10x.
178 #define FLASH_BASE0_PRELIM 0xff800000
179 #define FLASH_BASE1_PRELIM 0xffc00000
181 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
182 #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
184 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
185 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
191 /* No command line, one static partition, whole device */
192 #undef CONFIG_JFFS2_CMDLINE
193 #define CONFIG_JFFS2_DEV "nor0"
194 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
195 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
197 /* mtdparts command line support */
198 /* Note: fake mtd_id used, no linux mtd map file */
200 #define CONFIG_JFFS2_CMDLINE
201 #define MTDIDS_DEFAULT "nor0=elppc-0,nor1=elppc-1"
202 #define MTDPARTS_DEFAULT "mtdparts=elppc-0:-(jffs2),elppc-1:-(user)"
205 #define CFG_MONITOR_BASE CFG_FLASH_BASE
206 #define CFG_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
207 #define CFG_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */
211 * Environment settings
213 #define CONFIG_ENV_OVERWRITE
214 #define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
215 #define CFG_NVRAM_SIZE 0x800 /* NVRAM size (2kB) */
216 #define CFG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */
217 #define CFG_ENV_ADDR 0x0
218 #define CFG_ENV_MAP_ADRS 0xff000000
219 #define CFG_NV_SROM_COPY_ADDR (CFG_ENV_ADDR + CFG_ENV_SIZE)
220 #define CFG_NVRAM_ACCESS_ROUTINE /* only byte accsess alowed */
221 #define CFG_SROM_SIZE 0x100 /* shadow of revision info is in nvram */
227 #define CFG_NS16550_SERIAL
228 #define CFG_NS16550_REG_SIZE 1
229 #define CFG_NS16550_CLK 24000000
230 #define CFG_NS16550_COM1 (CFG_UART_BASE + 0)
231 #define CFG_NS16550_COM2 (CFG_UART_BASE + 8)
236 #define CONFIG_PCI /* include pci support */
237 #define CONFIG_PCI_PNP /* pci plug-and-play */
238 #define CONFIG_PCI_HOST PCI_HOST_AUTO
239 #undef CONFIG_PCI_SCAN_SHOW
242 * Optional Video console (graphic: SMI LynxEM)
245 #define CONFIG_CFB_CONSOLE
246 #define VIDEO_KBD_INIT_FCT (simple_strtol (getenv("console"), NULL, 10))
247 #define VIDEO_TSTC_FCT serial_tstc
248 #define VIDEO_GETC_FCT serial_getc
250 #define CONFIG_VIDEO_SMI_LYNXEM
251 #define CONFIG_VIDEO_LOGO
252 #define CONFIG_CONSOLE_EXTRA_INFO
261 #define CFG_DBAT0L CFG_IBAT1L
262 #define CFG_DBAT0U CFG_IBAT1U
266 #define CFG_DBAT1L CFG_IBAT1L
267 #define CFG_DBAT1U CFG_IBAT1U
271 #define CFG_DBAT2L CFG_IBAT2L
272 #define CFG_DBAT2U CFG_IBAT2U
276 #define CFG_DBAT3L CFG_IBAT3L
277 #define CFG_DBAT3U CFG_IBAT3U
282 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_RW)
283 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
284 #define CFG_DBAT0L CFG_IBAT1L
285 #define CFG_DBAT0U CFG_IBAT1U
287 /* address range for flashes */
288 #define CFG_IBAT1L (CFG_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
289 #define CFG_IBAT1U (CFG_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
290 #define CFG_DBAT1L CFG_IBAT1L
291 #define CFG_DBAT1U CFG_IBAT1U
294 #define CFG_IBAT2L (CFG_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
295 #define CFG_IBAT2U (CFG_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
296 #define CFG_DBAT2L CFG_IBAT2L
297 #define CFG_DBAT2U CFG_IBAT2U
299 /* ISA memory space */
300 #define CFG_IBAT3L (CFG_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
301 #define CFG_IBAT3U (CFG_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
302 #define CFG_DBAT3L CFG_IBAT3L
303 #define CFG_DBAT3U CFG_IBAT3U
308 * Speed settings are board specific
310 #define CFG_BUS_HZ 100000000
311 #define CFG_CPU_CLK 400000000
312 #define CFG_BUS_CLK CFG_BUS_HZ
315 * For booting Linux, the board info and command line data
316 * have to be in the first 8 MB of memory, since this is
317 * the maximum mapped by the Linux kernel during initialization.
319 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
322 * Cache Configuration
324 #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
325 #if defined(CONFIG_CMD_KGDB)
326 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
330 * L2CR setup -- make sure this is right for your board!
331 * look in include/74xx_7xx.h for the defines used here
337 #define L2_INIT 0 /* cpu 750 CXe*/
339 #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
340 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
342 #define L2_ENABLE (L2_INIT | L2CR_L2E)
345 * Internal Definitions
349 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
350 #define BOOTFLAG_WARM 0x02 /* Software reboot */
352 #define CONFIG_NET_MULTI /* Multi ethernet cards support */
353 #define CONFIG_EEPRO100
354 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
355 #define CONFIG_EEPRO100_SROM_WRITE
357 #endif /* __CONFIG_H */