3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC850 1 /* This is a MPC850 CPU */
37 #define CONFIG_ESTEEM192E 1 /* ...on a EST ESTEEM192E */
39 #define CONFIG_FLASH_16BIT 1 /* Rom 16 bit data bus */
41 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
42 #undef CONFIG_8xx_CONS_SMC2
43 #undef CONFIG_8xx_CONS_NONE
45 #define MPC8XX_FACT 10 /* Multiply by 10 */
46 #define MPC8XX_XIN 4915200 /* 4.915200 MHz in - ??? - XXX */
47 #define CFG_PLPRCR_MF ((MPC8XX_FACT-1) << 20)
48 #define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) /* 49,152,000 Hz */
50 #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */
52 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
54 #define CONFIG_BAUDRATE 9600
56 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
58 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
60 #define CONFIG_BOOTCOMMAND "bootm 40030000" /* autoboot command */
62 #define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk=8192 " \
63 "ip=100.100.100.21:100.100.100.14:100.100.100.1:255.0.0.0 "
65 * Miscellaneous configurable options
68 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
69 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
71 #undef CONFIG_WATCHDOG /* watchdog disabled */
73 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
76 * Command line configuration.
78 #include <config_cmd_default.h>
81 #define CFG_LONGHELP /* undef to save memory */
82 #define CFG_PROMPT "BOOT: " /* Monitor Command Prompt */
83 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
84 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
85 #define CFG_MAXARGS 8 /* max number of command args */
86 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
88 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
89 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
91 #define CFG_LOAD_ADDR 0x100000 /* default load address */
93 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
96 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
100 * Low Level Configuration Settings
101 * (address mappings, register initial values, etc.)
102 * You should know what you are doing if you make changes here.
104 /*-----------------------------------------------------------------------
105 * Internal Memory Mapped Register
107 #define CFG_IMMR 0xFF000000
109 /*-----------------------------------------------------------------------
110 * Definitions for initial stack pointer and data area (in DPRAM)
112 #define CFG_INIT_RAM_ADDR CFG_IMMR
113 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
114 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
115 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
116 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
119 /*-----------------------------------------------------------------------
120 * Start addresses for the final memory configuration
121 * (Set up by the startup code)
122 * Please note that CFG_SDRAM_BASE _must_ start at 0
124 #define CFG_SDRAM_BASE 0x00000000
125 #define CFG_FLASH_BASE 0x40000000
127 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
129 #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
131 #define CFG_MONITOR_BASE CFG_FLASH_BASE
132 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
135 * For booting Linux, the board info and command line data
136 * have to be in the first 8 MB of memory, since this is
137 * the maximum mapped by the Linux kernel during initialization.
139 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
140 /*-----------------------------------------------------------------------
143 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
144 #define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
146 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
147 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
149 #define CFG_ENV_IS_IN_FLASH 1
150 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
151 #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
152 /*-----------------------------------------------------------------------
153 * Cache Configuration
155 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
157 /*-----------------------------------------------------------------------
158 * SYPCR - System Protection Control 11-9
159 * SYPCR can only be written once after reset!
160 *-----------------------------------------------------------------------
161 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
163 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
165 /*-----------------------------------------------------------------------
166 * SUMCR - SIU Module Configuration 11-6
167 *-----------------------------------------------------------------------
168 * PCMCIA config., multi-function pin tri-state
170 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) /* DBGC00 */
172 /*-----------------------------------------------------------------------
173 * TBSCR - Time Base Status and Control 11-26
174 *-----------------------------------------------------------------------
175 * Clear Reference Interrupt Status, Timebase freezing enabled
177 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
179 /* (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) */
182 /*-----------------------------------------------------------------------
183 * PISCR - Periodic Interrupt Status and Control 11-31
184 *-----------------------------------------------------------------------
185 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
187 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
189 /*-----------------------------------------------------------------------
190 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
191 *-----------------------------------------------------------------------
192 * Reset PLL lock status sticky bit, timer expired status bit and timer
193 * interrupt status bit - leave PLL multiplication factor unchanged !
195 #define CFG_PLPRCR (CFG_PLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
197 /*-----------------------------------------------------------------------
198 * SCCR - System Clock and reset Control Register 15-27
199 *-----------------------------------------------------------------------
200 * Set clock output, timebase and RTC source and divider,
201 * power management and some other internal clocks
203 #define SCCR_MASK SCCR_EBDF11
204 #define CFG_SCCR (SCCR_TBS | \
205 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
206 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
209 /*-----------------------------------------------------------------------
211 *-----------------------------------------------------------------------
214 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
215 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
216 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
217 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
218 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
219 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
220 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
221 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
223 #define CFG_PCMCIA_INTERRUPT SIU_LEVEL6
225 /*-----------------------------------------------------------------------
227 *-----------------------------------------------------------------------
230 /*#define CFG_DER 0x2002000F*/
232 /*#define CFG_DER 0x02002000 */
236 * Init Memory Controller:
238 * BR0/1 and OR0/1 (FLASH)
241 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
242 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
244 /* used to re-map FLASH both when starting from SRAM or FLASH:
245 * restrict access enough to keep SRAM working (if any)
246 * but not too much to meddle with FLASH accesses
248 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
249 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
251 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
252 #define CFG_OR_TIMING_FLASH 0x00000160
253 /*(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
254 OR_SCY_5_CLK | OR_EHTR) */
256 #define CFG_OR0_REMAP 0x80000160 /*(CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)*/
257 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
258 #define CFG_BR0_PRELIM ( FLASH_BASE0_PRELIM | 0x00000801 )
260 #define CFG_OR1_REMAP CFG_OR0_REMAP
261 #define CFG_OR1_PRELIM CFG_OR0_PRELIM
262 #define CFG_BR1_PRELIM ( FLASH_BASE1_PRELIM | 0x00000801 )
265 * BR2/3 and OR2/3 (SDRAM)
268 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
269 #define SDRAM_BASE3_PRELIM 0x04000000 /* SDRAM bank #1 */
270 #define SDRAM_MAX_SIZE 0x02000000 /* max 32 MB per bank */
272 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
273 #define CFG_OR_TIMING_SDRAM 0x00000A00
275 #define CFG_OR2_PRELIM 0xFC000E00
276 #define CFG_BR2_PRELIM (SDRAM_BASE2_PRELIM | 0x00000081)
278 #define CFG_OR3_PRELIM CFG_OR2_PRELIM
279 #define CFG_BR3_PRELIM (SDRAM_BASE3_PRELIM | 0x00000081)
283 * Memory Periodic Timer Prescaler
286 /* periodic timer for refresh */
287 #define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
289 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
290 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
291 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
293 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
294 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
295 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
298 * MAMR settings for SDRAM
302 #define CFG_MAMR_8COL 0x18803112
303 #define CFG_MAMR_9COL 0x18803112 /* same as 8 column because its just easier to port with*/
307 * Internal Definitions
312 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
313 #define BOOTFLAG_WARM 0x02 /* Software reboot */
316 * Internal Definitions
320 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
321 #define BOOTFLAG_WARM 0x02 /* Software reboot */
323 #endif /* __CONFIG_H */