2 * A collection of structures, addresses, and values associated with
3 * the Motorola 860T FADS board. Copied from the MBX stuff.
4 * Magnus Damm added defines for 8xxrom and extended bd_info.
5 * Helmut Buchsbaum added bitvalues for BCSRx
7 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
11 * 1999-nov-26: The FADS is using the following physical memorymap:
13 * ff020000 -> ff02ffff : pcmcia
14 * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxrom
15 * ff000000 -> ff00ffff : IMAP internal in the cpu
16 * fe000000 -> ffnnnnnn : flash connected to CS0, setup by 8xxrom
17 * 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom
20 /* ------------------------------------------------------------------------- */
23 * board/config.h - configuration options, board specific
30 * High Level Configuration Options
33 #include <mpc8xx_irq.h>
35 #define CONFIG_MPC850 1
36 #define CONFIG_MPC850SAR 1
39 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40 #undef CONFIG_8xx_CONS_SMC2
41 #undef CONFIG_8xx_CONS_NONE
42 #define CONFIG_BAUDRATE 9600
45 #define MPC8XX_FACT 10 /* Multiply by 10 */
46 #define MPC8XX_XIN 50000000 /* 50 MHz in */
48 #define MPC8XX_FACT 12 /* Multiply by 12 */
49 #define MPC8XX_XIN 4000000 /* 4 MHz in */
51 #define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
53 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
56 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
58 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
61 #define CONFIG_BOOTCOMMAND "bootm 02880000" /* autoboot command */
62 #define CONFIG_BOOTARGS " "
64 #undef CONFIG_WATCHDOG /* watchdog disabled */
66 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
67 #include <cmd_confdefs.h>
70 * Miscellaneous configurable options
72 #undef CFG_LONGHELP /* undef to save memory */
73 #define CFG_PROMPT ":>" /* Monitor Command Prompt */
74 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
75 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
77 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
79 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
80 #define CFG_MAXARGS 16 /* max number of command args */
81 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
83 #define CFG_MEMTEST_START 0x00004000 /* memtest works on */
84 #define CFG_MEMTEST_END 0x00800000 /* 0 ... 8 MB in DRAM */
86 #define CFG_LOAD_ADDR 0x00100000 /* default load address */
88 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
90 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
93 * Low Level Configuration Settings
94 * (address mappings, register initial values, etc.)
95 * You should know what you are doing if you make changes here.
97 /*-----------------------------------------------------------------------
98 * Internal Memory Mapped Register
100 #define CFG_IMMR 0xFF000000
101 #define CFG_IMMR_SIZE ((uint)(64 * 1024))
103 /*-----------------------------------------------------------------------
104 * Definitions for initial stack pointer and data area (in DPRAM)
106 #define CFG_INIT_RAM_ADDR CFG_IMMR
107 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
108 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
109 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
110 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
112 /*-----------------------------------------------------------------------
113 * Start addresses for the final memory configuration
114 * (Set up by the startup code)
115 * Please note that CFG_SDRAM_BASE _must_ start at 0
116 * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
118 #define CFG_SDRAM_BASE 0x00000000
119 #define CFG_SDRAM_SIZE (4<<20) /* standard FADS has 4M */
120 #define CFG_FLASH_BASE 0x02800000
121 #define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
123 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */
125 #define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
127 #define CFG_MONITOR_BASE CFG_FLASH_BASE
128 #define CFG_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */
131 * For booting Linux, the board info and command line data
132 * have to be in the first 8 MB of memory, since this is
133 * the maximum mapped by the Linux kernel during initialization.
135 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
136 /*-----------------------------------------------------------------------
139 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
140 #define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
142 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
143 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
145 #define CFG_ENV_IS_IN_FLASH 1
146 #define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
147 #define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
149 /*-----------------------------------------------------------------------
150 * Cache Configuration
152 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
153 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
154 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
157 /*-----------------------------------------------------------------------
158 * SYPCR - System Protection Control 11-9
159 * SYPCR can only be written once after reset!
160 *-----------------------------------------------------------------------
161 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
163 #if defined(CONFIG_WATCHDOG)
164 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
165 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
167 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
170 /*-----------------------------------------------------------------------
171 * SIUMCR - SIU Module Configuration 11-6
172 *-----------------------------------------------------------------------
173 * PCMCIA config., multi-function pin tri-state
175 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
177 /*-----------------------------------------------------------------------
178 * TBSCR - Time Base Status and Control 11-26
179 *-----------------------------------------------------------------------
180 * Clear Reference Interrupt Status, Timebase freezing enabled
182 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
184 /*-----------------------------------------------------------------------
185 * PISCR - Periodic Interrupt Status and Control 11-31
186 *-----------------------------------------------------------------------
187 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
189 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
191 /*-----------------------------------------------------------------------
192 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
193 *-----------------------------------------------------------------------
194 * Reset PLL lock status sticky bit, timer expired status bit and timer *
195 * interrupt status bit - leave PLL multiplication factor unchanged !
197 #define CFG_PLPRCR (((MPC8XX_FACT-1) << 20) | \
198 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
200 /*-----------------------------------------------------------------------
201 * SCCR - System Clock and reset Control Register 15-27
202 *-----------------------------------------------------------------------
203 * Set clock output, timebase and RTC source and divider,
204 * power management and some other internal clocks
206 #define SCCR_MASK SCCR_EBDF11
207 #define CFG_SCCR (SCCR_TBS | \
208 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
209 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
212 /*-----------------------------------------------------------------------
214 *-----------------------------------------------------------------------
219 /* Because of the way the 860 starts up and assigns CS0 the
220 * entire address space, we have to set the memory controller
221 * differently. Normally, you write the option register
222 * first, and then enable the chip select by writing the
223 * base register. For CS0, you must write the base register
224 * first, followed by the option register.
228 * Init Memory Controller:
230 * BR0/1 and OR0/1 (FLASH)
232 /* the other CS:s are determined by looking at parameters in BCSRx */
235 #define BCSR_ADDR ((uint) 0x02100000)
236 #define BCSR_SIZE ((uint)(64 * 1024))
238 #define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */
239 #define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */
241 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
242 #define CFG_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */
244 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
245 #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
247 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
248 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
249 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
251 /* BCSRx - Board Control and Status Registers */
252 #define CFG_OR1_REMAP CFG_OR0_REMAP
253 #define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
254 #define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V )
258 * Memory Periodic Timer Prescaler
261 /* periodic timer for refresh */
262 #define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
264 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
265 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
266 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
268 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
269 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
270 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
273 * MAMR settings for SDRAM
277 #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
278 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
279 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
281 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
282 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
283 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
285 #define CFG_MAMR 0x13a01114
287 * Internal Definitions
291 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
292 #define BOOTFLAG_WARM 0x02 /* Software reboot */
295 /* values according to the manual */
298 #define PCMCIA_MEM_ADDR ((uint)0xff020000)
299 #define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
301 #define BCSR0 ((uint) (BCSR_ADDR + 00))
302 #define BCSR1 ((uint) (BCSR_ADDR + 0x04))
303 #define BCSR2 ((uint) (BCSR_ADDR + 0x08))
304 #define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
305 #define BCSR4 ((uint) (BCSR_ADDR + 0x10))
307 /* FADS bitvalues by Helmut Buchsbaum
308 * see MPC8xxADS User's Manual for a proper description
309 * of the following structures
312 #define BCSR0_ERB ((uint)0x80000000)
313 #define BCSR0_IP ((uint)0x40000000)
314 #define BCSR0_BDIS ((uint)0x10000000)
315 #define BCSR0_BPS_MASK ((uint)0x0C000000)
316 #define BCSR0_ISB_MASK ((uint)0x01800000)
317 #define BCSR0_DBGC_MASK ((uint)0x00600000)
318 #define BCSR0_DBPC_MASK ((uint)0x00180000)
319 #define BCSR0_EBDF_MASK ((uint)0x00060000)
321 #define BCSR1_FLASH_EN ((uint)0x80000000)
322 #define BCSR1_DRAM_EN ((uint)0x40000000)
323 #define BCSR1_ETHEN ((uint)0x20000000)
324 #define BCSR1_IRDEN ((uint)0x10000000)
325 #define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
326 #define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
327 #define BCSR1_BCSR_EN ((uint)0x02000000)
328 #define BCSR1_RS232EN_1 ((uint)0x01000000)
329 #define BCSR1_PCCEN ((uint)0x00800000)
330 #define BCSR1_PCCVCC0 ((uint)0x00400000)
331 #define BCSR1_PCCVPP_MASK ((uint)0x00300000)
332 #define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
333 #define BCSR1_RS232EN_2 ((uint)0x00040000)
334 #define BCSR1_SDRAM_EN ((uint)0x00020000)
335 #define BCSR1_PCCVCC1 ((uint)0x00010000)
337 #define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
338 #define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
339 #define BCSR2_DRAM_PD_SHIFT (23)
340 #define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
341 #define BCSR2_DBREVNR_MASK ((uint)0x00030000)
343 #define BCSR3_DBID_MASK ((ushort)0x3800)
344 #define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
345 #define BCSR3_BREVNR0 ((ushort)0x0080)
346 #define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
347 #define BCSR3_BREVN1 ((ushort)0x0008)
348 #define BCSR3_BREVN2_MASK ((ushort)0x0003)
350 #define BCSR4_ETHLOOP ((uint)0x80000000)
351 #define BCSR4_TFPLDL ((uint)0x40000000)
352 #define BCSR4_TPSQEL ((uint)0x20000000)
353 #define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
355 #define BCSR4_USB_EN ((uint)0x08000000)
356 #endif /* CONFIG_MPC823 */
357 #ifdef CONFIG_MPC860SAR
358 #define BCSR4_UTOPIA_EN ((uint)0x08000000)
359 #endif /* CONFIG_MPC860SAR */
360 #ifdef CONFIG_MPC860T
361 #define BCSR4_FETH_EN ((uint)0x08000000)
362 #endif /* CONFIG_MPC860T */
364 #define BCSR4_USB_SPEED ((uint)0x04000000)
365 #endif /* CONFIG_MPC823 */
366 #ifdef CONFIG_MPC860T
367 #define BCSR4_FETHCFG0 ((uint)0x04000000)
368 #endif /* CONFIG_MPC860T */
370 #define BCSR4_VCCO ((uint)0x02000000)
371 #endif /* CONFIG_MPC823 */
372 #ifdef CONFIG_MPC860T
373 #define BCSR4_FETHFDE ((uint)0x02000000)
374 #endif /* CONFIG_MPC860T */
376 #define BCSR4_VIDEO_ON ((uint)0x00800000)
377 #endif /* CONFIG_MPC823 */
379 #define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
380 #endif /* CONFIG_MPC823 */
381 #ifdef CONFIG_MPC860T
382 #define BCSR4_FETHCFG1 ((uint)0x00400000)
383 #endif /* CONFIG_MPC860T */
385 #define BCSR4_VIDEO_RST ((uint)0x00200000)
386 #endif /* CONFIG_MPC823 */
387 #ifdef CONFIG_MPC860T
388 #define BCSR4_FETHRST ((uint)0x00200000)
389 #endif /* CONFIG_MPC860T */
390 #define BCSR4_MODEM_EN ((uint)0x00100000)
391 #define BCSR4_DATA_VOICE ((uint)0x00080000)
393 #define CONFIG_DRAM_50MHZ 1
394 #define CONFIG_SDRAM_50MHZ
396 #ifdef CONFIG_MPC860T
398 /* Interrupt level assignments.
400 #define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
402 #endif /* CONFIG_MPC860T */
404 /* We don't use the 8259.
406 #define NR_8259_INTS 0
410 #define _MACH_8xx (_MACH_fads)
412 #define CONFIG_DISK_SPINUP_TIME 1000000
415 /* PCMCIA configuration */
417 #define PCMCIA_MAX_SLOTS 2
420 #define PCMCIA_SLOT_A 1
423 #endif /* __CONFIG_H */