3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_405EP 1 /* This is a PPC405 CPU */
37 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
38 #define CONFIG_G2000 1 /* ...on a PLU405 board */
40 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
41 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
43 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
46 #define CONFIG_BAUDRATE 115200
48 #define CONFIG_BAUDRATE 9600
51 #define CONFIG_PREBOOT
53 #undef CONFIG_BOOTARGS
55 #define CONFIG_EXTRA_ENV_SETTINGS \
56 "nfsargs=setenv bootargs root=/dev/nfs rw " \
57 "nfsroot=${serverip}:${rootpath}\0" \
58 "ramargs=setenv bootargs root=/dev/ram rw\0" \
59 "addip=setenv bootargs ${bootargs} " \
60 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
61 ":${hostname}:${netdev}:off\0" \
62 "addmisc=setenv bootargs ${bootargs} " \
63 "console=ttyS0,${baudrate} " \
65 "flash_nfs=run nfsargs addip addmisc;" \
66 "bootm ${kernel_addr}\0" \
67 "flash_self=run ramargs addip addmisc;" \
68 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
69 "net_nfs=tftp 200000 ${bootfile};" \
70 "run nfsargs addip addmisc;bootm\0" \
71 "rootpath=/opt/eldk/ppc_4xx\0" \
72 "bootfile=/tftpboot/g2000/pImage\0" \
73 "kernel_addr=ff800000\0" \
74 "ramdisk_addr=ff900000\0" \
75 "pciconfighost=yes\0" \
77 #define CONFIG_BOOTCOMMAND "run net_nfs"
79 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
81 #define CONFIG_NET_MULTI 1
83 #define CONFIG_MII 1 /* MII PHY management */
84 #define CONFIG_PHY_ADDR 0 /* PHY address */
85 #define CONFIG_PHY1_ADDR 1 /* PHY address */
88 #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
93 * Command line configuration.
95 #include <config_cmd_default.h>
97 #define CONFIG_CMD_DHCP
98 #define CONFIG_CMD_PCI
99 #define CONFIG_CMD_IRQ
100 #define CONFIG_CMD_ELF
101 #define CONFIG_CMD_DATE
102 #define CONFIG_CMD_I2C
103 #define CONFIG_CMD_MII
104 #define CONFIG_CMD_PING
105 #define CONFIG_CMD_BSP
106 #define CONFIG_CMD_EEPROM
109 #undef CONFIG_WATCHDOG /* watchdog disabled */
111 #if 0 /* test-only */
112 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
116 * Miscellaneous configurable options
118 #define CFG_LONGHELP /* undef to save memory */
119 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
121 #undef CFG_HUSH_PARSER /* use "hush" command parser */
122 #ifdef CFG_HUSH_PARSER
123 #define CFG_PROMPT_HUSH_PS2 "> "
126 #if defined(CONFIG_CMD_KGDB)
127 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
129 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
131 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
132 #define CFG_MAXARGS 16 /* max number of command args */
133 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
135 #define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
137 #define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
139 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
141 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
142 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
144 #undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
145 #define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
146 #define CFG_BASE_BAUD 691200
147 #undef CONFIG_UART1_CONSOLE /* define for uart1 as console */
149 /* The following table includes the supported baudrates */
150 #define CFG_BAUDRATE_TABLE \
151 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
152 57600, 115200, 230400, 460800, 921600 }
154 #define CFG_LOAD_ADDR 0x100000 /* default load address */
155 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
157 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
159 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
160 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
162 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
164 #define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
166 /*----------------------------------------------------------------------------*/
167 /* adding Ethernet setting: FTS OUI 00:11:0B */
168 /*----------------------------------------------------------------------------*/
169 #define CONFIG_ETHADDR 00:11:0B:00:00:01
170 #define CONFIG_HAS_ETH1
171 #define CONFIG_ETH1ADDR 00:11:0B:00:00:02
172 #define CONFIG_IPADDR 10.48.8.178
173 #define CONFIG_IP1ADDR 10.48.8.188
174 #define CONFIG_NETMASK 255.255.255.128
175 #define CONFIG_SERVERIP 10.48.8.138
177 /*-----------------------------------------------------------------------
179 *-----------------------------------------------------------------------
181 #define CONFIG_RTC_DS1337
182 #define CFG_I2C_RTC_ADDR 0x68
184 #if 0 /* test-only */
185 /*-----------------------------------------------------------------------
187 *-----------------------------------------------------------------------
189 #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
190 #define SECTORSIZE 512
192 #define ADDR_COLUMN 1
194 #define ADDR_COLUMN_PAGE 3
196 #define NAND_ChipID_UNKNOWN 0x00
197 #define NAND_MAX_FLOORS 1
198 #define NAND_MAX_CHIPS 1
200 #define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
201 #define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
202 #define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
203 #define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
205 #define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
206 #define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
207 #define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
208 #define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
209 #define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
210 #define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
211 #define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
213 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
214 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
215 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
216 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
219 /*-----------------------------------------------------------------------
221 *-----------------------------------------------------------------------
223 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
224 #define PCI_HOST_FORCE 1 /* configure as pci host */
225 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
227 #define CONFIG_PCI /* include pci support */
228 #define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
229 #define CONFIG_PCI_PNP /* do pci plug-and-play */
230 /* resource configuration */
232 #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
234 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
236 #define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
237 #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
238 #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
239 #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
240 #define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
241 #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
242 #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
243 #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
244 #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
247 * For booting Linux, the board info and command line data
248 * have to be in the first 8 MB of memory, since this is
249 * the maximum mapped by the Linux kernel during initialization.
251 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
253 /*-----------------------------------------------------------------------
257 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
258 #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
259 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
260 #undef CFG_FLASH_PROTECTION /* don't use hardware protection */
261 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
262 #define CFG_FLASH_BASE 0xFE000000 /* test-only...*/
263 #define CFG_FLASH_INCREMENT 0x01000000 /* test-only */
265 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
266 #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
267 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
268 #undef CFG_FLASH_PROTECTION /* don't use hardware protection */
269 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
270 #define CFG_FLASH_BASE 0xFF800000 /* test-only...*/
271 #define CFG_FLASH_INCREMENT 0x01000000 /* test-only */
274 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
276 #define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
277 #define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains u-boot */
279 /*-----------------------------------------------------------------------
280 * Start addresses for the final memory configuration
281 * (Set up by the startup code)
282 * Please note that CFG_SDRAM_BASE _must_ start at 0
284 #define CFG_SDRAM_BASE 0x00000000
285 #define CFG_MONITOR_BASE 0xFFFC0000
286 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
287 #define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
289 /*-----------------------------------------------------------------------
290 * Environment Variable setup
292 #if 1 /* test-only */
293 #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
294 #define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
295 #define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
296 /* total size of a CAT24WC16 is 2048 bytes */
298 #else /* DEFAULT: environment in flash, using redundand flash sectors */
300 #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
301 #define CFG_ENV_ADDR 0xFFFA0000 /* environment starts before u-boot */
302 #define CFG_ENV_SECT_SIZE 0x20000 /* 128k bytes may be used for env vars*/
306 /*-----------------------------------------------------------------------
307 * I2C EEPROM (CAT24WC16) for environment
309 #define CONFIG_HARD_I2C /* I2c with hardware support */
310 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
311 #define CFG_I2C_SLAVE 0x7F
313 #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
314 /* CAT24WC08/16... */
315 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
316 /* mask of address bits that overflow into the "EEPROM chip address" */
317 #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
318 #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
319 /* 16 byte page write mode using*/
320 /* last 4 bits of the address */
321 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
322 #define CFG_EEPROM_PAGE_WRITE_ENABLE
324 /*-----------------------------------------------------------------------
325 * Cache Configuration
327 #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
328 /* have only 8kB, 16kB is save here */
329 #define CFG_CACHELINE_SIZE 32 /* ... */
330 #if defined(CONFIG_CMD_KGDB)
331 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
334 /*-----------------------------------------------------------------------
335 * External Bus Controller (EBC) Setup
338 /* Memory Bank 0 (Intel Strata Flash) initialization */
339 #define CFG_EBC_PB0AP 0x92015480
340 #define CFG_EBC_PB0CR 0xFF87A000 /* BAS=0xFF8,BS=08MB,BU=R/W,BW=16bit*/
342 /* Memory Bank 1 ( Power TAU) initialization */
343 /* #define CFG_EBC_PB1AP 0x04041000 */
344 /* #define CFG_EBC_PB1CR 0xF0018000 */ /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
345 #define CFG_EBC_PB1AP 0x00000000
346 #define CFG_EBC_PB1CR 0x00000000
348 /* Memory Bank 2 (Intel Flash) initialization */
349 #define CFG_EBC_PB2AP 0x00000000
350 #define CFG_EBC_PB2CR 0x00000000
352 /* Memory Bank 3 (NAND) initialization */
353 #define CFG_EBC_PB3AP 0x92015480
354 #define CFG_EBC_PB3CR 0xF40B8000 /*addr 0xF40, BS=32M,BU=R/W, BW=8bit */
356 /* Memory Bank 4 (FPGA regs) initialization */
357 #define CFG_EBC_PB4AP 0x00000000
358 #define CFG_EBC_PB4CR 0x00000000 /* leave it blank */
360 #define CFG_NAND_BASE 0xF4000000
362 /*-----------------------------------------------------------------------
363 * Definitions for initial stack pointer and data area (in data cache)
365 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
366 #define CFG_TEMP_STACK_OCM 1
368 /* On Chip Memory location */
369 #define CFG_OCM_DATA_ADDR 0xF8000000
370 #define CFG_OCM_DATA_SIZE 0x1000
371 #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
372 #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
374 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
375 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
376 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
378 /*-----------------------------------------------------------------------
379 * Definitions for GPIO setup (PPC405EP specific)
381 * GPIO0[0] - External Bus Controller BLAST output
382 * GPIO0[1-9] - Instruction trace outputs
383 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
384 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
385 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
386 * GPIO0[24-27] - UART0 control signal inputs/outputs
387 * GPIO0[28-29] - UART1 data signal input/output
388 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
390 * following GPIO setting changed for G20000, 080304
392 #define CFG_GPIO0_OSRH 0x40005555
393 #define CFG_GPIO0_OSRL 0x40000110
394 #define CFG_GPIO0_ISR1H 0x00000000
395 #define CFG_GPIO0_ISR1L 0x15555445
396 #define CFG_GPIO0_TSRH 0x00000000
397 #define CFG_GPIO0_TSRL 0x00000000
398 #define CFG_GPIO0_TCR 0xF7FF8014
401 * Internal Definitions
405 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
406 #define BOOTFLAG_WARM 0x02 /* Software reboot */
409 * Default speed selection (cpu_plb_opb_ebc) in mhz.
410 * This value will be set if iic boot eprom is disabled.
413 #define PLLMR0_DEFAULT PLLMR0_266_66_33_33
414 #define PLLMR1_DEFAULT PLLMR1_266_66_33_33
417 #define PLLMR0_DEFAULT PLLMR0_266_133_66_33
418 #define PLLMR1_DEFAULT PLLMR1_266_133_66_33
421 #define PLLMR0_DEFAULT PLLMR0_200_100_50_33
422 #define PLLMR1_DEFAULT PLLMR1_200_100_50_33
425 #define PLLMR0_DEFAULT PLLMR0_133_66_66_33
426 #define PLLMR1_DEFAULT PLLMR1_133_66_66_33
429 #endif /* __CONFIG_H */