git.sur5r.net Git - u-boot/blob - include/configs/GEN860T.h

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  * Keith Outwater, keith_outwater@mvis.com
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * board/config_GEN860T.h - board specific configuration options
  27  */
  28
  29 #ifndef __CONFIG_GEN860T_H
  30 #define __CONFIG_H
  31
  32 /*
  33  * High Level Configuration Options
  34  */
  35 #define CONFIG_MPC860
  36 #define CONFIG_GEN860T
  37
  38 #define CONFIG_SYS_TEXT_BASE            0x40000000
  39
  40 /*
  41  * Identify the board
  42  */
  43 #if !defined(CONFIG_SC)
  44 #define CONFIG_IDENT_STRING             " B2"
  45 #else
  46 #define CONFIG_IDENT_STRING             " SC"
  47 #endif
  48
  49 /*
  50  * Don't depend on the RTC clock to determine clock frequency -
  51  * the 860's internal rtc uses a 32.768 KHz clock which is
  52  * generated by the DS1337 - and the DS1337 clock can be turned off.
  53  */
  54 #if !defined(CONFIG_SC)
  55 #define CONFIG_8xx_GCLK_FREQ            66600000
  56 #else
  57 #define CONFIG_8xx_GCLK_FREQ            48000000
  58 #endif
  59
  60 /*
  61  * The RS-232 console port is on SMC1
  62  */
  63 #define CONFIG_8xx_CONS_SMC1
  64 #define CONFIG_BAUDRATE                 38400
  65
  66 /*
  67  * Print console information
  68  */
  69 #undef   CONFIG_SYS_CONSOLE_INFO_QUIET
  70
  71 /*
  72  * Set the autoboot delay in seconds.  A delay of -1 disables autoboot
  73  */
  74 #define CONFIG_BOOTDELAY                                5
  75
  76 /*
  77  * Pass the clock frequency to the Linux kernel in units of MHz
  78  */
  79 #define CONFIG_CLOCKS_IN_MHZ
  80
  81 #define CONFIG_PREBOOT          \
  82         "echo;echo"
  83
  84 #undef  CONFIG_BOOTARGS
  85 #define CONFIG_BOOTCOMMAND      \
  86         "bootp;" \
  87         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
  88         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
  89         "bootm"
  90
  91 /*
  92  * Turn off echo for serial download by default.  Allow baud rate to be changed
  93  * for downloads
  94  */
  95 #undef  CONFIG_LOADS_ECHO
  96 #define CONFIG_SYS_LOADS_BAUD_CHANGE
  97
  98 /*
  99  * Turn off the watchdog timer
 100  */
 101 #undef  CONFIG_WATCHDOG
 102
 103 /*
 104  * Do not reboot if a panic occurs
 105  */
 106 #define CONFIG_PANIC_HANG
 107
 108 /*
 109  * Enable the status LED
 110  */
 111 #define CONFIG_STATUS_LED
 112
 113 /*
 114  * Reset address. We pick an address such that when an instruction
 115  * is executed at that address, a machine check exception occurs
 116  */
 117 #define CONFIG_SYS_RESET_ADDRESS                                ((ulong) -1)
 118
 119 /*
 120  * BOOTP options
 121  */
 122 #define CONFIG_BOOTP_SUBNETMASK
 123 #define CONFIG_BOOTP_GATEWAY
 124 #define CONFIG_BOOTP_HOSTNAME
 125 #define CONFIG_BOOTP_BOOTPATH
 126 #define CONFIG_BOOTP_BOOTFILESIZE
 127
 128
 129 /*
 130  * The GEN860T network interface uses the on-chip 10/100 FEC with
 131  * an Intel LXT971A PHY connected to the 860T's MII. The PHY's
 132  * MII address is hardwired on the board to zero.
 133  */
 134 #define CONFIG_FEC_ENET
 135 #define CONFIG_SYS_DISCOVER_PHY
 136 #define CONFIG_MII
 137 #define CONFIG_MII_INIT                 1
 138 #define CONFIG_PHY_ADDR                 0
 139
 140 /*
 141  * Set default IP stuff just to get bootstrap entries into the
 142  * environment so that we can source the full default environment.
 143  */
 144 #define CONFIG_ETHADDR                                  9a:52:63:15:85:25
 145 #define CONFIG_SERVERIP                                 10.0.4.201
 146 #define CONFIG_IPADDR                                   10.0.4.111
 147
 148 /*
 149  * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to
 150  * the MPC860T I2C interface.
 151  */
 152 #define CONFIG_SYS_I2C_EEPROM_ADDR                              0x50
 153 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS               6               /* 64 byte pages                */
 154 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   12              /* 10 mS w/ 20% margin  */
 155 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN                  2               /* need 16 bit address  */
 156 #define CONFIG_ENV_EEPROM_SIZE                          (32 * 1024)
 157
 158 /*
 159  * Enable I2C and select the hardware/software driver
 160  */
 161 #define CONFIG_HARD_I2C         1                               /* CPM based I2C                        */
 162 #undef  CONFIG_SOFT_I2C                                         /* Bit-banged I2C                       */
 163
 164 #ifdef CONFIG_HARD_I2C
 165 #define CONFIG_SYS_I2C_SPEED            100000                  /* clock speed in Hz            */
 166 #define CONFIG_SYS_I2C_SLAVE            0xFE                    /* I2C slave address            */
 167 #endif
 168
 169 #ifdef CONFIG_SOFT_I2C
 170 #define PB_SCL                          0x00000020              /* PB 26                                        */
 171 #define PB_SDA                          0x00000010              /* PB 27                                        */
 172 #define I2C_INIT                        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 173 #define I2C_ACTIVE                      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 174 #define I2C_TRISTATE            (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 175 #define I2C_READ                        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 176 #define I2C_SDA(bit)            if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 177                                                                 else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 178 #define I2C_SCL(bit)            if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 179                                                                 else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 180 #define I2C_DELAY                       udelay(5)               /* 1/4 I2C clock duration       */
 181 #endif
 182
 183 /*
 184  * Allow environment overwrites by anyone
 185  */
 186 #define CONFIG_ENV_OVERWRITE
 187
 188 #if !defined(CONFIG_SC)
 189 /*
 190  * The MPC860's internal RTC is horribly broken in rev D masks. Three
 191  * internal MPC860T circuit nodes were inadvertently left floating; this
 192  * causes KAPWR current in power down mode to be three orders of magnitude
 193  * higher than specified in the datasheet (from 10 uA to 10 mA).  No
 194  * reasonable battery can keep that kind RTC running during powerdown for any
 195  * length of time, so we use an external RTC on the I2C bus instead.
 196  */
 197 #define CONFIG_RTC_DS1337
 198 #define CONFIG_SYS_I2C_RTC_ADDR                         0x68
 199
 200 #else
 201 /*
 202  * No external RTC on SC variant, so we're stuck with the internal one.
 203  */
 204 #define CONFIG_RTC_MPC8xx
 205 #endif
 206
 207 /*
 208  * Power On Self Test support
 209  */
 210 #define CONFIG_POST                       ( CONFIG_SYS_POST_CACHE               | \
 211                                                                 CONFIG_SYS_POST_MEMORY          | \
 212                                                                 CONFIG_SYS_POST_CPU             | \
 213                                                                 CONFIG_SYS_POST_UART            | \
 214                                                                 CONFIG_SYS_POST_SPR )
 215
 216
 217 /*
 218  * Command line configuration.
 219  */
 220 #include <config_cmd_default.h>
 221
 222 #define CONFIG_CMD_ASKENV
 223 #define CONFIG_CMD_DHCP
 224 #define CONFIG_CMD_I2C
 225 #define CONFIG_CMD_EEPROM
 226 #define CONFIG_CMD_REGINFO
 227 #define CONFIG_CMD_IMMAP
 228 #define CONFIG_CMD_ELF
 229 #define CONFIG_CMD_DATE
 230 #define CONFIG_CMD_FPGA
 231 #define CONFIG_CMD_MII
 232 #define CONFIG_CMD_BEDBUG
 233
 234 #ifdef CONFIG_POST
 235 #define CONFIG_CMD_DIAG
 236 #endif
 237
 238 /*
 239  * There is no IDE/PCMCIA hardware support on the board.
 240  */
 241 #undef  CONFIG_IDE_PCMCIA
 242 #undef  CONFIG_IDE_LED
 243 #undef  CONFIG_IDE_RESET
 244
 245 /*
 246  * Enable the call to misc_init_r() for miscellaneous platform
 247  * dependent initialization.
 248  */
 249 #define CONFIG_MISC_INIT_R
 250
 251 /*
 252  * Enable call to last_stage_init() so we can twiddle some LEDS :)
 253  */
 254 #define CONFIG_LAST_STAGE_INIT
 255
 256 /*
 257  * Virtex2 FPGA configuration support
 258  */
 259 #define CONFIG_FPGA_COUNT               1
 260 #define CONFIG_FPGA
 261 #define CONFIG_FPGA_XILINX
 262 #define CONFIG_FPGA_VIRTEX2
 263 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 264
 265 /*
 266  * Verbose help from command monitor.
 267  */
 268 #define CONFIG_SYS_LONGHELP
 269 #if !defined(CONFIG_SC)
 270 #define CONFIG_SYS_PROMPT                       "B2> "
 271 #else
 272 #define CONFIG_SYS_PROMPT                       "SC> "
 273 #endif
 274
 275
 276 /*
 277  * Use the "hush" command parser
 278  */
 279 #define CONFIG_SYS_HUSH_PARSER
 280
 281 /*
 282  * Set buffer size for console I/O
 283  */
 284 #if defined(CONFIG_CMD_KGDB)
 285 #define CONFIG_SYS_CBSIZE                       1024
 286 #else
 287 #define CONFIG_SYS_CBSIZE                       256
 288 #endif
 289
 290 /*
 291  * Print buffer size
 292  */
 293 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 294
 295 /*
 296  * Maximum number of arguments that a command can accept
 297  */
 298 #define CONFIG_SYS_MAXARGS                      16
 299
 300 /*
 301  * Boot argument buffer size
 302  */
 303 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 304
 305 /*
 306  * Default memory test range
 307  */
 308 #define CONFIG_SYS_MEMTEST_START        0x0100000
 309 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START  + (128 * 1024))
 310
 311 /*
 312  * Select the more full-featured memory test
 313  */
 314 #define CONFIG_SYS_ALT_MEMTEST
 315
 316 /*
 317  * Default load address
 318  */
 319 #define CONFIG_SYS_LOAD_ADDR            0x01000000
 320
 321 /*
 322  * Set decrementer frequency (1 ms ticks)
 323  */
 324 #define CONFIG_SYS_HZ                           1000
 325
 326 /*
 327  * Device memory map (after SDRAM remap to 0x0):
 328  *
 329  * CS           Device                          Base Addr       Size
 330  * ----------------------------------------------------
 331  * CS0*         Flash                           0x40000000      64 M
 332  * CS1*         SDRAM                           0x00000000      16 M
 333  * CS2*         Disk-On-Chip            0x50000000      32 K
 334  * CS3*         FPGA                            0x60000000      64 M
 335  * CS4*         SelectMap                       0x70000000      32 K
 336  * CS5*         Mil-Std 1553 I/F        0x80000000      32 K
 337  * CS6*         Unused
 338  * CS7*         Unused
 339  * IMMR         860T Registers          0xfff00000
 340  */
 341
 342 /*
 343  * Base addresses and block sizes
 344  */
 345 #define CONFIG_SYS_IMMR                 0xFF000000
 346
 347 #define SDRAM_BASE                      0x00000000
 348 #define SDRAM_SIZE                      (64 * 1024 * 1024)
 349
 350 #define FLASH_BASE                      0x40000000
 351 #define FLASH_SIZE                      (16 * 1024 * 1024)
 352
 353 #define DOC_BASE                        0x50000000
 354 #define DOC_SIZE                        (32 * 1024)
 355
 356 #define FPGA_BASE                       0x60000000
 357 #define FPGA_SIZE                       (64 * 1024 * 1024)
 358
 359 #define SELECTMAP_BASE          0x70000000
 360 #define SELECTMAP_SIZE          (32 * 1024)
 361
 362 #define M1553_BASE                      0x80000000
 363 #define M1553_SIZE                      (64 * 1024)
 364
 365 /*
 366  * Definitions for initial stack pointer and data area (in DPRAM)
 367  */
 368 #define CONFIG_SYS_INIT_RAM_ADDR                CONFIG_SYS_IMMR
 369 #define CONFIG_SYS_INIT_RAM_SIZE                0x2F00  /* Size of used area in DPRAM           */
 370 #define CONFIG_SYS_INIT_DATA_SIZE               64      /* # bytes reserved for initial data*/
 371 #define CONFIG_SYS_GBL_DATA_OFFSET              (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
 372 #define CONFIG_SYS_INIT_SP_OFFSET               CONFIG_SYS_GBL_DATA_OFFSET
 373
 374 /*
 375  * Start addresses for the final memory configuration
 376  * (Set up by the startup code)
 377  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 378  */
 379 #define CONFIG_SYS_SDRAM_BASE                   SDRAM_BASE
 380
 381 /*
 382  * FLASH organization
 383  */
 384 #define CONFIG_SYS_FLASH_BASE                   FLASH_BASE
 385 #define CONFIG_SYS_FLASH_SIZE                   FLASH_SIZE
 386 #define CONFIG_SYS_FLASH_SECT_SIZE              (128 * 1024)
 387 #define CONFIG_SYS_MAX_FLASH_BANKS              1
 388 #define CONFIG_SYS_MAX_FLASH_SECT               128
 389
 390 /*
 391  * The timeout values are for an entire chip and are in milliseconds.
 392  * Yes I know that the write timeout is huge.  Accroding to the
 393  * datasheet a single byte takes 630 uS (round to 1 ms) max at worst
 394  * case VCC and temp after 100K programming cycles.  It works out
 395  * to 280 minutes (might as well be forever).
 396  */
 397 #define CONFIG_SYS_FLASH_ERASE_TOUT     (CONFIG_SYS_MAX_FLASH_SECT * 5000)
 398 #define CONFIG_SYS_FLASH_WRITE_TOUT     (CONFIG_SYS_MAX_FLASH_SECT * 128 * 1024 * 1)
 399
 400 /*
 401  * Allow direct writes to FLASH from tftp transfers (** dangerous **)
 402  */
 403 #define CONFIG_SYS_DIRECT_FLASH_TFTP
 404
 405 /*
 406  * Reserve memory for U-Boot.
 407  */
 408 #define CONFIG_SYS_MAX_UBOOT_SECTS              4
 409 #define CONFIG_SYS_MONITOR_LEN                  (CONFIG_SYS_MAX_UBOOT_SECTS * CONFIG_SYS_FLASH_SECT_SIZE)
 410 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 411
 412 /*
 413  * Select environment placement.  NOTE that u-boot.lds must
 414  * be edited if this is changed!
 415  */
 416 #undef  CONFIG_ENV_IS_IN_FLASH
 417 #define CONFIG_ENV_IS_IN_EEPROM
 418
 419 #if defined(CONFIG_ENV_IS_IN_EEPROM)
 420 #define CONFIG_ENV_SIZE                 (2 * 1024)
 421 #define CONFIG_ENV_OFFSET                       (CONFIG_ENV_EEPROM_SIZE - (8 * 1024))
 422 #else
 423 #define CONFIG_ENV_SIZE                 0x1000
 424 #define CONFIG_ENV_SECT_SIZE            CONFIG_SYS_FLASH_SECT_SIZE
 425
 426 /*
 427  * This ultimately gets passed right into the linker script, so we have to
 428  * use a number :(
 429  */
 430 #define CONFIG_ENV_OFFSET                       0x060000
 431 #endif
 432
 433 /*
 434  * Reserve memory for malloc()
 435  */
 436 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)
 437
 438 /*
 439  * For booting Linux, the board info and command line data
 440  * have to be in the first 8 MB of memory, since this is
 441  * the maximum mapped by the Linux kernel during initialization.
 442  */
 443 #define CONFIG_SYS_BOOTMAPSZ            (8 * 1024 * 1024)
 444
 445 /*
 446  * Cache Configuration
 447  */
 448 #define CONFIG_SYS_CACHELINE_SIZE               16      /* For all MPC8xx CPUs                          */
 449 #if defined(CONFIG_CMD_KGDB)
 450 #define CONFIG_SYS_CACHELINE_SHIFT              4       /* log base 2 of above value            */
 451 #endif
 452
 453 /*------------------------------------------------------------------------
 454  * SYPCR - System Protection Control                                                    UM 11-9
 455  * -----------------------------------------------------------------------
 456  * SYPCR can only be written once after reset!
 457  *
 458  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 459  */
 460 #if defined(CONFIG_WATCHDOG)
 461 #define CONFIG_SYS_SYPCR        ( SYPCR_SWTC    | \
 462                                           SYPCR_BMT     | \
 463                                           SYPCR_BME     | \
 464                                           SYPCR_SWF     | \
 465                                           SYPCR_SWE     | \
 466                                           SYPCR_SWRI    | \
 467                                           SYPCR_SWP               \
 468                                         )
 469 #else
 470 #define CONFIG_SYS_SYPCR        ( SYPCR_SWTC    | \
 471                                           SYPCR_BMT     | \
 472                                           SYPCR_BME     | \
 473                                           SYPCR_SWF     | \
 474                                           SYPCR_SWP               \
 475                                         )
 476 #endif
 477
 478 /*-----------------------------------------------------------------------
 479  * SIUMCR - SIU Module Configuration                                                    UM 11-6
 480  *-----------------------------------------------------------------------
 481  * Set debug pin mux, enable SPKROUT and GPLB5*.
 482  */
 483 #define CONFIG_SYS_SIUMCR       ( SIUMCR_DBGC11 | \
 484                                           SIUMCR_DBPC11 | \
 485                                           SIUMCR_MLRC11 | \
 486                                           SIUMCR_GB5E     \
 487                                         )
 488
 489 /*-----------------------------------------------------------------------
 490  * TBSCR - Time Base Status and Control                                                 UM 11-26
 491  *-----------------------------------------------------------------------
 492  * Clear Reference Interrupt Status, Timebase freeze enabled
 493  */
 494 #define CONFIG_SYS_TBSCR        ( TBSCR_REFA | \
 495                                           TBSCR_REFB | \
 496                                           TBSCR_TBF        \
 497                                         )
 498
 499 /*-----------------------------------------------------------------------
 500  * RTCSC - Real-Time Clock Status and Control Register                  UM 11-27
 501  *-----------------------------------------------------------------------
 502  */
 503 #define CONFIG_SYS_RTCSC        ( RTCSC_SEC     | \
 504                                           RTCSC_ALR | \
 505                                           RTCSC_RTF | \
 506                                           RTCSC_RTE       \
 507                                         )
 508
 509 /*-----------------------------------------------------------------------
 510  * PISCR - Periodic Interrupt Status and Control                                UM 11-31
 511  *-----------------------------------------------------------------------
 512  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 513  */
 514 #define CONFIG_SYS_PISCR        ( PISCR_PS              | \
 515                                           PISCR_PITF      \
 516                                         )
 517
 518 /*-----------------------------------------------------------------------
 519  * PLPRCR - PLL, Low-Power, and Reset Control Register                  UM 15-30
 520  *-----------------------------------------------------------------------
 521  * Reset PLL lock status sticky bit, timer expired status bit and timer
 522  * interrupt status bit. Set MF for 1:2:1 mode.
 523  */
 524 #define CONFIG_SYS_PLPRCR       ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK)    | \
 525                                           PLPRCR_SPLSS  | \
 526                                           PLPRCR_TEXPS  | \
 527                                           PLPRCR_TMIST    \
 528                                         )
 529
 530 /*-----------------------------------------------------------------------
 531  * SCCR - System Clock and reset Control Register                               UM 15-27
 532  *-----------------------------------------------------------------------
 533  * Set clock output, timebase and RTC source and divider,
 534  * power management and some other internal clocks
 535  */
 536 #define SCCR_MASK   SCCR_EBDF11
 537
 538 #if !defined(CONFIG_SC)
 539 #define CONFIG_SYS_SCCR ( SCCR_TBS                      |       /* timebase = GCLK/2    */ \
 540                                           SCCR_COM00            |       /* full strength CLKOUT */ \
 541                                           SCCR_DFSYNC00 |       /* SYNCLK / 1 (normal)  */ \
 542                                           SCCR_DFBRG00          |       /* BRGCLK / 1 (normal)  */ \
 543                                           SCCR_DFNL000          | \
 544                                           SCCR_DFNH000            \
 545                                         )
 546 #else
 547 #define CONFIG_SYS_SCCR ( SCCR_TBS                      |       /* timebase = GCLK/2    */ \
 548                                           SCCR_COM00            |       /* full strength CLKOUT */ \
 549                                           SCCR_DFSYNC00 |       /* SYNCLK / 1 (normal)  */ \
 550                                           SCCR_DFBRG00          |       /* BRGCLK / 1 (normal)  */ \
 551                                           SCCR_DFNL000          | \
 552                                           SCCR_DFNH000          | \
 553                                           SCCR_RTDIV            | \
 554                                           SCCR_RTSEL              \
 555                                         )
 556 #endif
 557
 558 /*-----------------------------------------------------------------------
 559  * DER - Debug Enable Register                                                                  UM 37-46
 560  *-----------------------------------------------------------------------
 561  * Mask all events that can cause entry into debug mode
 562  */
 563 #define CONFIG_SYS_DER                          0
 564
 565 /*
 566  * Initialize Memory Controller:
 567  *
 568  * BR0 and OR0 (FLASH memory)
 569  */
 570 #define FLASH_BASE0_PRELIM      FLASH_BASE
 571
 572 /*
 573  * Flash address mask
 574  */
 575 #define CONFIG_SYS_PRELIM_OR_AM 0xfe000000
 576
 577 /*
 578  * FLASH timing:
 579  * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1
 580  */
 581 #define CONFIG_SYS_OR_TIMING_FLASH      ( OR_CSNT_SAM   | \
 582                                                           OR_ACS_DIV2   | \
 583                                                           OR_BI                 | \
 584                                                           OR_SCY_2_CLK  | \
 585                                                           OR_TRLX               | \
 586                                                           OR_EHTR                 \
 587                                                         )
 588
 589 #define CONFIG_SYS_OR0_PRELIM   ( CONFIG_SYS_PRELIM_OR_AM               | \
 590                                                   CONFIG_SYS_OR_TIMING_FLASH      \
 591                                                 )
 592
 593 #define CONFIG_SYS_BR0_PRELIM   ( (FLASH_BASE0_PRELIM & BR_BA_MSK)      | \
 594                                                   BR_MS_GPCM                                            | \
 595                                                   BR_PS_8                                                       | \
 596                                                   BR_V                                                            \
 597                                                 )
 598
 599 /*
 600  * SDRAM configuration
 601  */
 602 #define CONFIG_SYS_OR1_AM       0xfc000000
 603 #define CONFIG_SYS_OR1          ( (CONFIG_SYS_OR1_AM & OR_AM_MSK)       | \
 604                                           OR_CSNT_SAM                             \
 605                                         )
 606
 607 #define CONFIG_SYS_BR1          ( (SDRAM_BASE & BR_BA_MSK)      | \
 608                                           BR_MS_UPMA                            | \
 609                                           BR_PS_32                                      | \
 610                                           BR_V                                            \
 611                                         )
 612
 613 /*
 614  * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank
 615  * of 256 MBit SDRAM
 616  */
 617 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16
 618
 619 /*
 620  * Periodic timer for refresh @ 33 MHz system clock
 621  */
 622 #define CONFIG_SYS_MAMR_PTA     64
 623
 624 /*
 625  * MAMR settings for SDRAM
 626  */
 627 #define CONFIG_SYS_MAMR_8COL    ( (CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)       | \
 628                                                   MAMR_PTAE                             | \
 629                                                   MAMR_AMA_TYPE_1                       | \
 630                                                   MAMR_DSA_1_CYCL                       | \
 631                                                   MAMR_G0CLA_A10                        | \
 632                                                   MAMR_RLFA_1X                          | \
 633                                                   MAMR_WLFA_1X                          | \
 634                                                   MAMR_TLFA_4X                            \
 635                                                 )
 636
 637 /*
 638  * CS2* configuration for Disk On Chip:
 639  * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
 640  * no burst.
 641  */
 642 #define CONFIG_SYS_OR2_PRELIM   ( (0xffff0000 & OR_AM_MSK)      | \
 643                                                   OR_CSNT_SAM                           | \
 644                                                   OR_ACS_DIV2                           | \
 645                                                   OR_BI                                         | \
 646                                                   OR_SCY_2_CLK                          | \
 647                                                   OR_TRLX                                       | \
 648                                                   OR_EHTR                                         \
 649                                                 )
 650
 651 #define CONFIG_SYS_BR2_PRELIM   ( (DOC_BASE & BR_BA_MSK)        | \
 652                                                   BR_PS_8                                       | \
 653                                                   BR_MS_GPCM                            | \
 654                                                   BR_V                                            \
 655                                                 )
 656
 657 /*
 658  * CS3* configuration for FPGA:
 659  * 33 MHz bus with SCY=15, no burst.
 660  * The FPGA uses TA and TEA to terminate bus cycles, but we
 661  * clear SETA and set the cycle length to a large number so that
 662  * the cycle will still complete even if there is a configuration
 663  * error that prevents TA from asserting on FPGA accesss.
 664  */
 665 #define CONFIG_SYS_OR3_PRELIM   ( (0xfc000000 & OR_AM_MSK)  | \
 666                                                   OR_SCY_15_CLK                         | \
 667                                                   OR_BI                                   \
 668                                                 )
 669
 670 #define CONFIG_SYS_BR3_PRELIM   ( (FPGA_BASE & BR_BA_MSK)       | \
 671                                                   BR_PS_32                                      | \
 672                                                   BR_MS_GPCM                            | \
 673                                                   BR_V                                            \
 674                                                 )
 675 /*
 676  * CS4* configuration for FPGA SelectMap configuration interface.
 677  * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
 678  * of GCLK1_50
 679  */
 680 #define CONFIG_SYS_OR4_PRELIM   ( (0xffff0000 & OR_AM_MSK)      | \
 681                                                   OR_G5LS                                               | \
 682                                                   OR_BI                                                   \
 683                                                 )
 684
 685 #define CONFIG_SYS_BR4_PRELIM   ( (SELECTMAP_BASE & BR_BA_MSK)  | \
 686                                                   BR_PS_8                                               | \
 687                                                   BR_MS_UPMB                                    | \
 688                                                   BR_V                                                    \
 689                                                 )
 690
 691 /*
 692  * CS5* configuration for Mil-Std 1553 databus interface.
 693  * 33 MHz bus, GPCM, no burst.
 694  * The 1553 interface  uses TA and TEA to terminate bus cycles,
 695  * but we clear SETA and set the cycle length to a large number so that
 696  * the cycle will still complete even if there is a configuration
 697  * error that prevents TA from asserting on FPGA accesss.
 698  */
 699 #define CONFIG_SYS_OR5_PRELIM   ( (0xffff0000 & OR_AM_MSK)  | \
 700                                                   OR_SCY_15_CLK                         | \
 701                                                   OR_EHTR                                       | \
 702                                                   OR_TRLX                                       | \
 703                                                   OR_CSNT_SAM                           | \
 704                                                   OR_BI                                           \
 705                                                 )
 706
 707 #define CONFIG_SYS_BR5_PRELIM   ( (M1553_BASE & BR_BA_MSK)      | \
 708                                                   BR_PS_16                                      | \
 709                                                   BR_MS_GPCM                            | \
 710                                                   BR_V                                            \
 711                                                 )
 712
 713 /*
 714  * FEC interrupt assignment
 715  */
 716 #define FEC_INTERRUPT   SIU_LEVEL1
 717
 718 /*
 719  * Sanity checks
 720  */
 721 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
 722 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
 723 #endif
 724
 725 #endif  /* __CONFIG_GEN860T_H */