2 * (C) Copyright 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
31 #include <mpc8xx_irq.h>
35 # warning DEBUG Defined
39 * High Level Configuration Options
42 #define CONFIG_MPC860 1
43 #define CONFIG_IAD210 1 /* ...on a IAD210 module */
44 #define CONFIG_MPC860T 1
45 #define CONFIG_MPC862 1
47 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
49 #undef CONFIG_8xx_CONS_SMC1
50 #undef CONFIG_8xx_CONS_SMC2
51 #define CONFIG_8xx_CONS_SCC2 /* V24 on SCC2 */
52 #undef CONFIG_8xx_CONS_NONE
53 #define CONFIG_BAUDRATE 9600
56 # define MPC8XX_FACT 16
57 # define CONFIG_8xx_GCLK_FREQ (64000000L) /* define if can't use get_gclk_freq */
58 # define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
61 # define CONFIG_BOOTDELAY -1 /* autoboot disabled */
63 # define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
66 #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
68 /* using this define saves us updating another source file */
69 #define CONFIG_BOARD_EARLY_INIT_F 1
71 #undef CONFIG_BOOTARGS
72 /* #define CONFIG_BOOTCOMMAND \
74 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
75 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
79 #define CONFIG_BOOTCOMMAND \
80 "setenv bootargs root=/dev/nfs" \
81 "ip=192.168.28.129:139.10.137.138:192.168.28.1:255.255.255.0:iadlinux002::off; " \
83 #undef CONFIG_WATCHDOG /* watchdog disabled */
85 /* #define CONFIG_STATUS_LED 1*/ /* Status LED enabled */
87 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
89 # undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
90 # define CONFIG_FEC_ENET 1 /* use FEC ethernet */
92 # define CFG_DISCOVER_PHY 1
93 # define CONFIG_FEC_UTOPIA 1
94 # define CONFIG_ETHADDR 08:00:06:26:A2:6D
95 # define CONFIG_IPADDR 192.168.28.128
96 # define CONFIG_SERVERIP 139.10.137.138
97 # define CFG_DISCOVER_PHY 1
99 #define CONFIG_MAC_PARTITION
100 #define CONFIG_DOS_PARTITION
102 /* enable I2C and select the hardware/software driver */
103 #undef CONFIG_HARD_I2C /* I2C with hardware support */
104 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
105 # define CFG_I2C_SPEED 50000
106 # define CFG_I2C_SLAVE 0xDD
107 # define CFG_I2C_EEPROM_ADDR 0x50
109 * Software (bit-bang) I2C driver configuration
111 #define PB_SCL 0x00000020 /* PB 26 */
112 #define PB_SDA 0x00000010 /* PB 27 */
114 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
115 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
116 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
117 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
118 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
119 else immr->im_cpm.cp_pbdat &= ~PB_SDA
120 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
121 else immr->im_cpm.cp_pbdat &= ~PB_SCL
122 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
124 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
126 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
131 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
132 #include <cmd_confdefs.h>
135 * Miscellaneous configurable options
137 #define CFG_LONGHELP /* undef to save memory */
138 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
139 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
140 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
142 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
144 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
145 #define CFG_MAXARGS 16 /* max number of command args */
146 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
148 #define CFG_MEMTEST_START 0x0100000 /* memtest works on */
149 #define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
151 #define CFG_LOAD_ADDR 0x00100000
153 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
155 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
158 * Low Level Configuration Settings
159 * (address mappings, register initial values, etc.)
160 * You should know what you are doing if you make changes here.
162 /*-----------------------------------------------------------------------
163 * Internal Memory Mapped Register
165 #define CFG_IMMR 0xFFF00000
166 #define CFG_IMMR_SIZE ((uint)(64 * 1024))
168 /*-----------------------------------------------------------------------
169 * Definitions for initial stack pointer and data area (in DPRAM)
171 #define CFG_INIT_RAM_ADDR CFG_IMMR
172 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
173 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
174 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
175 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
177 /*-----------------------------------------------------------------------
178 * Start addresses for the final memory configuration
179 * (Set up by the startup code)
180 * Please note that CFG_SDRAM_BASE _must_ start at 0
182 #define CFG_SDRAM_BASE 0x00000000
183 #define CFG_FLASH_BASE 0x08000000
184 #define CFG_FLASH_SIZE ((uint)(4 * 1024 * 1024)) /* max 16Mbyte */
186 #define CFG_RESET_ADDRESS 0xFFF00100
189 # define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
191 # define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
194 # define CFG_MONITOR_BASE CFG_FLASH_BASE
195 # define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
198 * For booting Linux, the board info and command line data
199 * have to be in the first 8 MB of memory, since this is
200 * the maximum mapped by the Linux kernel during initialization.
202 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
203 /*-----------------------------------------------------------------------
206 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
207 #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
209 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
210 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
212 #define CFG_ENV_IS_IN_FLASH 1
213 #define CFG_ENV_OFFSET 0x8000
214 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
216 /*-----------------------------------------------------------------------
217 * Cache Configuration
219 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
220 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
221 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
224 /*-----------------------------------------------------------------------
225 * SYPCR - System Protection Control 11-9
226 * SYPCR can only be written once after reset!
227 *-----------------------------------------------------------------------
228 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
230 #if defined(CONFIG_WATCHDOG)
231 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
232 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
234 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
237 /*-----------------------------------------------------------------------
238 * SIUMCR - SIU Module Configuration 11-6
239 *-----------------------------------------------------------------------
240 * PCMCIA config., multi-function pin tri-state
242 #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
244 /*-----------------------------------------------------------------------
245 * TBSCR - Time Base Status and Control 11-26
246 *-----------------------------------------------------------------------
247 * Clear Reference Interrupt Status, Timebase freezing enabled
249 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
251 /*-----------------------------------------------------------------------
252 * PISCR - Periodic Interrupt Status and Control 11-31
253 *-----------------------------------------------------------------------
254 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
256 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
258 /*-----------------------------------------------------------------------
259 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
260 *-----------------------------------------------------------------------
261 * set the PLL, the low-power modes and the reset control (15-29)
263 #define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
264 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
266 /*-----------------------------------------------------------------------
267 * SCCR - System Clock and reset Control Register 15-27
268 *-----------------------------------------------------------------------
269 * Set clock output, timebase and RTC source and divider,
270 * power management and some other internal clocks
272 #define SCCR_MASK SCCR_EBDF11
274 #define CFG_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \
275 SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
276 SCCR_DFLCD000 |SCCR_DFALCD00 )
278 /*-----------------------------------------------------------------------
279 * RCCR - RISC Controller Configuration Register 19-4
280 *-----------------------------------------------------------------------
282 /* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */
283 #define CFG_RCCR 0x0020
285 /*-----------------------------------------------------------------------
287 *-----------------------------------------------------------------------
289 #define PCMCIA_MEM_ADDR ((uint)0xff020000)
290 #define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
292 /*-----------------------------------------------------------------------
294 *-----------------------------------------------------------------------
299 /* Because of the way the 860 starts up and assigns CS0 the
300 * entire address space, we have to set the memory controller
301 * differently. Normally, you write the option register
302 * first, and then enable the chip select by writing the
303 * base register. For CS0, you must write the base register
304 * first, followed by the option register.
308 * Init Memory Controller:
310 * BR0 and OR0 (FLASH)
313 #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
315 /* used to re-map FLASH both when starting from SRAM or FLASH:
316 * restrict access enough to keep SRAM working (if any)
317 * but not too much to meddle with FLASH accesses
319 #define CFG_REMAP_OR_AM 0xF8000000 /* OR addr mask */
320 #define CFG_PRELIM_OR_AM 0xF8000000 /* OR addr mask */
323 TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
324 #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | \
325 OR_SCY_3_CLK | OR_EHTR)
327 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
328 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
331 * BR2/3 and OR2/3 (SDRAM)
334 #define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM bank #0 */
335 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
337 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
339 #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | OR_CSNT_SAM | OR_BI | OR_ACS_DIV4)
340 #define CFG_BR2_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
341 #define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
344 * Memory Periodic Timer Prescaler
347 /* periodic timer for refresh */
348 #define CFG_MAMR_PTA 124 /* start with divider for 64 MHz */
350 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
351 #define CFG_MPTPR MPTPR_PTP_DIV32 /* setting for 1 bank */
354 * MAMR settings for SDRAM
357 #define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
358 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
359 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_8X)
363 * Internal Definitions
367 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
368 #define BOOTFLAG_WARM 0x02 /* Software reboot */
370 #ifdef CONFIG_MPC860T
372 /* Interrupt level assignments.
374 #define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
376 #endif /* CONFIG_MPC860T */
379 #endif /* __CONFIG_H */