2 * (C) Copyright 2001-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
31 #include <mpc8xx_irq.h>
34 * High Level Configuration Options
37 #define CONFIG_MPC860 1
38 #define CONFIG_MPC860T 1
39 #define CONFIG_ICU862 1
40 #define CONFIG_MPC862 1
42 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
43 #undef CONFIG_8xx_CONS_SMC2
44 #undef CONFIG_8xx_CONS_NONE
45 #define CONFIG_BAUDRATE 9600
46 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
49 #define MPC8XX_FACT 24 /* Multiply by 24 */
50 #define MPC8XX_XIN 4165000 /* 4.165 MHz in */
51 #define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN)
52 /* define if cant' use get_gclk_freq */
54 #if 1 /* for 50MHz version of processor */
55 #define MPC8XX_FACT 12 /* Multiply by 12 */
56 #define MPC8XX_XIN 4000000 /* 4 MHz in */
57 #define CONFIG_8xx_GCLK_FREQ 48000000 /* define if cant use get_gclk_freq */
58 #else /* for 80MHz version of processor */
59 #define MPC8XX_FACT 20 /* Multiply by 20 */
60 #define MPC8XX_XIN 4000000 /* 4 MHz in */
61 #define CONFIG_8xx_GCLK_FREQ 80000000 /* define if cant use get_gclk_freq */
66 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
68 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
71 #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
73 #undef CONFIG_BOOTARGS
74 #define CONFIG_BOOTCOMMAND \
76 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
77 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
80 #undef CONFIG_WATCHDOG /* watchdog disabled */
82 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
84 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
86 #undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
87 #define CONFIG_FEC_ENET 1 /* use FEC ethernet */
90 #define CFG_DISCOVER_PHY 1
92 #undef CFG_DISCOVER_PHY
95 #define CONFIG_MAC_PARTITION
96 #define CONFIG_DOS_PARTITION
98 /* enable I2C and select the hardware/software driver */
99 #undef CONFIG_HARD_I2C /* I2C with hardware support */
100 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
101 # define CFG_I2C_SPEED 50000
102 # define CFG_I2C_SLAVE 0xFE
103 # define CFG_I2C_EEPROM_ADDR 0x50
104 # define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
106 * Software (bit-bang) I2C driver configuration
108 #define PB_SCL 0x00000020 /* PB 26 */
109 #define PB_SDA 0x00000010 /* PB 27 */
111 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
112 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
113 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
114 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
115 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
116 else immr->im_cpm.cp_pbdat &= ~PB_SDA
117 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
118 else immr->im_cpm.cp_pbdat &= ~PB_SCL
119 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
121 #define CFG_EEPROM_X40430 /* Use a Xicor X40430 EEPROM */
122 #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16 bytes page write mode */
124 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
128 * Command line configuration.
130 #include <config_cmd_default.h>
132 #define CONFIG_CMD_ASKENV
133 #define CONFIG_CMD_DATE
134 #define CONFIG_CMD_DHCP
135 #define CONFIG_CMD_EEPROM
136 #define CONFIG_CMD_I2C
137 #define CONFIG_CMD_IDE
138 #define CONFIG_CMD_NFS
139 #define CONFIG_CMD_SNTP
143 * Miscellaneous configurable options
145 #define CFG_LONGHELP /* undef to save memory */
146 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
147 #if defined(CONFIG_CMD_KGDB)
148 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
150 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
152 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
153 #define CFG_MAXARGS 16 /* max number of command args */
154 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
156 #define CFG_MEMTEST_START 0x0100000 /* memtest works on */
157 #define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
159 #define CFG_LOAD_ADDR 0x00100000
161 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
163 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
166 * Low Level Configuration Settings
167 * (address mappings, register initial values, etc.)
168 * You should know what you are doing if you make changes here.
170 /*-----------------------------------------------------------------------
171 * Internal Memory Mapped Register
173 #define CFG_IMMR 0xF0000000
174 #define CFG_IMMR_SIZE ((uint)(64 * 1024))
176 /*-----------------------------------------------------------------------
177 * Definitions for initial stack pointer and data area (in DPRAM)
179 #define CFG_INIT_RAM_ADDR CFG_IMMR
180 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
181 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
182 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
183 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
185 /*-----------------------------------------------------------------------
186 * Start addresses for the final memory configuration
187 * (Set up by the startup code)
188 * Please note that CFG_SDRAM_BASE _must_ start at 0
190 #define CFG_SDRAM_BASE 0x00000000
191 #define CFG_FLASH_BASE 0x40000000
192 #define CFG_FLASH_SIZE ((uint)(16 * 1024 * 1024)) /* max 16Mbyte */
194 #define CFG_RESET_ADDRESS 0xFFF00100
198 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
200 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
203 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
205 #define CFG_MONITOR_BASE TEXT_BASE
206 #define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
209 * For booting Linux, the board info and command line data
210 * have to be in the first 8 MB of memory, since this is
211 * the maximum mapped by the Linux kernel during initialization.
213 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
214 /*-----------------------------------------------------------------------
217 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
218 #define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
220 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
221 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
224 #define CFG_ENV_IS_IN_FLASH 1
225 #define CFG_ENV_OFFSET 0x00F40000
227 #define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment sector */
228 #define CFG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */
230 /*-----------------------------------------------------------------------
231 * Cache Configuration
233 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
234 #if defined(CONFIG_CMD_KGDB)
235 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
238 /*-----------------------------------------------------------------------
239 * SYPCR - System Protection Control 11-9
240 * SYPCR can only be written once after reset!
241 *-----------------------------------------------------------------------
242 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
244 #if defined(CONFIG_WATCHDOG)
245 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
246 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
248 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
251 /*-----------------------------------------------------------------------
252 * SIUMCR - SIU Module Configuration 11-6
253 *-----------------------------------------------------------------------
254 * PCMCIA config., multi-function pin tri-state
256 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
258 /*-----------------------------------------------------------------------
259 * TBSCR - Time Base Status and Control 11-26
260 *-----------------------------------------------------------------------
261 * Clear Reference Interrupt Status, Timebase freezing enabled
263 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
265 /*-----------------------------------------------------------------------
266 * PISCR - Periodic Interrupt Status and Control 11-31
267 *-----------------------------------------------------------------------
268 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
270 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
272 /*-----------------------------------------------------------------------
273 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
274 *-----------------------------------------------------------------------
275 * set the PLL, the low-power modes and the reset control (15-29)
277 #define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
278 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
280 /*-----------------------------------------------------------------------
281 * SCCR - System Clock and reset Control Register 15-27
282 *-----------------------------------------------------------------------
283 * Set clock output, timebase and RTC source and divider,
284 * power management and some other internal clocks
286 #ifdef CONFIG_100MHz /* for 100 MHz, external bus is half CPU clock */
288 #define CFG_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \
289 SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
290 SCCR_DFLCD000 |SCCR_DFALCD00 | SCCR_EBDF01)
291 #else /* up to 50 MHz we use a 1:1 clock */
292 #define SCCR_MASK SCCR_EBDF11
293 #define CFG_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \
294 SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
295 SCCR_DFLCD000 |SCCR_DFALCD00 )
296 #endif /* CONFIG_100MHz */
298 /*-----------------------------------------------------------------------
299 * RCCR - RISC Controller Configuration Register 19-4
300 *-----------------------------------------------------------------------
302 /* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */
303 #define CFG_RCCR 0x0020
305 /*-----------------------------------------------------------------------
307 *-----------------------------------------------------------------------
309 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
310 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
311 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
312 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
313 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
314 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
315 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
316 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
318 /*-----------------------------------------------------------------------
319 * PCMCIA Power Switch
321 * The ICU862 uses a TPS2205 PC-Card Power-Interface Switch to
322 * control the voltages on the PCMCIA slot which is connected to Port B
323 *-----------------------------------------------------------------------
326 #define TPS2205_VCC5 0x00008000 /* PB.16: 5V Voltage Control */
327 #define TPS2205_VCC3 0x00004000 /* PB.17: 3V Voltage Control */
328 #define TPS2205_VPP_PGM 0x00002000 /* PB.18: PGM Voltage Control */
329 #define TPS2205_VPP_VCC 0x00001000 /* PB.19: VPP Voltage Control */
330 #define TPS2205_SHDN 0x00000200 /* PB.22: Shutdown */
331 #define TPS2205_OUTPUTS ( TPS2205_VCC5 | TPS2205_VCC3 | \
332 TPS2205_VPP_PGM | TPS2205_VPP_VCC | \
336 #define TPS2205_OC 0x00000100 /* PB.23: Over-Current */
337 #define TPS2205_INPUTS ( TPS2205_OC )
339 /*-----------------------------------------------------------------------
340 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
341 *-----------------------------------------------------------------------
344 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
346 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
347 #undef CONFIG_IDE_LED /* LED for ide not supported */
348 #undef CONFIG_IDE_RESET /* reset for ide not supported */
350 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
351 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
353 #define CFG_ATA_IDE0_OFFSET 0x0000
355 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
357 /* Offset for data I/O */
358 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
360 /* Offset for normal register accesses */
361 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
363 /* Offset for alternate registers */
364 #define CFG_ATA_ALT_OFFSET 0x0100
367 /*-----------------------------------------------------------------------
369 *-----------------------------------------------------------------------
374 /* Because of the way the 860 starts up and assigns CS0 the
375 * entire address space, we have to set the memory controller
376 * differently. Normally, you write the option register
377 * first, and then enable the chip select by writing the
378 * base register. For CS0, you must write the base register
379 * first, followed by the option register.
383 * Init Memory Controller:
385 * BR0 and OR0 (FLASH)
388 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
389 #define FLASH_BASE1_PRELIM 0x0 /* FLASH bank #1 */
391 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
392 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
394 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
395 #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
397 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
399 #define CFG_OR0_PRELIM 0xFF000954 /* Real values for the board */
400 #define CFG_BR0_PRELIM 0x40000001 /* Real values for the board */
403 * BR1 and OR1 (SDRAM)
405 #define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank */
406 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
408 #define CFG_OR_TIMING_SDRAM 0x00000800 /* BIH is not set */
410 #define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM)
411 #define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
414 * Memory Periodic Timer Prescaler
417 /* periodic timer for refresh */
418 #define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
420 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
421 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
422 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
424 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
425 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
426 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
429 * MAMR settings for SDRAM
433 #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
434 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
435 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
437 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
438 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
439 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
441 #define CFG_MAMR 0x13a01114
443 * Internal Definitions
447 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
448 #define BOOTFLAG_WARM 0x02 /* Software reboot */
450 #ifdef CONFIG_MPC860T
452 /* Interrupt level assignments.
454 #define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
456 #endif /* CONFIG_MPC860T */
459 #endif /* __CONFIG_H */