2 * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
4 * This file is based on similar values for other boards found in
5 * other U-Boot config files, mainly tqm8260.h and mpc8260ads.h.
7 * SPDX-License-Identifier: GPL-2.0+
11 * Config header file for a Interphase 4539 PMC, 64 MB SDRAM, 4MB Flash.
17 /*-----------------------------------------------------------------------
18 * High Level Configuration Options
22 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
23 #define CONFIG_IPHASE4539 1 /* ...on a Interphase 4539 PMC */
25 #define CONFIG_SYS_TEXT_BASE 0xffb00000
27 #define CONFIG_CPM2 1 /* Has a CPM2 */
29 /*-----------------------------------------------------------------------
30 * select serial console configuration
32 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
33 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
36 * if CONFIG_CONS_NONE is defined, then the serial console routines must
37 * defined elsewhere (for example, on the cogent platform, there are serial
38 * ports on the motherboard which are used for the serial console - see
39 * cogent/cma101/serial.[ch]).
41 #define CONFIG_CONS_ON_SMC /* define if console on SMC */
42 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
43 #undef CONFIG_CONS_NONE /* define if console on something else */
44 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
46 /*-----------------------------------------------------------------------
47 * select ethernet configuration
49 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
50 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
53 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
54 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
56 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
57 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
58 #undef CONFIG_ETHER_NONE /* define if ether on something else */
59 #define CONFIG_ETHER_INDEX 3 /* which channel for ether */
61 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
63 /*-----------------------------------------------------------------------
66 * - Select bus for bd/buffers (see 28-13)
69 # define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
70 # define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
71 # define CONFIG_SYS_CPMFCR_RAMTYPE 0
72 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
74 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
78 #define CONFIG_8260_CLKIN 66666666 /* in Hz */
79 #define CONFIG_BAUDRATE 19200
84 #define CONFIG_BOOTP_SUBNETMASK
85 #define CONFIG_BOOTP_GATEWAY
86 #define CONFIG_BOOTP_HOSTNAME
87 #define CONFIG_BOOTP_BOOTPATH
88 #define CONFIG_BOOTP_BOOTFILESIZE
91 * select i2c support configuration
93 * Supported configurations are {none, software, hardware} drivers.
94 * If the software driver is chosen, there are some additional
95 * configuration items that the driver uses to drive the port pins.
97 #undef CONFIG_HARD_I2C /* I2C with hardware support */
98 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
99 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
100 #define CONFIG_SYS_I2C_SLAVE 0x7F
103 * Software (bit-bang) I2C driver configuration
105 #ifdef CONFIG_SOFT_I2C
106 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
107 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
108 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
109 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
110 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
111 else iop->pdat &= ~0x00010000
112 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
113 else iop->pdat &= ~0x00020000
114 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
115 #endif /* CONFIG_SOFT_I2C */
119 * Command line configuration.
121 #include <config_cmd_default.h>
124 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
125 #define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */
126 #define CONFIG_BOOTARGS "root=/dev/ram rw"
128 #if defined(CONFIG_CMD_KGDB)
129 #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
130 #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
131 #undef CONFIG_KGDB_NONE /* define if kgdb on something else */
132 #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
133 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
136 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
138 /*-----------------------------------------------------------------------
139 * Miscellaneous configurable options
141 #define CONFIG_SYS_LONGHELP /* undef to save memory */
142 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
143 #if defined(CONFIG_CMD_KGDB)
144 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
146 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
148 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
149 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
150 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
152 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
153 #define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15 MB in DRAM */
155 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passed to Linux in MHz */
156 /* for versions < 2.4.5-pre5 */
158 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
160 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
162 #define CONFIG_SYS_RESET_ADDRESS 0x04400000
164 #define CONFIG_MISC_INIT_R 1 /* We need misc_init_r() */
166 /*-----------------------------------------------------------------------
167 * For booting Linux, the board info and command line data
168 * have to be in the first 8 MB of memory, since this is
169 * the maximum mapped by the Linux kernel during initialization.
171 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
173 /*-----------------------------------------------------------------------
174 * Start addresses for the final memory configuration (Setup by the
175 * startup code). Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0.
177 #define CONFIG_SYS_SDRAM_BASE 0x00000000
178 #define CONFIG_SYS_FLASH_BASE 0xFF800000
180 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
181 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
182 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
184 /*-----------------------------------------------------------------------
187 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
188 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* max num of sects on one chip */
189 #define CONFIG_SYS_MAX_FLASH_SIZE (CONFIG_SYS_MAX_FLASH_SECT * 0x10000) /* 4 MB */
191 #define CONFIG_SYS_FLASH_ERASE_TOUT 2400000 /* Flash Erase Timeout (in ms) */
192 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
194 /* Environment in FLASH, there is little space left in Serial EEPROM */
195 #define CONFIG_ENV_IS_IN_FLASH 1
196 #define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
197 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x10000) /* 2. sector */
200 /*-----------------------------------------------------------------------
201 * Hard Reset Configuration Words
203 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
204 * defines for the various registers affected by the HRCW e.g. changing
205 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
207 #define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS01 | HRCW_EBM ) |\
208 ( HRCW_L2CPC10 | HRCW_ISB110 ) |\
209 ( HRCW_MMR11 | HRCW_APPC10 ) |\
210 ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
214 #define CONFIG_SYS_HRCW_SLAVE1 0
215 #define CONFIG_SYS_HRCW_SLAVE2 0
216 #define CONFIG_SYS_HRCW_SLAVE3 0
217 #define CONFIG_SYS_HRCW_SLAVE4 0
218 #define CONFIG_SYS_HRCW_SLAVE5 0
219 #define CONFIG_SYS_HRCW_SLAVE6 0
220 #define CONFIG_SYS_HRCW_SLAVE7 0
222 /*-----------------------------------------------------------------------
223 * Internal Memory Mapped Register
225 #define CONFIG_SYS_IMMR 0xFF000000 /* We keep original value */
227 /*-----------------------------------------------------------------------
228 * Definitions for initial stack pointer and data area (in DPRAM)
230 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
231 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
232 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
233 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
235 /*-----------------------------------------------------------------------
236 * Cache Configuration
238 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
239 #if defined(CONFIG_CMD_KGDB)
240 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
243 /*-----------------------------------------------------------------------
244 * HIDx - Hardware Implementation-dependent Registers 2-11
245 *-----------------------------------------------------------------------
246 * HID0 also contains cache control.
248 * HID1 has only read-only information - nothing to set.
250 #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
252 #define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
253 #define CONFIG_SYS_HID2 0
255 /*-----------------------------------------------------------------------
256 * RMR - Reset Mode Register 5-5
257 *-----------------------------------------------------------------------
258 * turn on Checkstop Reset Enable
260 #define CONFIG_SYS_RMR RMR_CSRE
262 /*-----------------------------------------------------------------------
263 * BCR - Bus Configuration 4-25
264 *-----------------------------------------------------------------------
266 #define CONFIG_SYS_BCR 0xA01C0000
268 /*-----------------------------------------------------------------------
269 * SIUMCR - SIU Module Configuration 4-31
270 *-----------------------------------------------------------------------
272 #define CONFIG_SYS_SIUMCR 0X4205C000
274 /*-----------------------------------------------------------------------
275 * SYPCR - System Protection Control 4-35
276 * SYPCR can only be written once after reset!
277 *-----------------------------------------------------------------------
278 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
280 #if defined (CONFIG_WATCHDOG)
281 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
282 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
284 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
285 SYPCR_SWRI|SYPCR_SWP)
286 #endif /* CONFIG_WATCHDOG */
288 /*-----------------------------------------------------------------------
289 * TMCNTSC - Time Counter Status and Control 4-40
290 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
291 * and enable Time Counter
292 *-----------------------------------------------------------------------
294 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
296 /*-----------------------------------------------------------------------
297 * PISCR - Periodic Interrupt Status and Control 4-42
298 *-----------------------------------------------------------------------
299 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
302 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
304 /*-----------------------------------------------------------------------
305 * SCCR - System Clock Control 9-8
306 *-----------------------------------------------------------------------
307 * Ensure DFBRG is Divide by 16
309 #define CONFIG_SYS_SCCR 0
311 /*-----------------------------------------------------------------------
312 * RCCR - RISC Controller Configuration 13-7
313 *-----------------------------------------------------------------------
315 #define CONFIG_SYS_RCCR 0
317 /*-----------------------------------------------------------------------
318 * Init Memory Controller:
320 * Bank Bus Machine PortSz Device
321 * ---- --- ------- ------ ------
322 * 0 60x GPCM 64 bit FLASH
323 * 1 60x SDRAM 64 bit SDRAM
326 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) | 0x0801)
327 #define CONFIG_SYS_OR0_PRELIM 0xFF800882
328 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) | 0x0041)
329 #define CONFIG_SYS_OR1_PRELIM 0xF8002CD0
331 #define CONFIG_SYS_PSDMR 0x404A241A
332 #define CONFIG_SYS_MPTPR 0x00007400
333 #define CONFIG_SYS_PSRT 0x00000007
335 #endif /* __CONFIG_H */