2 * Copyright (C) 2004 Arabella Software Ltd.
3 * Yuli Barcohen <yuli@arabellasw.com>
5 * Support for Interphase iSPAN Communications Controllers
6 * (453x and others). Tested on 4532.
8 * Derived from iSPAN 4539 port (iphase4539) by
9 * Wolfgang Grandegger <wg@denx.de>
11 * SPDX-License-Identifier: GPL-2.0+
16 #define CONFIG_MPC8260 /* This is an MPC8260 CPU */
17 #define CONFIG_ISPAN /* ...on one of Interphase iSPAN boards */
18 #define CONFIG_CPM2 1 /* Has a CPM2 */
20 #define CONFIG_SYS_TEXT_BASE 0xFE7A0000
22 /*-----------------------------------------------------------------------
23 * Select serial console configuration
25 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
26 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
29 * If CONFIG_CONS_NONE is defined, then the serial console routines must be
30 * defined elsewhere (for example, on the cogent platform, there are serial
31 * ports on the motherboard which are used for the serial console - see
32 * cogent/cma101/serial.[ch]).
34 #define CONFIG_CONS_ON_SMC /* Define if console on SMC */
35 #undef CONFIG_CONS_ON_SCC /* Define if console on SCC */
36 #undef CONFIG_CONS_NONE /* Define if console on something else */
37 #define CONFIG_CONS_INDEX 1 /* Which serial channel for console */
39 /*-----------------------------------------------------------------------
40 * Select Ethernet configuration
42 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
43 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
46 * If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must
47 * be defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
49 #undef CONFIG_ETHER_ON_SCC /* Define if Ethernet on SCC */
50 #define CONFIG_ETHER_ON_FCC /* Define if Ethernet on FCC */
51 #undef CONFIG_ETHER_NONE /* Define if Ethernet on something else */
52 #define CONFIG_ETHER_INDEX 3 /* Which channel for Ethernrt */
54 #ifdef CONFIG_ETHER_ON_FCC
56 #if CONFIG_ETHER_INDEX == 3
58 #define CONFIG_SYS_PHY_ADDR 0
59 #define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
60 #define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
62 #endif /* CONFIG_ETHER_INDEX == 3 */
64 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
65 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
67 #define CONFIG_MII /* MII PHY management */
68 #define CONFIG_BITBANGMII /* Bit-bang MII PHY management */
70 * GPIO pins used for bit-banged MII communications
72 #define MDIO_PORT 3 /* Port D */
73 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
74 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
75 #define MDC_DECLARE MDIO_DECLARE
78 #define CONFIG_SYS_MDIO_PIN 0x00040000 /* PD13 */
79 #define CONFIG_SYS_MDC_PIN 0x00080000 /* PD12 */
81 #define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
82 #define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
83 #define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
85 #define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
86 else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
88 #define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
89 else iop->pdat &= ~CONFIG_SYS_MDC_PIN
91 #define MIIDELAY udelay(1)
93 #endif /* CONFIG_ETHER_ON_FCC */
95 #define CONFIG_8260_CLKIN 65536000 /* in Hz */
96 #define CONFIG_BAUDRATE 38400
102 #define CONFIG_BOOTP_BOOTFILESIZE
103 #define CONFIG_BOOTP_BOOTPATH
104 #define CONFIG_BOOTP_GATEWAY
105 #define CONFIG_BOOTP_HOSTNAME
109 * Command line configuration.
111 #include <config_cmd_default.h>
113 #define CONFIG_CMD_ASKENV
114 #define CONFIG_CMD_DHCP
115 #define CONFIG_CMD_IMMAP
116 #define CONFIG_CMD_MII
117 #define CONFIG_CMD_PING
118 #define CONFIG_CMD_REGINFO
121 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
122 #define CONFIG_BOOTCOMMAND "bootm fe010000" /* autoboot command */
123 #define CONFIG_BOOTARGS "root=/dev/ram rw"
125 #define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
126 #undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
128 /*-----------------------------------------------------------------------
129 * Miscellaneous configurable options
131 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
132 #define CONFIG_SYS_HUSH_PARSER
133 #define CONFIG_SYS_LONGHELP /* #undef to save memory */
134 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
135 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
136 #define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
137 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
139 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
140 #define CONFIG_SYS_MEMTEST_END 0x03B00000 /* 1 ... 59 MB in SDRAM */
142 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* Default load address */
144 #define CONFIG_SYS_HZ 1000 /* Decrementer freq: 1 ms ticks */
146 #define CONFIG_SYS_RESET_ADDRESS 0x09900000
148 #define CONFIG_MISC_INIT_R /* We need misc_init_r() */
150 /*-----------------------------------------------------------------------
151 * For booting Linux, the board info and command line data
152 * have to be in the first 8 MB of memory, since this is
153 * the maximum mapped by the Linux kernel during initialization.
155 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
157 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
158 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
160 #define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
162 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
163 #endif /* CONFIG_BZIP2 */
165 /*-----------------------------------------------------------------------
168 #define CONFIG_SYS_FLASH_BASE 0xFE000000
169 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
170 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
171 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max num of memory banks */
172 #define CONFIG_SYS_MAX_FLASH_SECT 142 /* Max num of sects on one chip */
174 /* Environment is in flash, there is little space left in Serial EEPROM */
175 #define CONFIG_ENV_IS_IN_FLASH
176 #define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
177 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
178 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
179 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
180 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
182 /*-----------------------------------------------------------------------
183 * Hard Reset Configuration Words
185 * If you change bits in the HRCW, you must also change the CONFIG_SYS_*
186 * defines for the various registers affected by the HRCW e.g. changing
187 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
190 #define CONFIG_SYS_HRCW_MASTER (HRCW_EBM | HRCW_BPS01 | HRCW_CIP |\
191 HRCW_L2CPC10 | HRCW_ISB110 |\
192 HRCW_BMS | HRCW_MMR11 | HRCW_APPC10 |\
193 HRCW_CS10PC01 | HRCW_MODCK_H0101 \
196 #define CONFIG_SYS_HRCW_SLAVE1 0
197 #define CONFIG_SYS_HRCW_SLAVE2 0
198 #define CONFIG_SYS_HRCW_SLAVE3 0
199 #define CONFIG_SYS_HRCW_SLAVE4 0
200 #define CONFIG_SYS_HRCW_SLAVE5 0
201 #define CONFIG_SYS_HRCW_SLAVE6 0
202 #define CONFIG_SYS_HRCW_SLAVE7 0
204 /*-----------------------------------------------------------------------
205 * Internal Memory Mapped Register
207 #define CONFIG_SYS_IMMR 0xF0F00000
208 #ifdef CONFIG_SYS_REV_B
209 #define CONFIG_SYS_DEFAULT_IMMR 0xFF000000
210 #endif /* CONFIG_SYS_REV_B */
211 /*-----------------------------------------------------------------------
212 * Definitions for initial stack pointer and data area (in DPRAM)
214 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
215 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
216 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
217 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
219 /*-----------------------------------------------------------------------
220 * Cache Configuration
222 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
224 /*-----------------------------------------------------------------------
225 * HIDx - Hardware Implementation-dependent Registers 2-11
226 *-----------------------------------------------------------------------
227 * HID0 also contains cache control.
229 * HID1 has only read-only information - nothing to set.
231 #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
233 #define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
234 #define CONFIG_SYS_HID2 0
236 /*-----------------------------------------------------------------------
237 * RMR - Reset Mode Register 5-5
238 *-----------------------------------------------------------------------
239 * turn on Checkstop Reset Enable
241 #define CONFIG_SYS_RMR RMR_CSRE
243 /*-----------------------------------------------------------------------
244 * BCR - Bus Configuration 4-25
245 *-----------------------------------------------------------------------
247 #define CONFIG_SYS_BCR 0xA01C0000
249 /*-----------------------------------------------------------------------
250 * SIUMCR - SIU Module Configuration 4-31
251 *-----------------------------------------------------------------------
253 #define CONFIG_SYS_SIUMCR 0x42250000/* 0x4205C000 */
255 /*-----------------------------------------------------------------------
256 * SYPCR - System Protection Control 4-35
257 * SYPCR can only be written once after reset!
258 *-----------------------------------------------------------------------
259 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
261 #if defined (CONFIG_WATCHDOG)
262 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
263 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
265 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
266 SYPCR_SWRI|SYPCR_SWP)
267 #endif /* CONFIG_WATCHDOG */
269 /*-----------------------------------------------------------------------
270 * TMCNTSC - Time Counter Status and Control 4-40
271 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
272 * and enable Time Counter
273 *-----------------------------------------------------------------------
275 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
277 /*-----------------------------------------------------------------------
278 * PISCR - Periodic Interrupt Status and Control 4-42
279 *-----------------------------------------------------------------------
280 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
283 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
285 /*-----------------------------------------------------------------------
286 * SCCR - System Clock Control 9-8
287 *-----------------------------------------------------------------------
288 * Ensure DFBRG is Divide by 16
290 #define CONFIG_SYS_SCCR SCCR_DFBRG01
292 /*-----------------------------------------------------------------------
293 * RCCR - RISC Controller Configuration 13-7
294 *-----------------------------------------------------------------------
296 #define CONFIG_SYS_RCCR 0
298 /*-----------------------------------------------------------------------
299 * Init Memory Controller:
301 * Bank Bus Machine PortSize Device
302 * ---- --- ------- ----------------------------- ------
303 * 0 60x GPCM 8 bit (Rev.B)/16 bit (Rev.D) Flash
304 * 1 60x SDRAM 64 bit SDRAM
305 * 2 Local SDRAM 32 bit SDRAM
307 #define CONFIG_SYS_USE_FIRMWARE /* If defined - do not initialise memory
308 controller, rely on initialisation
309 performed by the Interphase boot firmware.
312 #define CONFIG_SYS_OR0_PRELIM 0xFE000882
313 #ifdef CONFIG_SYS_REV_B
314 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BRx_PS_8 | BRx_V)
316 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BRx_PS_16 | BRx_V)
317 #endif /* CONFIG_SYS_REV_B */
319 #define CONFIG_SYS_MPTPR 0x7F00
321 /* Please note that 60x SDRAM MUST start at 0 */
322 #define CONFIG_SYS_SDRAM_BASE 0x00000000
323 #define CONFIG_SYS_60x_BR 0x00000041
324 #define CONFIG_SYS_60x_OR 0xF0002CD0
325 #define CONFIG_SYS_PSDMR 0x0049929A
326 #define CONFIG_SYS_PSRT 0x07
328 #define CONFIG_SYS_LSDRAM_BASE 0xF7000000
329 #define CONFIG_SYS_LOC_BR 0x00001861
330 #define CONFIG_SYS_LOC_OR 0xFF803280
331 #define CONFIG_SYS_LSDMR 0x8285A552
332 #define CONFIG_SYS_LSRT 0x07
334 #endif /* __CONFIG_H */