2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
32 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
33 #define CONFIG_ICECUBE 1 /* ... on IceCube board */
35 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
37 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
38 #define BOOTFLAG_WARM 0x02 /* Software reboot */
41 * Serial console configuration
43 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
44 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
45 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
48 #ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
51 * 0x40000000 - 0x4fffffff - PCI Memory
52 * 0x50000000 - 0x50ffffff - PCI IO Space
56 #if defined(CONFIG_PCI)
57 #define CONFIG_PCI_PNP 1
58 #define CONFIG_PCI_SCAN_SHOW 1
60 #define CONFIG_PCI_MEM_BUS 0x40000000
61 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
62 #define CONFIG_PCI_MEM_SIZE 0x10000000
64 #define CONFIG_PCI_IO_BUS 0x50000000
65 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
66 #define CONFIG_PCI_IO_SIZE 0x01000000
67 #define ADD_PCI_CMD CFG_CMD_PCI
70 #define CFG_XLB_PIPELINING 1
72 #define CONFIG_NET_MULTI 1
74 #define CONFIG_EEPRO100 1
75 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
76 #define CONFIG_NS8382X 1
81 #define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
86 #define CONFIG_MAC_PARTITION
87 #define CONFIG_DOS_PARTITION
88 #define CONFIG_ISO_PARTITION
92 #define CONFIG_USB_OHCI
93 #define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
94 #define CONFIG_USB_STORAGE
99 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
103 * Command line configuration.
105 #include <config_cmd_default.h>
107 #define CONFIG_CMD_EEPROM
108 #define CONFIG_CMD_FAT
109 #define CONFIG_CMD_I2C
110 #define CONFIG_CMD_IDE
111 #define CONFIG_CMD_NFS
112 #define CONFIG_CMD_SNTP
113 #define CONFIG_PCI_CMD
114 #define CONFIG_USB_CMD
117 #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
118 # define CFG_LOWBOOT 1
119 # define CFG_LOWBOOT16 1
121 #if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
122 #if defined(CONFIG_LITE5200B)
123 # error CFG_LOWBOOT08 is incompatible with the Lite5200B
125 # define CFG_LOWBOOT 1
126 # define CFG_LOWBOOT08 1
133 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
135 #define CONFIG_PREBOOT "echo;" \
136 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
139 #undef CONFIG_BOOTARGS
141 #define CONFIG_EXTRA_ENV_SETTINGS \
143 "nfsargs=setenv bootargs root=/dev/nfs rw " \
144 "nfsroot=${serverip}:${rootpath}\0" \
145 "ramargs=setenv bootargs root=/dev/ram rw\0" \
146 "addip=setenv bootargs ${bootargs} " \
147 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
148 ":${hostname}:${netdev}:off panic=1\0" \
149 "flash_nfs=run nfsargs addip;" \
150 "bootm ${kernel_addr}\0" \
151 "flash_self=run ramargs addip;" \
152 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
153 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
154 "rootpath=/opt/eldk/ppc_82xx\0" \
155 "bootfile=/tftpboot/MPC5200/uImage\0" \
158 #define CONFIG_BOOTCOMMAND "run flash_self"
160 #if defined(CONFIG_MPC5200)
162 * IPB Bus clocking configuration.
164 #if defined(CONFIG_LITE5200B)
165 #define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
167 #undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
169 #endif /* CONFIG_MPC5200 */
171 /* pass open firmware flat tree */
172 #define CONFIG_OF_FLAT_TREE 1
173 #define CONFIG_OF_BOARD_SETUP 1
175 /* maximum size of the flat tree (8K) */
176 #define OF_FLAT_TREE_MAX_SIZE 8192
178 #define OF_CPU "PowerPC,5200@0"
179 #define OF_SOC "soc5200@f0000000"
180 #define OF_TBCLK (bd->bi_busfreq / 4)
181 #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
186 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
187 #define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
189 #define CFG_I2C_SPEED 100000 /* 100 kHz */
190 #define CFG_I2C_SLAVE 0x7F
193 * EEPROM configuration
195 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
196 #define CFG_I2C_EEPROM_ADDR_LEN 1
197 #define CFG_EEPROM_PAGE_WRITE_BITS 3
198 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
201 * Flash configuration
203 #if defined(CONFIG_LITE5200B)
204 #define CFG_FLASH_BASE 0xFE000000
205 #define CFG_FLASH_SIZE 0x01000000
206 #if !defined(CFG_LOWBOOT)
207 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x01760000 + 0x00800000)
208 #else /* CFG_LOWBOOT */
209 #if defined(CFG_LOWBOOT08)
210 # error CFG_LOWBOOT08 is incompatible with the Lite5200B
212 #if defined(CFG_LOWBOOT16)
213 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x01060000)
215 #endif /* CFG_LOWBOOT */
216 #else /* !CONFIG_LITE5200B (IceCube)*/
217 #define CFG_FLASH_BASE 0xFF000000
218 #define CFG_FLASH_SIZE 0x01000000
219 #if !defined(CFG_LOWBOOT)
220 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00740000 + 0x00800000)
221 #else /* CFG_LOWBOOT */
222 #if defined(CFG_LOWBOOT08)
223 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000 + 0x00800000)
225 #if defined(CFG_LOWBOOT16)
226 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
228 #endif /* CFG_LOWBOOT */
229 #endif /* CONFIG_LITE5200B */
230 #define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
232 #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
234 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
235 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
237 #undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
239 #if defined(CONFIG_LITE5200B)
240 #define CFG_FLASH_CFI_DRIVER
241 #define CFG_FLASH_CFI
242 #define CFG_FLASH_BANKS_LIST {CFG_CS1_START,CFG_CS0_START}
247 * Environment settings
249 #define CFG_ENV_IS_IN_FLASH 1
250 #define CFG_ENV_SIZE 0x10000
251 #if defined(CONFIG_LITE5200B)
252 #define CFG_ENV_SECT_SIZE 0x20000
254 #define CFG_ENV_SECT_SIZE 0x10000
256 #define CONFIG_ENV_OVERWRITE 1
261 #define CFG_MBAR 0xF0000000
262 #define CFG_SDRAM_BASE 0x00000000
263 #define CFG_DEFAULT_MBAR 0x80000000
265 /* Use SRAM until RAM will be available */
266 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
267 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
270 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
271 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
272 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
274 #define CFG_MONITOR_BASE TEXT_BASE
275 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
276 # define CFG_RAMBOOT 1
279 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
280 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
281 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
284 * Ethernet configuration
286 #define CONFIG_MPC5xxx_FEC 1
288 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
290 /* #define CONFIG_FEC_10MBIT 1 */
291 #define CONFIG_PHY_ADDR 0x00
292 #if defined(CONFIG_LITE5200B)
293 #define CONFIG_FEC_MII100 1
299 #ifdef CONFIG_MPC5200_DDR
300 #define CFG_GPS_PORT_CONFIG 0x90000004
302 #define CFG_GPS_PORT_CONFIG 0x10000004
306 * Miscellaneous configurable options
308 #define CFG_LONGHELP /* undef to save memory */
309 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
310 #if defined(CONFIG_CMD_KGDB)
311 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
313 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
315 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
316 #define CFG_MAXARGS 16 /* max number of command args */
317 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
319 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
320 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
322 #define CFG_LOAD_ADDR 0x100000 /* default load address */
324 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
326 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
327 #if defined(CONFIG_CMD_KGDB)
328 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
332 * Various low-level settings
334 #if defined(CONFIG_MPC5200)
335 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
336 #define CFG_HID0_FINAL HID0_ICE
338 #define CFG_HID0_INIT 0
339 #define CFG_HID0_FINAL 0
342 #if defined(CONFIG_LITE5200B)
343 #define CFG_CS1_START CFG_FLASH_BASE
344 #define CFG_CS1_SIZE CFG_FLASH_SIZE
345 #define CFG_CS1_CFG 0x00047800
346 #define CFG_CS0_START (CFG_FLASH_BASE + CFG_FLASH_SIZE)
347 #define CFG_CS0_SIZE CFG_FLASH_SIZE
348 #define CFG_BOOTCS_START CFG_CS0_START
349 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
350 #define CFG_BOOTCS_CFG 0x00047800
351 #else /* IceCube aka Lite5200 */
352 #ifdef CONFIG_MPC5200_DDR
354 #define CFG_BOOTCS_START (CFG_CS1_START + CFG_CS1_SIZE)
355 #define CFG_BOOTCS_SIZE 0x00800000
356 #define CFG_BOOTCS_CFG 0x00047801
357 #define CFG_CS1_START CFG_FLASH_BASE
358 #define CFG_CS1_SIZE 0x00800000
359 #define CFG_CS1_CFG 0x00047800
361 #else /* !CONFIG_MPC5200_DDR */
363 #define CFG_BOOTCS_START CFG_FLASH_BASE
364 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
365 #define CFG_BOOTCS_CFG 0x00047801
366 #define CFG_CS0_START CFG_FLASH_BASE
367 #define CFG_CS0_SIZE CFG_FLASH_SIZE
369 #endif /* CONFIG_MPC5200_DDR */
370 #endif /*CONFIG_LITE5200B */
372 #define CFG_CS_BURST 0x00000000
373 #define CFG_CS_DEADCYCLE 0x33333333
375 #define CFG_RESET_ADDRESS 0xff000000
377 /*-----------------------------------------------------------------------
379 *-----------------------------------------------------------------------
381 #define CONFIG_USB_CLOCK 0x0001BBBB
382 #define CONFIG_USB_CONFIG 0x00001000
384 /*-----------------------------------------------------------------------
385 * IDE/ATA stuff Supports IDE harddisk
386 *-----------------------------------------------------------------------
389 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
391 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
392 #undef CONFIG_IDE_LED /* LED for ide not supported */
394 #define CONFIG_IDE_RESET /* reset for ide supported */
395 #define CONFIG_IDE_PREINIT
397 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
398 #define CFG_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
400 #define CFG_ATA_IDE0_OFFSET 0x0000
402 #define CFG_ATA_BASE_ADDR MPC5XXX_ATA
404 /* Offset for data I/O */
405 #define CFG_ATA_DATA_OFFSET (0x0060)
407 /* Offset for normal register accesses */
408 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
410 /* Offset for alternate registers */
411 #define CFG_ATA_ALT_OFFSET (0x005C)
413 /* Interval between registers */
414 #define CFG_ATA_STRIDE 4
416 #define CONFIG_ATAPI 1
418 #endif /* __CONFIG_H */