2 * (C) Copyright 2000-2010
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
6 * SPDX-License-Identifier: GPL-2.0+
10 * board/config.h - configuration options, board specific
11 * Derived from ../tqm8xx/tqm8xx.c
18 * High Level Configuration Options
22 #define CONFIG_MPC855 1 /* This is a MPC855 CPU */
23 #define CONFIG_KUP4K 1 /* ...on a KUP4K module */
25 #define CONFIG_SYS_TEXT_BASE 0x40000000
27 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
28 #undef CONFIG_8xx_CONS_SMC2
29 #undef CONFIG_8xx_CONS_NONE
30 #define CONFIG_BAUDRATE 115200 /* console baudrate */
31 #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
33 #define CONFIG_BOARD_TYPES 1 /* support board types */
35 #undef CONFIG_BOOTARGS
37 #define CONFIG_EXTRA_ENV_SETTINGS \
38 "slot_a_boot=setenv bootargs root=/dev/sda2 ip=off;" \
39 "run addhw; mw.b 400000 00 80; diskboot 400000 0:1; bootm 400000\0" \
40 "slot_b_boot=setenv bootargs root=/dev/sda2 ip=off;" \
41 "run addhw; mw.b 400000 00 80; diskboot 400000 2:1; bootm 400000\0" \
42 "nfs_boot=mw.b 400000 00 80; dhcp; run nfsargs addip addhw; bootm 400000\0" \
43 "fat_boot=mw.b 400000 00 80; fatload ide 2:1 400000 st.bin; run addhw; \
45 "panic_boot=echo No Bootdevice !!! reset\0" \
46 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${rootpath}\0" \
47 "ramargs=setenv bootargs root=/dev/ram rw\0" \
48 "addip=setenv bootargs ${bootargs} ip=${ipaddr}::${gatewayip}" \
49 ":${netmask}:${hostname}:${netdev}:off\0" \
50 "addhw=setenv bootargs ${bootargs} ${mtdparts} console=${console} ${debug} \
51 hw=${hw} key1=${key1} panic=1 mem=${mem}\0" \
52 "console=ttyCPM0,115200\0" \
56 "mtdparts=" MTDPARTS_DEFAULT "\0" \
57 "load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0" \
58 "update=protect off 1:0-9;era 1:0-9;cp.b 100000 40000000 ${filesize};" \
59 "cp.b 200000 40050000 14000\0"
61 #define CONFIG_BOOTCOMMAND \
62 "run fat_boot;run slot_b_boot;run slot_a_boot;run nfs_boot;run panic_boot"
64 #define CONFIG_PREBOOT "setenv preboot; saveenv"
66 #define CONFIG_MISC_INIT_R 1
67 #define CONFIG_MISC_INIT_F 1
69 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
70 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
72 #define CONFIG_WATCHDOG 1 /* watchdog enabled */
74 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
76 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
81 #define CONFIG_BOOTP_SUBNETMASK
82 #define CONFIG_BOOTP_GATEWAY
83 #define CONFIG_BOOTP_HOSTNAME
84 #define CONFIG_BOOTP_BOOTPATH
85 #define CONFIG_BOOTP_BOOTFILESIZE
87 #define CONFIG_MAC_PARTITION
88 #define CONFIG_DOS_PARTITION
91 * enable I2C and select the hardware/software driver
93 #define CONFIG_SYS_I2C
94 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
95 #define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
96 #define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
99 * Software (bit-bang) I2C driver configuration
101 #define PB_SCL 0x00000020 /* PB 26 */
102 #define PB_SDA 0x00000010 /* PB 27 */
104 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
105 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
106 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
107 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
108 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
109 else immr->im_cpm.cp_pbdat &= ~PB_SDA
110 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
111 else immr->im_cpm.cp_pbdat &= ~PB_SCL
112 #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
114 /*-----------------------------------------------------------------------
118 #define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */
119 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
121 /* List of I2C addresses to be verified by POST */
123 #define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_PICIO_ADDR, \
124 CONFIG_SYS_I2C_RTC_ADDR, \
127 #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
129 #define CONFIG_SYS_DISCOVER_PHY
132 /* Define to allow the user to overwrite serial and ethaddr */
133 #define CONFIG_ENV_OVERWRITE
136 * Command line configuration.
138 #include <config_cmd_default.h>
140 #define CONFIG_CMD_DATE
141 #define CONFIG_CMD_DHCP
142 #define CONFIG_CMD_I2C
143 #define CONFIG_CMD_IDE
144 #define CONFIG_CMD_MII
145 #define CONFIG_CMD_NFS
146 #define CONFIG_CMD_FAT
147 #define CONFIG_CMD_SNTP
150 #define CONFIG_CMD_DIAG
154 * Miscellaneous configurable options
156 #define CONFIG_SYS_LONGHELP /* undef to save memory */
157 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
158 #if defined(CONFIG_CMD_KGDB)
159 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
161 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
163 /* Print Buffer Size */
164 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
165 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
166 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
168 #define CONFIG_SYS_MEMTEST_START 0x000400000 /* memtest works on */
169 #define CONFIG_SYS_MEMTEST_END 0x005C00000 /* 4 ... 92 MB in DRAM */
170 #define CONFIG_SYS_ALT_MEMTEST 1
171 #define CONFIG_SYS_MEMTEST_SCRATCH 0x90000200 /* using latch as scratch register */
173 #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
175 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
177 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 }
179 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1
182 * Low Level Configuration Settings
183 * (address mappings, register initial values, etc.)
184 * You should know what you are doing if you make changes here.
186 /*-----------------------------------------------------------------------
187 * Internal Memory Mapped Register
189 #define CONFIG_SYS_IMMR 0xFFF00000
191 /*-----------------------------------------------------------------------
192 * Definitions for initial stack pointer and data area (in DPRAM)
194 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
195 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
196 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
197 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
199 /*-----------------------------------------------------------------------
200 * Start addresses for the final memory configuration
201 * (Set up by the startup code)
202 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
204 #define CONFIG_SYS_SDRAM_BASE 0x00000000
205 #define CONFIG_SYS_FLASH_BASE 0x40000000
206 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
207 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
208 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
211 * For booting Linux, the board info and command line data
212 * have to be in the first 8 MB of memory, since this is
213 * the maximum mapped by the Linux kernel during initialization.
215 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
217 /*-----------------------------------------------------------------------
220 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
221 #define CONFIG_SYS_MAX_FLASH_SECT 19 /* max number of sectors on one chip */
223 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
224 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
226 #define CONFIG_ENV_IS_IN_FLASH 1
227 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
228 #define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
229 #define CONFIG_ENV_SECT_SIZE 0x10000
231 /*-----------------------------------------------------------------------
232 * Dynamic MTD partition support
234 #define MTDPARTS_DEFAULT "mtdparts=40000000.flash:256k(u-boot)," \
240 /*-----------------------------------------------------------------------
241 * Hardware Information Block
243 #define CONFIG_SYS_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */
244 #define CONFIG_SYS_HWINFO_SIZE 0x00000100 /* size of HW Info block */
245 #define CONFIG_SYS_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */
247 /*-----------------------------------------------------------------------
248 * Cache Configuration
250 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
251 #if defined(CONFIG_CMD_KGDB)
252 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
255 /*-----------------------------------------------------------------------
256 * SYPCR - System Protection Control 11-9
257 * SYPCR can only be written once after reset!
258 *-----------------------------------------------------------------------
259 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
261 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
263 /*-----------------------------------------------------------------------
264 * SIUMCR - SIU Module Configuration 11-6
265 *-----------------------------------------------------------------------
266 * PCMCIA config., multi-function pin tri-state
268 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
270 /*-----------------------------------------------------------------------
271 * TBSCR - Time Base Status and Control 11-26
272 *-----------------------------------------------------------------------
273 * Clear Reference Interrupt Status, Timebase freezing enabled
275 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
277 /*-----------------------------------------------------------------------
278 * RTCSC - Real-Time Clock Status and Control Register 11-27
279 *-----------------------------------------------------------------------
281 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
283 /*-----------------------------------------------------------------------
284 * PISCR - Periodic Interrupt Status and Control 11-31
285 *-----------------------------------------------------------------------
286 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
288 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
290 /*-----------------------------------------------------------------------
291 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
292 *-----------------------------------------------------------------------
293 * Reset PLL lock status sticky bit, timer expired status bit and timer
294 * interrupt status bit
296 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
298 #define CONFIG_SYS_PLPRCR ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
300 /*-----------------------------------------------------------------------
301 * SCCR - System Clock and reset Control Register 15-27
302 *-----------------------------------------------------------------------
303 * Set clock output, timebase and RTC source and divider,
304 * power management and some other internal clocks
306 #define SCCR_MASK SCCR_EBDF00
307 #define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF01 | \
308 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
309 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
312 /*-----------------------------------------------------------------------
314 *-----------------------------------------------------------------------
318 /* KUP4K use both slots, SLOT_A as "primary". */
319 #define CONFIG_PCMCIA_SLOT_A 1
321 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
322 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
323 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
324 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
325 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
326 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
327 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
328 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
330 #define PCMCIA_SOCKETS_NO 2
331 #define PCMCIA_MEM_WIN_NO 8
332 /*-----------------------------------------------------------------------
333 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
334 *-----------------------------------------------------------------------
337 #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
338 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
340 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
341 #define CONFIG_IDE_LED 1 /* LED for ide supported */
342 #undef CONFIG_IDE_RESET /* reset for ide not supported */
344 #define CONFIG_SYS_IDE_MAXBUS 2
345 #define CONFIG_SYS_IDE_MAXDEVICE 4
347 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
349 #define CONFIG_SYS_ATA_IDE1_OFFSET (4 * CONFIG_SYS_PCMCIA_MEM_SIZE)
351 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
353 /* Offset for data I/O */
354 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
356 /* Offset for normal register accesses */
357 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
359 /* Offset for alternate registers */
360 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
362 /*-----------------------------------------------------------------------
364 *-----------------------------------------------------------------------
367 #define CONFIG_SYS_DER 0
370 * Init Memory Controller:
372 * BR0/1 and OR0/1 (FLASH)
374 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
376 /* used to re-map FLASH both when starting from SRAM or FLASH:
377 * restrict access enough to keep SRAM working (if any)
378 * but not too much to meddle with FLASH accesses
380 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
381 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
386 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_CSNT_SAM | \
387 OR_SCY_5_CLK | OR_EHTR | OR_BI)
389 #define CONFIG_SYS_OR0_REMAP \
390 (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
391 #define CONFIG_SYS_OR0_PRELIM \
392 (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
393 #define CONFIG_SYS_BR0_PRELIM \
394 ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
397 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
398 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
401 * Memory Periodic Timer Prescaler
403 * The Divider for PTA (refresh timer) configuration is based on an
404 * example SDRAM configuration (64 MBit, one bank). The adjustment to
405 * the number of chip selects (NCS) and the actually needed refresh
406 * rate is done by setting MPTPR.
408 * PTA is calculated from
409 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
411 * gclk CPU clock (not bus clock!)
412 * Trefresh Refresh cycle * 4 (four word bursts used)
414 * 4096 Rows from SDRAM example configuration
415 * 1000 factor s -> ms
416 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
417 * 4 Number of refresh cycles per period
418 * 64 Refresh cycle in ms per number of rows
419 * --------------------------------------------
420 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
422 * 50 MHz => 50.000.000 / Divider = 98
423 * 66 Mhz => 66.000.000 / Divider = 129
424 * 80 Mhz => 80.000.000 / Divider = 156
426 #if defined(CONFIG_80MHz)
427 #define CONFIG_SYS_MAMR_PTA 156
428 #elif defined(CONFIG_66MHz)
429 #define CONFIG_SYS_MAMR_PTA 129
431 #define CONFIG_SYS_MAMR_PTA 98
432 #endif /*CONFIG_??MHz */
435 * For 16 MBit, refresh rates could be 31.3 us
436 * (= 64 ms / 2K = 125 / quad bursts).
437 * For a simpler initialization, 15.6 us is used instead.
439 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
440 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
442 #define CONFIG_SYS_MPTPR 0x400
445 * MAMR settings for SDRAM
449 #define CONFIG_SYS_MAMR_8COL 0x68802114
451 #define CONFIG_SYS_MAMR_9COL 0x68904114
456 #define CONFIG_SYS_OR0
457 #define CONFIG_SYS_BR0
459 #define CONFIG_SYS_OR1_8COL 0xFF000A00
460 #define CONFIG_SYS_BR1_8COL 0x00000081
461 #define CONFIG_SYS_OR2_8COL 0xFE000A00
462 #define CONFIG_SYS_BR2_8COL 0x01000081
463 #define CONFIG_SYS_OR3_8COL 0xFC000A00
464 #define CONFIG_SYS_BR3_8COL 0x02000081
466 #define CONFIG_SYS_OR1_9COL 0xFE000A00
467 #define CONFIG_SYS_BR1_9COL 0x00000081
468 #define CONFIG_SYS_OR2_9COL 0xFE000A00
469 #define CONFIG_SYS_BR2_9COL 0x02000081
470 #define CONFIG_SYS_OR3_9COL 0xFE000A00
471 #define CONFIG_SYS_BR3_9COL 0x04000081
473 #define CONFIG_SYS_OR4 0xFFFF8926
474 #define CONFIG_SYS_BR4 0x90000401
476 #define CONFIG_SYS_OR5 0xFFC007F0 /* EPSON: 4 MB 17 WS or externel TA */
477 #define CONFIG_SYS_BR5 0x80080801 /* Start at 0x80080000 */
479 #define LATCH_ADDR 0x90000200
481 #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
482 #define CONFIG_AUTOBOOT_STOP_STR "."
483 #define CONFIG_SILENT_CONSOLE 1
484 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* enble null device */
485 #define CONFIG_VERSION_VARIABLE 1
487 /* pass open firmware flat tree */
488 #define CONFIG_OF_LIBFDT 1
489 #define CONFIG_OF_BOARD_SETUP 1
491 #endif /* __CONFIG_H */