2 * Configuation settings for the Freescale MCF52277 EVB board.
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
11 * board/config.h - configuration options, board specific
18 * High Level Configuration Options
21 #define CONFIG_M52277EVB /* M52277EVB board */
23 #define CONFIG_MCFUART
24 #define CONFIG_SYS_UART_PORT (0)
26 #undef CONFIG_WATCHDOG
28 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
33 #define CONFIG_BOOTP_BOOTFILESIZE
34 #define CONFIG_BOOTP_BOOTPATH
35 #define CONFIG_BOOTP_GATEWAY
36 #define CONFIG_BOOTP_HOSTNAME
38 #define CONFIG_HOSTNAME M52277EVB
39 #define CONFIG_SYS_UBOOT_END 0x3FFFF
40 #define CONFIG_SYS_LOAD_ADDR2 0x40010007
41 #ifdef CONFIG_SYS_STMICRO_BOOT
42 /* ST Micro serial flash */
43 #define CONFIG_EXTRA_ENV_SETTINGS \
44 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
45 "loadaddr=0x40010000\0" \
46 "uboot=u-boot.bin\0" \
47 "load=loadb ${loadaddr} ${baudrate};" \
48 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
49 "upd=run load; run prog\0" \
50 "prog=sf probe 0:2 10000 1;" \
52 "sf write ${loadaddr} 0 30000;" \
56 #ifdef CONFIG_SYS_SPANSION_BOOT
57 #define CONFIG_EXTRA_ENV_SETTINGS \
58 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
59 "loadaddr=0x40010000\0" \
60 "uboot=u-boot.bin\0" \
61 "load=loadb ${loadaddr} ${baudrate}\0" \
62 "upd=run load; run prog\0" \
63 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
64 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \
65 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
66 __stringify(CONFIG_SYS_UBOOT_END) ";" \
67 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
68 " ${filesize}; save\0" \
69 "updsbf=run loadsbf; run progsbf\0" \
70 "loadsbf=loadb ${loadaddr} ${baudrate};" \
71 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
72 "progsbf=sf probe 0:2 10000 1;" \
74 "sf write ${loadaddr} 0 30000;" \
80 #define CONFIG_SPLASH_SCREEN
81 #define CONFIG_LCD_LOGO
82 #define CONFIG_SHARP_LQ035Q7DH06
87 #define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000
88 #define CONFIG_SYS_USB_EHCI_CPU_INIT
94 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
101 #define CONFIG_SYS_I2C
102 #define CONFIG_SYS_I2C_FSL
103 #define CONFIG_SYS_FSL_I2C_SPEED 80000
104 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
105 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
106 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
108 /* DSPI and Serial Flash */
109 #define CONFIG_CF_SPI
110 #define CONFIG_CF_DSPI
111 #define CONFIG_HARD_SPI
112 #define CONFIG_SYS_SBFHDR_SIZE 0x7
113 #ifdef CONFIG_CMD_SPI
114 # define CONFIG_SYS_DSPI_CS2
116 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
117 DSPI_CTAR_PCSSCK_1CLK | \
118 DSPI_CTAR_PASC(0) | \
120 DSPI_CTAR_CSSCK(0) | \
125 /* Input, PCI, Flexbus, and VCO */
126 #define CONFIG_EXTRA_CLOCK
128 #define CONFIG_SYS_INPUT_CLKSRC 16000000
130 #define CONFIG_PRAM 2048 /* 2048 KB */
132 #define CONFIG_SYS_LONGHELP /* undef to save memory */
134 #if defined(CONFIG_CMD_KGDB)
135 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
137 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
139 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
140 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
141 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
143 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
145 #define CONFIG_SYS_MBAR 0xFC000000
148 * Low Level Configuration Settings
149 * (address mappings, register initial values, etc.)
150 * You should know what you are doing if you make changes here.
154 * Definitions for initial stack pointer and data area (in DPRAM)
156 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
157 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
158 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
159 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
160 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
161 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
164 * Start addresses for the final memory configuration
165 * (Set up by the startup code)
166 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
168 #define CONFIG_SYS_SDRAM_BASE 0x40000000
169 #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
170 #define CONFIG_SYS_SDRAM_CFG1 0x43711630
171 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
172 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
173 #define CONFIG_SYS_SDRAM_EMOD 0x81810000
174 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000
175 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00
177 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
178 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
181 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
183 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
185 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
186 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
187 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
189 /* Initial Memory map for Linux */
190 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
191 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
194 * Configuration for environment
195 * Environment is not embedded in u-boot. First time runing may have env
196 * crc error warning if there is no correct environment on the flash.
199 # define CONFIG_ENV_IS_IN_SPI_FLASH
200 # define CONFIG_ENV_SPI_CS 2
202 # define CONFIG_ENV_IS_IN_FLASH 1
204 #define CONFIG_ENV_OVERWRITE 1
206 /*-----------------------------------------------------------------------
209 #ifdef CONFIG_SYS_STMICRO_BOOT
210 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
211 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
212 # define CONFIG_ENV_OFFSET 0x30000
213 # define CONFIG_ENV_SIZE 0x1000
214 # define CONFIG_ENV_SECT_SIZE 0x10000
216 #ifdef CONFIG_SYS_SPANSION_BOOT
217 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
218 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
219 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
220 # define CONFIG_ENV_SIZE 0x1000
221 # define CONFIG_ENV_SECT_SIZE 0x8000
224 #define CONFIG_SYS_FLASH_CFI
225 #ifdef CONFIG_SYS_FLASH_CFI
226 # define CONFIG_FLASH_CFI_DRIVER 1
227 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
228 # define CONFIG_FLASH_SPANSION_S29WS_N 1
229 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
230 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
231 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
232 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
233 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
234 # define CONFIG_SYS_FLASH_CHECKSUM
235 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
238 #define LDS_BOARD_TEXT \
239 arch/m68k/cpu/mcf5227x/built-in.o (.text*) \
240 arch/m68k/lib/built-in.o (.text*)
243 * This is setting for JFFS2 support in u-boot.
244 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
246 #ifdef CONFIG_CMD_JFFS2
247 # define CONFIG_JFFS2_DEV "nor0"
248 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000)
249 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000)
252 /*-----------------------------------------------------------------------
253 * Cache Configuration
255 #define CONFIG_SYS_CACHELINE_SIZE 16
257 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
258 CONFIG_SYS_INIT_RAM_SIZE - 8)
259 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
260 CONFIG_SYS_INIT_RAM_SIZE - 4)
261 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
262 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
263 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
264 CF_ACR_EN | CF_ACR_SM_ALL)
265 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
266 CF_CACR_DISD | CF_CACR_INVI | \
267 CF_CACR_CEIB | CF_CACR_DCM | \
270 /*-----------------------------------------------------------------------
271 * Memory bank definitions
283 #define CONFIG_SYS_CS0_BASE 0x04000000
284 #define CONFIG_SYS_CS0_MASK 0x00FF0001
285 #define CONFIG_SYS_CS0_CTRL 0x00001FA0
287 #define CONFIG_SYS_CS0_BASE 0x00000000
288 #define CONFIG_SYS_CS0_MASK 0x00FF0001
289 #define CONFIG_SYS_CS0_CTRL 0x00001FA0
292 #endif /* _M52277EVB_H */