2 * Configuation settings for the Freescale MCF5329 FireEngine board.
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
11 * board/config.h - configuration options, board specific
18 * High Level Configuration Options
22 #define CONFIG_MCFUART
23 #define CONFIG_SYS_UART_PORT (0)
25 #undef CONFIG_WATCHDOG
26 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
31 #define CONFIG_BOOTP_BOOTFILESIZE
32 #define CONFIG_BOOTP_BOOTPATH
33 #define CONFIG_BOOTP_GATEWAY
34 #define CONFIG_BOOTP_HOSTNAME
36 /* Command line configuration */
37 #define CONFIG_CMD_PCI
42 # define CONFIG_MII_INIT 1
43 # define CONFIG_SYS_DISCOVER_PHY
44 # define CONFIG_SYS_RX_ETH_BUFFER 8
45 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
47 # define CONFIG_SYS_FEC0_PINMUX 0
48 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
49 # define MCFFEC_TOUT_LOOP 50000
50 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
51 # ifndef CONFIG_SYS_DISCOVER_PHY
52 # define FECDUPLEX FULL
53 # define FECSPEED _100BASET
55 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
56 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
58 # endif /* CONFIG_SYS_DISCOVER_PHY */
66 #define CONFIG_SYS_I2C
67 #define CONFIG_SYS_i2C_FSL
68 #define CONFIG_SYS_FSL_I2C_SPEED 80000
69 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
70 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
71 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
72 #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
73 #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
74 #define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
76 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
77 #define CONFIG_BOOTFILE "u-boot.bin"
79 # define CONFIG_IPADDR 192.162.1.2
80 # define CONFIG_NETMASK 255.255.255.0
81 # define CONFIG_SERVERIP 192.162.1.1
82 # define CONFIG_GATEWAYIP 192.162.1.1
85 #define CONFIG_HOSTNAME M5235EVB
86 #define CONFIG_EXTRA_ENV_SETTINGS \
89 "u-boot=u-boot.bin\0" \
90 "load=tftp ${loadaddr) ${u-boot}\0" \
91 "upd=run load; run prog\0" \
92 "prog=prot off ffe00000 ffe3ffff;" \
93 "era ffe00000 ffe3ffff;" \
94 "cp.b ${loadaddr} ffe00000 ${filesize};"\
98 #define CONFIG_PRAM 512 /* 512 KB */
99 #define CONFIG_SYS_LONGHELP /* undef to save memory */
101 #if defined(CONFIG_KGDB)
102 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
104 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
107 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
108 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
109 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
110 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000)
112 #define CONFIG_SYS_CLK 75000000
113 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
115 #define CONFIG_SYS_MBAR 0x40000000
118 * Low Level Configuration Settings
119 * (address mappings, register initial values, etc.)
120 * You should know what you are doing if you make changes here.
122 /*-----------------------------------------------------------------------
123 * Definitions for initial stack pointer and data area (in DPRAM)
125 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
126 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
127 #define CONFIG_SYS_INIT_RAM_CTRL 0x21
128 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
129 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
131 /*-----------------------------------------------------------------------
132 * Start addresses for the final memory configuration
133 * (Set up by the startup code)
134 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
136 #define CONFIG_SYS_SDRAM_BASE 0x00000000
137 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
139 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
140 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
142 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
143 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
145 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
146 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
149 * For booting Linux, the board info and command line data
150 * have to be in the first 8 MB of memory, since this is
151 * the maximum mapped by the Linux kernel during initialization ??
153 /* Initial Memory map for Linux */
154 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
155 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
157 /*-----------------------------------------------------------------------
160 #define CONFIG_SYS_FLASH_CFI
161 #ifdef CONFIG_SYS_FLASH_CFI
162 # define CONFIG_FLASH_CFI_DRIVER 1
163 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
164 #ifdef NORFLASH_PS32BIT
165 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
167 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
169 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
170 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
171 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
174 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
176 /* Configuration for environment
177 * Environment is embedded in u-boot in the second sector of the flash
179 #define CONFIG_ENV_IS_IN_FLASH 1
181 #define LDS_BOARD_TEXT \
182 . = DEFINED(env_offset) ? env_offset : .; \
183 common/env_embedded.o (.text);
185 #ifdef NORFLASH_PS32BIT
186 # define CONFIG_ENV_OFFSET (0x8000)
187 # define CONFIG_ENV_SIZE 0x4000
188 # define CONFIG_ENV_SECT_SIZE 0x4000
190 # define CONFIG_ENV_OFFSET (0x4000)
191 # define CONFIG_ENV_SIZE 0x2000
192 # define CONFIG_ENV_SECT_SIZE 0x2000
195 /*-----------------------------------------------------------------------
196 * Cache Configuration
198 #define CONFIG_SYS_CACHELINE_SIZE 16
200 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
201 CONFIG_SYS_INIT_RAM_SIZE - 8)
202 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
203 CONFIG_SYS_INIT_RAM_SIZE - 4)
204 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
205 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
206 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
207 CF_ACR_EN | CF_ACR_SM_ALL)
208 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
209 CF_CACR_CEIB | CF_CACR_DCM | \
212 /*-----------------------------------------------------------------------
213 * Chipselect bank definitions
216 * CS0 - NOR Flash 1, 2, 4, or 8MB
225 #ifdef NORFLASH_PS32BIT
226 # define CONFIG_SYS_CS0_BASE 0xFFC00000
227 # define CONFIG_SYS_CS0_MASK 0x003f0001
228 # define CONFIG_SYS_CS0_CTRL 0x00001D00
230 # define CONFIG_SYS_CS0_BASE 0xFFE00000
231 # define CONFIG_SYS_CS0_MASK 0x001f0001
232 # define CONFIG_SYS_CS0_CTRL 0x00001D80
235 #endif /* _M5329EVB_H */