2 * Configuation settings for the Freescale MCF53017EVB.
4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
11 * board/config.h - configuration options, board specific
18 * High Level Configuration Options
22 #define CONFIG_MCFUART
23 #define CONFIG_SYS_UART_PORT (0)
25 #undef CONFIG_WATCHDOG
26 #define CONFIG_WATCHDOG_TIMEOUT 5000
28 /* Command line configuration */
29 #define CONFIG_CMD_REGINFO
31 #define CONFIG_SYS_UNIFY_CACHE
36 # define CONFIG_MII_INIT 1
37 # define CONFIG_SYS_DISCOVER_PHY
38 # define CONFIG_SYS_RX_ETH_BUFFER 8
39 # define CONFIG_SYS_TX_ETH_BUFFER 8
40 # define CONFIG_SYS_FEC_BUF_USE_SRAM
41 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
42 # define CONFIG_HAS_ETH1
44 # define CONFIG_SYS_FEC0_PINMUX 0
45 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
46 # define CONFIG_SYS_FEC1_PINMUX 0
47 # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE
48 # define MCFFEC_TOUT_LOOP 50000
50 # define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2"
52 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
53 # ifndef CONFIG_SYS_DISCOVER_PHY
54 # define FECDUPLEX FULL
55 # define FECSPEED _100BASET
57 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
58 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
60 # endif /* CONFIG_SYS_DISCOVER_PHY */
65 #define CONFIG_SYS_RTC_CNT (0x8000)
66 #define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
73 #define CONFIG_SYS_I2C
74 #define CONFIG_SYS_I2C_FSL
75 #define CONFIG_SYS_FSL_I2C_SPEED 80000
76 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
77 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
78 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
80 #define CONFIG_UDP_CHECKSUM
83 # define CONFIG_IPADDR 192.162.1.2
84 # define CONFIG_NETMASK 255.255.255.0
85 # define CONFIG_SERVERIP 192.162.1.1
86 # define CONFIG_GATEWAYIP 192.162.1.1
89 #define CONFIG_HOSTNAME M53017
90 #define CONFIG_EXTRA_ENV_SETTINGS \
92 "loadaddr=40010000\0" \
93 "u-boot=u-boot.bin\0" \
94 "load=tftp ${loadaddr) ${u-boot}\0" \
95 "upd=run load; run prog\0" \
96 "prog=prot off 0 3ffff;" \
98 "cp.b ${loadaddr} 0 ${filesize};" \
102 #define CONFIG_PRAM 512 /* 512 KB */
103 #define CONFIG_SYS_LONGHELP /* undef to save memory */
105 #ifdef CONFIG_CMD_KGDB
106 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
108 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
111 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
112 #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
113 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */
114 #define CONFIG_SYS_LOAD_ADDR 0x40010000
116 #define CONFIG_SYS_CLK 80000000
117 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
119 #define CONFIG_SYS_MBAR 0xFC000000
122 * Low Level Configuration Settings
123 * (address mappings, register initial values, etc.)
124 * You should know what you are doing if you make changes here.
127 * Definitions for initial stack pointer and data area (in DPRAM)
129 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
130 #define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */
131 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
132 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
133 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
136 * Start addresses for the final memory configuration
137 * (Set up by the startup code)
138 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
140 #define CONFIG_SYS_SDRAM_BASE 0x40000000
141 #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
142 #define CONFIG_SYS_SDRAM_CFG1 0x43711630
143 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
144 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000
145 #define CONFIG_SYS_SDRAM_EMOD 0x80010000
146 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000
148 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
149 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
151 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
152 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
154 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
155 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
158 * For booting Linux, the board info and command line data
159 * have to be in the first 8 MB of memory, since this is
160 * the maximum mapped by the Linux kernel during initialization ??
162 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
163 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
165 /*-----------------------------------------------------------------------
168 #define CONFIG_SYS_FLASH_CFI
169 #ifdef CONFIG_SYS_FLASH_CFI
170 # define CONFIG_FLASH_CFI_DRIVER 1
171 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
172 # define CONFIG_FLASH_SPANSION_S29WS_N 1
173 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
174 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
175 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
176 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
177 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
180 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
182 /* Configuration for environment
183 * Environment is embedded in u-boot in the second sector of the flash
185 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_BASE + 0x40000)
186 #define CONFIG_ENV_SIZE 0x1000
187 #define CONFIG_ENV_SECT_SIZE 0x8000
188 #define CONFIG_ENV_IS_IN_FLASH 1
190 #define LDS_BOARD_TEXT \
191 . = DEFINED(env_offset) ? env_offset : .; \
192 common/env_embedded.o (.text*)
194 /*-----------------------------------------------------------------------
195 * Cache Configuration
197 #define CONFIG_SYS_CACHELINE_SIZE 16
199 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
200 CONFIG_SYS_INIT_RAM_SIZE - 8)
201 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
202 CONFIG_SYS_INIT_RAM_SIZE - 4)
203 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
204 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
205 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
206 CF_ACR_EN | CF_ACR_SM_ALL)
207 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
210 /*-----------------------------------------------------------------------
211 * Chipselect bank definitions
221 #define CONFIG_SYS_CS0_BASE 0
222 #define CONFIG_SYS_CS0_MASK 0x00FF0001
223 #define CONFIG_SYS_CS0_CTRL 0x00001FA0
225 #define CONFIG_SYS_CS1_BASE 0xC0000000
226 #define CONFIG_SYS_CS1_MASK 0x00070001
227 #define CONFIG_SYS_CS1_CTRL 0x00001FA0
229 #endif /* _M53017EVB_H */